JPH05108588A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To easily, speedily and surely detect the reset of the slave device independently of a main device by the own main device without loading burden to the main device. CONSTITUTION:A flip-flop 138 of a slave device 30 is reset by a reset signal (a) impressed from any part excepting for a main device 20. The main device 20 reads the contents of the flip-flop 138 through a BIF (external bus interface) 32 and an ORC (reset instruction detecting circuit) 36 and when the content shows the set state, the slave device 30 judges the slave device 30 is reset by the instruction of any part excepting for the own device. Continuously, the flip-flop 138 is reset through the BIF 32 and the ORC 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a reset state of a slave device by a master device in a multiprocessor system comprising a master device and at least one slave device controlled by the master device. Regarding monitoring method.

[0002]

2. Description of the Related Art In an information processing apparatus, an electronic exchange, and a test apparatus for an electronic exchange, a plurality of devices equipped with a microprocessor are arranged for each function in order to improve the processing capacity as the price of the microprocessor is reduced. The mainstream is a function-distributed multiprocessor configuration or a load-distributed multiprocessor configuration in which a device equipped with the microprocessor is added according to the load.

In such a multiprocessor configuration system, there is a system in which one device serves as a main device and the main device distributes processing to other devices (slave devices) to perform distributed processing. Then, in such a system, there is a mode in which the slave device is not only controlled by the master device but is independently reset.

FIG. 5 is a schematic diagram showing the system configuration of such a conventional apparatus having a multiprocessor configuration. In the figure, the master device 20 and the slave device 30 are connected to each other by a bidirectional external bus 40, and the slave device 30 is a BI device.
Main unit 20 via F (external bus interface) 32
Inputs various commands (order) and various data to be sent to the external bus 40, and the BIF 32 sends these various commands and various data to the MPU (microprocessor) 35 via the internal bus 34. Then, the MPU 35 performs a predetermined process in accordance with various commands and various data input by the MPU 35.

The slave device 30 also sends a reset command sent from the master device 20 via the external bus 40 to the BIF.
It is provided with an ORC (reset instruction detection circuit) 36 that internally resets the slave device 30 via an OR gate 37 when input via 32. Further, the reset instruction signal a output from other than the main device 20 is input to one input terminal of the OR gate 37.
0 is reset independently from other than the main device 20.

[0006]

As described above, in a multiprocessor system in which the slave device 30 is reset independently of the master device 20, conventionally, the slave device 30 is reset by this reset. 20 is not provided, and the slave device 30 is provided on the master device 20 side.
It was not possible to immediately detect that the device was reset independently of its own device. Then, the master device 20 indirectly detects that the slave device 30 has been reset independently of its own device, from an abnormality in the reaction of the slave device 30 with respect to a command sent to the slave device 30, or the like. The main device 20 is
Although this detection is performed by software processing, since this processing is complicated, the processing is a heavy load on the main device 20 side, which is one of the causes of lowering the processing efficiency of the entire system. Further, since the software development is not easy, the software development cost of the master device 20 is also high, and the reset detection of the slave device 30 is an indirect guess, so the reliability (reliability) is high. It was low.

The present invention makes it possible for the master device to detect that the slave device has been reset independently of the master device without burdening the software processing on the master device side with ease, speed, and certainty. The purpose is to do.

[0008]

FIG. 1 illustrates the principle of the present invention. In the present invention, the master device 1 has one or more slave devices 2
It is assumed that a multiprocessor system that controls

Each slave device 2 stores the following storage means 2a.
And a notification means 2b. When the storage unit 2a is reset by a factor other than an instruction from the main device 1, the storage unit 2a stores the reset event.

The notification means 2b notifies the main storage device 1 of the contents stored in the storage means 2a in response to an instruction from the main device 1.
The storage means 2a is composed of, for example, a flip-flop as set forth in claim 2, and the flip-flop is set by a set instruction signal from a device other than the main device 1. Also, for example, as described in claim 3, the main device is set. It is reset by the reset instruction signal from 1.

[0011]

According to the present invention, when the slave device 2 controlled by the master device 1 is reset by a factor other than the instruction by the master device 1, the event is stored in the slave device 2 by the storage means. 2a.

The main device 1 gives a predetermined instruction to the notification means 2b of each slave device 2 which it controls,
The storage contents in the storage means 2a are read from each slave device 2, and it is detected based on the read storage contents that any slave device 2 is reset by an instruction from other than itself.

Therefore, the main device 1 can read the contents stored in the storage means 2a in each slave device 2 controlled by itself by the simple process of reading the contents stored in the storage device 2a via the notification means 2b. The reset independently of the device can be detected easily, quickly and reliably.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a schematic configuration diagram of a multiprocessor system which is an embodiment of the present invention. In the figure, the same symbols are given to the same blocks as the blocks in the conventional multiprocessor system shown in FIG. 5 described above, and the description of the function of each block is omitted because it is redundant.

In this embodiment, an RS-flip-flop 138 (hereinafter simply referred to as a flip-flop 138) for storing that it has been newly reset by an instruction from a device other than the master device 20 is incorporated in the slave device 130. OR to the set terminal S of the flip-flop 138
The output of C36 is input to the reset terminal R of the reset signal a from other than the main device 20, and the output Q of the flip-flop 138 is input to the BIF 32.

That is, in this embodiment, the output Q of the flip-flop 138 is initialized to the L level in advance, and the reset signal a is active (H level) from the device other than the main unit 20 at the set terminal S thereof. When added, the output Q immediately changes to H level. Therefore, the master device 20 reads out the status of the output Q of the flip-flop 138, for example, periodically via the external bus 40 and the BIF 32 to determine whether the slave device 130 has been reset by an instruction from a device other than itself. , Always,
Can be accurately monitored. In the above configuration,
In order to reduce the overhead of the main device 20, if the flip-flop 138 is set to the H level, the BIF
The configuration may be such that 32 interrupts the main device 20.

The master device 20 is the slave device 1 as described above.
When it is detected that 30 is reset from a device other than its own device, the ORC 3 is transmitted via the external bus 40 and the BIF 32.
6 sends a reset command for the device 130 to reset the flip-flop 138 to the L level via the ORC 36.

With such a configuration, the master device 20 can easily, immediately, and surely detect that the slave device 130 has been reset by an instruction from a device other than itself.

Next, FIG. 3 shows a structural example of the slave device 130. In addition to the master device 20, the slave device 130 shown in the figure has a reset key 131 provided in the device itself or a power-on reset circuit 132 that operates by turning on the power.
The internal reset is also performed by the reset key 131 and the power-on reset circuit 132.
Is applied to the set terminal S of the flip-flop 138 as the reset signal a via the OR gate 133.

BIF (external bus interface)
Reference numeral 32 denotes a three-state buffer 32a for inputting data from the external bus 40, a three-state buffer 32b for outputting data to the external bus 40, and an external bus control for controlling the three-state buffers 32a and 32b. It consists of a circuit 32c. The output of the three-state buffer 32a is input to the ORC (reset instruction detection circuit) 36, and the Q output of the flip-flop 138 is input to the input terminal of the three-state buffer 32b.

Further, the MPU 35 is connected to the internal bus 34.
Besides, ROM (Read Only Memory) 134, R
AM (random access memory) 135 and I /
An O (input / output device) 136 is connected. Then, the reset signal b output from the OR gate 37 inside the device
Are input to the MPU 35 and the I / O 136.

That is, the slave device 130 is adapted to be internally reset by the operation of turning on the reset key 131 or turning on the power source. When these operations are performed, the flip-flop 1 is operated via the OR gate 133.
38 is set to H level, and its flip-flop 1
The set state of 38, that is, the internal reset of the slave device 130 is read by the main device 20 via the three-state buffer 32b of the BIF 32 and the external bus 40. As a result, the master device 20 can detect (recognize) that the slave device 130 has been reset due to a factor that is not expected by itself, and the master device 20 can
After the detection, a reset command is sent to the slave device 130 via the external bus 40, the flip-flop 138 is reset to the L level again via the three-state buffer 32a of the BIF 32 and the ORC 36, and the next slave device 130 is reset.
Prepare for detection of internal reset of.

Next, FIG. 4 shows an application example in which the present invention is applied to the test apparatus 300 of the exchange 200. Test equipment 30
0 is a master device 310 having a microprocessor, and slave devices 320-1, 320-2, ...
.. 320-N, and the main device 310 and the N slave devices 320-1, 320-2, ... 320-N are connected by an external bus. Each of the slave devices 320-1, 320-2, ... 320-N is assigned to its own device by an instruction (order: ORDER) transmitted from the master device 310 via the external bus.
00 various maintenance tests (call path test, subscriber line test, etc.), and the test results (answer: ANSWER) are returned to the main unit 310 via an external bus. In the above configuration, in the slave devices 310-1, 310-2, ... 310-N,
The circuit shown in FIG. 3 is provided, and the master device 310, in the same manner as described above, connects each slave device 310- through the external bus.
It is detected that 1, 310-2, ... 310-N are reset independently of the own device.

In the above embodiment, the test apparatus 300 of the exchange 200 is shown as an example of the system to which the present invention is applied, but the present invention is not limited to this, and at least one main device is provided. It can be applied to all devices having a multiprocessor system configuration for controlling the slave device.

[0025]

As described above, according to the present invention,
The slave device is provided with a means for storing the event when it is reset by an instruction command from a device other than the main device, and the master device can easily read the contents of the storage means in the slave device. Without imposing a heavy load on the software processing of the device, the master device should be able to reset all slave devices that it controls independently of its own device due to factors other than its own instruction. Easy,
It enables quick and reliable detection.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a schematic configuration diagram of a multiprocessor system that is an embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a slave device.

FIG. 4 is a system configuration diagram of a test apparatus for an exchange, which is an application example of the present invention.

FIG. 5 is a schematic configuration diagram of a conventional multiprocessor system.

[Explanation of symbols]

 1 main device 2 slave device 2a storage means 2b notification means

Claims (3)

[Claims] 1. A master device (1) comprising one or more slave devices (2).
In the multiprocessor system for controlling the above, when the slave device (2) is reset by a factor other than an instruction from the main device (1), a storage means (2a) for storing the reset event, According to an instruction from the main device (1), the storage means (2
A multiprocessor system comprising: a notification unit (2b) for notifying the main device (1) of the stored contents of a). 2. The multiprocessor system according to claim 1, wherein said storage means (2a) is a flip-flop set by a set instruction signal from other than said main unit (1). 3. The microprocessor system according to claim 2, wherein the flip-flop is reset by a reset instruction signal from the main unit (1).