JPH01279355A - Access processing system for direct memory access controller - Google Patents

Abstract

PURPOSE:To improve the hard access processing speed by adding a fault detecting process to a direct memory access DMA controller and at the same time turning the fault processing into blocks via the software. CONSTITUTION:An order sending means 2 sends the memory address order and the memory value order to a DMA controller 7. Thus the controller 7 sends these received orders to a peripheral device 11. If the abnormality occurs under such conditions, this abnormality is detected by a fault detecting circuit 9 of the controller 7 and sets the results of said fault at a fault memory 10 and a soft informing flip-flop group FFG 6 of a CPU 1. While the CPU 1 monitors the fault result set at the FFG 6 via a fault monitor means 4 for programs. Then the CPU 1 sets the result of a fault if detected at a sending result memory 3. Thus the means 2 starts a fault processing step according to the result of the memory 3 and performs the retry or the switch of the memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an access processing method for a direct memory access control device that controls the transmission and reception of a large amount of data from a main storage device of an electronic exchange to a peripheral device.

[Conventional technology]

Conventionally, the access processing method for a direct memory access device consists of three order transmissions9, the first of which is transmission of an order of the start address of the access memory, the second is transmission of an order of the memory amount of the access memory, and the second is transmission of an order of the memory amount of the access memory. 3 was to send out the read order of the access result.

[Problem to be solved by the invention]

The access processing method of the conventional direct memory access control device described above, especially data transmission and reception control, is as follows:
Despite the fact that the probability of failure occurring is very low due to quality improvement, access result orders are sent every time transmission and reception control is performed, which reduces the processing capacity of the central processing unit. It also has the disadvantage of increasing access time.

[Means to solve the problem]

In the access processing method of the direct memory access control device according to the present invention, when the direct memory access control device detects that a hardware failure factor has occurred, it notifies the central control device by setting a software notification FFG; Each time the central processing unit executes an instruction to control the direct memory access control device, failure processing is performed without determining the control result.

[Effect]

This invention can improve the hard access processing speed by blocking failure processing using software.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of an access processing method of a direct memory access control device according to the present invention. In the figure, reference numeral 1 indicates an order sending means 21 for sending out orders such as memory address order and memory amount order, and 3 sending result memory 3. Software program fault monitoring means 4. A group of flip-flops that can be read and written by the fault processing means 5 and program processing (hereinafter simply referred to as software notification FFG)
6, T is an order sending circuit 8. A direct memory access control device includes a fault detection circuit 9 and a faulty memory 10, and 11 is a peripheral device.

Next, the operation of the access processing device of the direct memory access control device having the above configuration will be explained with reference to the flowchart shown in FIG. First, in order sending step S1, the order sending means 2 sends a memory address order and a memory amount order to the direct memory access control device 7 for direct memory access from the central processing unit 1. 7 is this memory address order and memo IJ
- Send the i order to the peripheral device 11. Then, this direct memory access control device 7 judges the sending result in step S2, and when an abnormality occurs, the fault detection circuit 9 detects the abnormality and sends the fault memory 10 and the software notification FFG 6 of the central processing unit 1. The failure result is set. Then, in the fault monitoring step S3, the central processing unit 1 uses the fault monitoring means 4 of the software program to monitor the fault result set in the software notification FFG 6. If there is a failure, it is set in the sending result memory 3 of the order sending means 2. Then, the order sending means 2 starts the failure processing step S4 based on the memory result. In this failure processing step S, a read order for the failure memory 10 is sent out, and depending on the result, a retry or switching can be performed.

〔Effect of the invention〕

As explained in detail above, according to the access processing method of the direct memory access control device according to the present invention,
While the fault detection process is provided in the direct memory access control device, the hardware access processing speed can be improved by blocking the fault process using software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an access processing method of a direct memory access control device according to the present invention, and FIG.
The figure is a flowchart for explaining the operation of FIG. 1...Central processing unit, 2...Order sending means,
3... Sending result memory, 4... Fault monitoring means,
5...Fault processing means, 6...-Lip 70 tag group (FFG for software notification), 7...Direct memory access control device, 8...Order sending circuit, 9
...fault detection circuit, 10...fault memory, 11
...Peripheral equipment.

Claims (1)

[Claims] In the processing method of a direct memory access control device that directly transmits and receives data between the main storage device of an electronic exchange and peripheral devices, the central control device of the electronic exchange is equipped with a group of flip-flops that can be read and written by program processing. The direct memory access control device is provided with a setting means for setting information at the time of failure detection in the flip-flop group, and the direct memory access control device sets the flip-flop group when the direct memory access control device detects that a hard access failure factor has occurred. Therefore, the direct memory access is characterized by notifying the central control unit of the electronic exchange and handling the failure without determining the control result every time the central processing unit executes an instruction to control the direct memory access control unit. Control device access processing method.