JPH05101673A - Program circuit - Google Patents

Program circuit

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Publication number
JPH05101673A
JPH05101673A JP26018191A JP26018191A JPH05101673A JP H05101673 A JPH05101673 A JP H05101673A JP 26018191 A JP26018191 A JP 26018191A JP 26018191 A JP26018191 A JP 26018191A JP H05101673 A JPH05101673 A JP H05101673A
Authority
JP
Japan
Prior art keywords
fuse
level
output
circuit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26018191A
Other languages
Japanese (ja)
Other versions
JP2994114B2 (en
Inventor
Shogo Tanabe
昇吾 田▲邉▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP26018191A priority Critical patent/JP2994114B2/en
Publication of JPH05101673A publication Critical patent/JPH05101673A/en
Application granted granted Critical
Publication of JP2994114B2 publication Critical patent/JP2994114B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Read Only Memory (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To eliminate a minute leak current which flows in the case that a polysilicon fuse which should have been disconnected by a lser is connected with a high resistance. CONSTITUTION:A power source Vcc and a fuse F are connected with a P-type MOS transistor TR T4 between them, and the source of the TR T4 is connected to an output out, and a set circuit A is used to initialize the level of a nodal point N at the time of power-on. Even if the fuse P which should be disconnected is connected to a high resistance R, the TR T4 is turned off by going of the out of output to the high level, and the DC current flowing through the fuse F connected with the high resistance in a conventional circuit is cut off by the TR T4 and disappears.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体記憶回路のプログ
ラム回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program circuit of a semiconductor memory circuit.

【０００２】[0002]

【従来の技術】従来のプログラム回路の構成及び動作
を、図３を用いて説明する。2. Description of the Related Art The structure and operation of a conventional program circuit will be described with reference to FIG.

【０００３】図３において、Ｎ型ＭＯＳトランジスタＴ
1 ，Ｔ2と、Ｐ型ＭＯＳトランジスタＴ3 と、ポリシリ
コンヒューズＦと、高抵抗素子Ｒとを有し、節点Ｎはト
ランジスタＴ3 ，Ｔ2 のゲート入力である。In FIG. 3, an N-type MOS transistor T
1 and T 2 , a P-type MOS transistor T 3 , a polysilicon fuse F, and a high resistance element R, and a node N is a gate input of the transistors T 3 and T 2 .

【０００４】図３のプログラム回路では、ヒューズＦを
介して節点ＮはＶｃｃ電源からの電荷の供給によりＶｃ
ｃ電源の電位まで上昇する為、Ｐ型ＭＯＳトランジスタ
Ｔ3 はＯＦＦ，Ｎ型ＭＯＳトランジスタＴ2 はＯＮにな
り、プログラム回路の出力ｏｕｔはＧＮＤレベルにな
る。この為、Ｎ型ＭＯＳトランジスタＴ1 はＯＦＦにな
るので、出力ｏｕｔは常に低（ＬＯＷ）レベルに保持さ
れる。In the program circuit shown in FIG. 3, the node N is supplied to the Vc power source through the fuse F by supplying electric charge from the Vcc power source.
Since the potential of the power source c is increased, the P-type MOS transistor T 3 is turned off, the N-type MOS transistor T 2 is turned on, and the output out of the program circuit becomes the GND level. Therefore, the N-type MOS transistor T 1 is turned off, and the output out is always held at the low (LOW) level.

【０００５】また、ポリシリコンヒューズＦをレーザで
切断すると、節点ＮはＶｃｃ電源から電荷が供給されな
い為、節点ＮはＬＯＷレベルになり、Ｐ型ＭＯＳトラン
ジスタＴ3 はＯＮ、Ｎ型ＭＯＳトランジスタＴ2 はＯＦ
Ｆになるので、出力ｏｕｔはＨＩＧＨレベルが出力さ
れ、Ｎ型ＭＯＳトランジスタＴ1 はＯＮし、出力ｏｕｔ
は常にＨＩＧＨレベルに保持される。Further, when the polysilicon fuse F is cut by a laser, no electric charge is supplied to the node N from the Vcc power source, so that the node N becomes LOW level, the P-type MOS transistor T 3 is turned on, and the N-type MOS transistor T 2 is turned on. Is OF
Since it becomes F, the output out is at a high level, the N-type MOS transistor T 1 is turned on, and the output out
Is always held at the HIGH level.

【０００６】このようにプログラム回路はヒューズＦの
素子をレーザで切断する事で出力ｏｕｔのレベルを切り
換える事が出来る。As described above, the program circuit can switch the level of the output out by cutting the element of the fuse F with the laser.

【０００７】[0007]

【発明が解決しようとする課題】従来のプログラム回路
では、ヒューズＦをレーザで切断すると、プログラム回
路の出力レベルは変換されるが、レーザ光線の強さある
いはポリシリコンヒューズＦの膜厚や幅等の製造上のバ
ラツキによって切断したはずのヒューズが完全に切断さ
れず高抵抗でつながっている場合がある。In the conventional program circuit, when the fuse F is cut by a laser, the output level of the program circuit is converted, but the intensity of the laser beam or the film thickness and width of the polysilicon fuse F, etc. The fuse that should have been cut may not be completely cut due to manufacturing variations, and may be connected with high resistance.

【０００８】この様な場合、回路上の動作は正常に行う
が高抵抗のヒューズＦの素子に流れる微少な電流により
節点Ｎは電位が上る。この対策として、従来の回路で
は、節点Ｎの電位が上昇しなくする為、高抵抗素子Ｒを
接続する事で高抵抗でつながっているヒューズ素子を通
して流れる微少な電流をＧＮＤの電源に流していた。し
かしながら、近年ますます低電流化が進む一方、高集積
化が進み、この様な微少電流は低電流化の妨げとなって
いた。In such a case, the circuit operates normally, but the potential of the node N rises due to the minute current flowing through the element of the high resistance fuse F. As a countermeasure against this, in the conventional circuit, in order to prevent the potential of the node N from rising, a minute current flowing through the fuse element connected by the high resistance is supplied to the GND power source by connecting the high resistance element R. .. However, in recent years, as the current has been further reduced, high integration has been advanced, and such a minute current has been an obstacle to the reduction of current.

【０００９】本発明の目的は、前記問題点を解決し、微
少電流を流す必要のないようにしたプログラム回路を提
供することにある。An object of the present invention is to solve the above-mentioned problems and to provide a program circuit in which it is unnecessary to pass a minute current.

【００１０】[0010]

【課題を解決するための手段】本発明のプログラム回路
の構成は、インバータを設け、第１のトランジスタ，ヒ
ューズ素子，第２のトランジスタの直列体を設け、前記
第１，第２のトランジスタのゲートを前記インバータの
出力端子に接続し、前記ヒューズ素子の前記第２のトラ
ンジスタとの共通接続点と前記インバータの入力とを共
通接続して節点となし、前記第２のトランジスタと並列
に抵抗を接続し、前記節点に単安定マルチバイブレータ
の出力が接続されていることを特徴とする。According to the configuration of a program circuit of the present invention, an inverter is provided, a series body of a first transistor, a fuse element, and a second transistor is provided, and the gates of the first and second transistors are provided. Is connected to the output terminal of the inverter, the common connection point of the fuse element with the second transistor and the input of the inverter are commonly connected to form a node, and a resistor is connected in parallel with the second transistor. However, the output of the monostable multivibrator is connected to the node.

【００１１】[0011]

【実施例】図１は本発明の一実施例のプログラム回路を
示す回路図である。1 is a circuit diagram showing a program circuit according to an embodiment of the present invention.

【００１２】図１において、本実施例のプログラム回路
は、Ｎ型ＭＯＳトランジスタＴ1 ，Ｔ2 と、Ｐ型ＭＯＳ
トランジスタＴ3 ，Ｔ4 と、ヒューズ素子Ｆと、抵抗Ｒ
と、プログラム回路の出力端子ｏｕｔと、セット回路Ａ
とを備えている。Referring to FIG. 1, the program circuit of this embodiment includes N-type MOS transistors T 1 and T 2 and a P-type MOS transistor.
Transistors T 3 and T 4 , fuse element F, and resistor R
And the output terminal out of the program circuit and the set circuit A
It has and.

【００１３】本発明の実施例と、前記した従来例の構成
上の相違点は、Ｖｃｃ電源端子とヒューズＦの素子をＰ
型ＭＯＳトランジスタＴ4 を介して接続し、かつゲート
端子をプログラム回路の出力端子ｏｕｔに接続した点
と、セット回路Ａを備えている点である。The difference between the embodiment of the present invention and the above-mentioned conventional example is that the elements of the Vcc power supply terminal and the fuse F are P-type.
Type MOS transistor T 4 and the gate terminal is connected to the output terminal out of the program circuit, and the set circuit A is provided.

【００１４】図２は本発明の一実施例の各部の波形図で
ある。図２において、セット回路Ａは、（ａ），（ｂ）
に示すように、Ｖｃｃ電源を投入すると、ワンショット
パルスを発生する回路が好ましい。FIG. 2 is a waveform diagram of each part of one embodiment of the present invention. In FIG. 2, the set circuit A includes (a) and (b).
As shown in, a circuit that generates a one-shot pulse when the Vcc power supply is turned on is preferable.

【００１５】次に本発明の実施例の動作について図１，
図２を用いて説明すると、まずヒューズＦを切断してな
い時、電源を投入（ＯＮ）するとセット回路Ａからの出
力はＬＯＷであり、また接点ＮのレベルはＬＯＷとな
り、トランジスタＴ3 ，Ｔ2 はＯＮ，ＯＦＦとなり、出
力ｏｕｔはＨＩＧＨレベルとなり、トランジスタＴ1 ，
Ｔ4 はＯＮ，ＯＦＦとなる。Next, the operation of the embodiment of the present invention will be described with reference to FIG.
Referring to FIG. 2, first, when the power is turned on (ON) when the fuse F is not cut, the output from the set circuit A is LOW, and the level of the contact N is LOW, so that the transistors T 3 , T 2 is ON and OFF, the output out is HIGH level, and the transistor T 1 ,
T 4 is ON, turned OFF.

【００１６】その後、セット回路Ａの出力は一定時間Ｈ
ＩＧＨレベルが出力される。この為一時的に節点Ｎは一
時的にＨＩＧＨレベルになり、トランジスタＴ3 ，Ｔ2
はＯＦＦ，ＯＮに変り、出力ｏｕｔのレベルはＨＩＧＨ
からＬＯＷに変化しトランジスタＴ4 ，Ｔ1 はＯＮ，Ｏ
ＦＦになる。After that, the output of the set circuit A is H for a certain period of time.
The IGH level is output. Therefore, the node N temporarily becomes HIGH level temporarily, and the transistors T 3 and T 2
Changes to OFF and ON, and the level of output out is HIGH
Changes from LOW to LOW and the transistors T 4 and T 1 are ON and O
Become FF.

【００１７】セット回路Ａの出力は、再びＬＯＷになる
が、トランジスタＴ4 がＯＮしている為、節点Ｎのレベ
ルはＶｃｃ電源から電荷が供給される。この為、ＨＩＧ
Ｈレベルが保たれ続ける。The output of the set circuit A becomes LOW again, but since the transistor T 4 is on, the level of the node N is supplied with electric charges from the Vcc power supply. Therefore, HIG
H level continues to be maintained.

【００１８】よって、図２の（ｃ）に示すように、プロ
グラム回路の出力ｏｕｔはＬＯＷレベルを保持した状態
となる。Therefore, as shown in FIG. 2 (c), the output out of the program circuit is kept at the LOW level.

【００１９】一方、図１のヒューズＦの素子を切断した
場合の動作を説明すると、セット回路Ａの動作はヒュー
ズＦを切断してない場合と同じであるから、電源投入時
は節点ＮはＬＯＷレベルである。出力ｏｕｔのレベルは
ＨＩＧＨとなり、トランジスタＴ4 ，Ｔ1 はＯＦＦ，Ｏ
Ｎとなる。On the other hand, the operation when the element of the fuse F in FIG. 1 is cut will be described. Since the operation of the set circuit A is the same as when the fuse F is not cut, the node N is LOW when the power is turned on. It is a level. The level of the output out becomes HIGH, and the transistors T 4 and T 1 are OFF and O
N.

【００２０】その後、セット回路Ａの出力はＬＯＷから
一定時間ＨＩＧＨに変化する為、節点ＮのレベルはＬＯ
ＷからＨＩＧＨになり、出力ｏｕｔは一定時間ＬＯＷに
なり、トランジスタＴ4 ，Ｔ1 はＯＮ，ＯＦＦになる
が、ヒューズＦは切断してある為、トランジスタＴ4 を
通して流れる電流はない。After that, since the output of the set circuit A changes from LOW to HIGH for a certain time, the level of the node N becomes LO.
The output W goes HIGH for a certain period of time, the output OUT goes LOW for a certain period of time, and the transistors T 4 and T 1 are turned ON and OFF, but since the fuse F is cut off, there is no current flowing through the transistor T 4 .

【００２１】再び、セット回路Ａの出力はＨＩＧＨから
ＬＯＷレベルになり、以後ＬＯＷレベルを保つ事より、
節点ＮのレベルはＬＯＷとなるから、図２の（ｄ）に示
すように出力ｏｕｔはＨＩＧＨレベルを保持し続ける。Again, the output of the set circuit A changes from HIGH to LOW level, and thereafter maintains LOW level.
Since the level of the node N becomes LOW, the output out continues to hold the HIGH level as shown in (d) of FIG.

【００２２】これより、トランジスタＴ4 がＯＦＦする
為、ヒューズＦが完全に切れずに残っていても、従来流
れていた微少電流をまったく流さずに、従来のプログラ
ム回路と同様の動作を行う事が出来る。As a result, since the transistor T 4 is turned off, even if the fuse F is not completely cut off and remains, the same operation as that of the conventional program circuit is performed without supplying the minute current which has been conventionally flowing. Can be done.

【００２３】[0023]

【発明の効果】以上説明したように、本発明は、たとえ
ば切断されたヒューズが高抵抗でつながっている場合、
従来では流れていた微少電流を、ＭＯＳトランジスタを
制御する事で消滅出来るという効果がある。As described above, according to the present invention, when a blown fuse is connected with high resistance,
There is an effect that the minute current that has conventionally flowed can be extinguished by controlling the MOS transistor.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例のプログラム回路を示す回路
図である。FIG. 1 is a circuit diagram showing a program circuit according to an embodiment of the present invention.

【図２】図１の各部の動作状態を示す波形図である。FIG. 2 is a waveform diagram showing an operating state of each unit in FIG.

【図３】従来のプログラム回路を示す回路図である。FIG. 3 is a circuit diagram showing a conventional program circuit.

【符号の説明】[Explanation of symbols]

Ｆ ポリシリコンヒューズ Ｔ1 ，Ｔ2 Ｎ型ＭＯＳトランジスタ Ｔ3 ，Ｔ4 Ｐ型ＭＯＳトランジスタ Ｒ 高抵抗素子 ｏｕｔ プログラム回路の出力 Ａ セット回路F Polysilicon fuse T 1 , T 2 N-type MOS transistor T 3 , T 4 P-type MOS transistor R High resistance element out Program circuit output A set circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 インバータを設け、第１のトランジス
タ，ヒューズ素子，第２のトランジスタの直列体を設
け、前記第１，第２のトランジスタのゲートを前記イン
バータの出力端子に接続し、前記ヒューズ素子の前記第
２のトランジスタとの共通接続点と前記インバータの入
力とを共通接続して節点となし、前記第２のトランジス
タと並列に抵抗を接続し、前記節点に単安定マルチバイ
ブレータの出力が接続されていることを特徴とするプロ
グラム回路。1. An inverter is provided, a series body of a first transistor, a fuse element, and a second transistor is provided, and gates of the first and second transistors are connected to an output terminal of the inverter, and the fuse element is provided. A common connection point with the second transistor and the input of the inverter are commonly connected to form a node, a resistor is connected in parallel with the second transistor, and the output of the monostable multivibrator is connected to the node. A program circuit characterized by being provided.
JP26018191A 1991-10-08 1991-10-08 Program circuit Expired - Lifetime JP2994114B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26018191A JP2994114B2 (en) 1991-10-08 1991-10-08 Program circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26018191A JP2994114B2 (en) 1991-10-08 1991-10-08 Program circuit

Publications (2)

Publication Number Publication Date
JPH05101673A true JPH05101673A (en) 1993-04-23
JP2994114B2 JP2994114B2 (en) 1999-12-27

Family

ID=17344453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26018191A Expired - Lifetime JP2994114B2 (en) 1991-10-08 1991-10-08 Program circuit

Country Status (1)

Country Link
JP (1) JP2994114B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321654B1 (en) * 1998-07-06 2002-01-24 가네꼬 히사시 Fuse circuit and redundant decoder
JP2002298594A (en) * 2001-03-30 2002-10-11 Fujitsu Ltd Address generating circuit
KR100570204B1 (en) * 1999-03-23 2006-04-12 주식회사 하이닉스반도체 Repair circuit of memory device
JP2010170636A (en) * 2009-01-26 2010-08-05 Fujitsu Semiconductor Ltd Semiconductor device, control method thereof, and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321654B1 (en) * 1998-07-06 2002-01-24 가네꼬 히사시 Fuse circuit and redundant decoder
KR100570204B1 (en) * 1999-03-23 2006-04-12 주식회사 하이닉스반도체 Repair circuit of memory device
JP2002298594A (en) * 2001-03-30 2002-10-11 Fujitsu Ltd Address generating circuit
JP2010170636A (en) * 2009-01-26 2010-08-05 Fujitsu Semiconductor Ltd Semiconductor device, control method thereof, and electronic device

Also Published As

Publication number Publication date
JP2994114B2 (en) 1999-12-27

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