JP2964775B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reference voltage generating circuit, and more particularly to a reference voltage generating circuit formed on a semiconductor integrated circuit manufactured by a MOS transistor process.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4B, this type of reference voltage generating circuit includes PMOS transistors 36 and 37 having the same gate size and NMOS transistors 39 and 40 having the same gate size.
A mirror circuit comprising: a PMOS transistor 38;
It comprises a resistor 41, a resistor 44 having a resistance several times the resistance 41, and diodes 42, 43 and 45. Note that the diodes 42 and 45 are generally formed by connecting one or more diodes in parallel, respectively, but in FIG.
Only one diode is shown. In FIG. 4B, the current flowing through the PMOS transistor 36, the NMOS transistor 39, the resistor 41 and the diode 42 is represented by I
_1, and when the current flowing through the PMOS transistor 37, NMOS transistor 37 and diode 43 and I _2, the relationship of these currents I ₁ and I ₂ is as shown in FIG.

In this case, the mirror circuit composed of the PMOS transistors 36 and 37 and the NMOS transistors 39 and 40 operates so that the currents I ₁ and I ₂ have the same current value. As shown in FIG. Accordingly, in the circuit including the resistor 41 and the diodes 42 and 42, the contact between the NMOS transistor 39 and the resistor 41 and the contact between the NMOS transistor 40 and the diode 43 are formed by the operation of the mirror circuit described above. Assuming that the same voltage is applied and the diode 42 is configured by connecting the same diode as the diode 43 in n pieces in parallel, the following equation is established.

[0004] _{RI 1 + V T ln (I} 1 / nI s) = V T ln (I 2 / I s) ...... (1) where the resistance value of R is the resistance 41, I _s is the diode saturation current, V _T is a constant expressed as V _T = kT / q, k is the Portsman constant, T is the absolute temperature, and q
Is the elementary charge.

When the above equation (1) is solved for I ₂ , the following equation is obtained.

I ₂ = (I ₁ / n) exp (RI ₁ / V _T ) (2) The relationship of the above equation (2) is shown by 202 in FIG. Accordingly, in the actual operation state in the conventional example of FIG. 4B, a current corresponding to the intersection of the straight line 201 and the curve 202 of FIG. 3 flows. In this case, since the same current flows through the resistor 44 and the diode 45 by the PMOS transistor 38, the output terminal 60 connected to the contact point between the PMOS transistor 38 and the resistor 44 provides a reference having less dependence on the power supply voltage and temperature fluctuation. A voltage 106 is obtained.

In the conventional example shown in FIG. 4A, the PMOS transistors 25, 38 corresponding to the PMOS transistors 36, 37 and 38 in the conventional reference voltage generating circuit shown in FIG. The drains are connected to the gates of the gates 26 and 27, the source is connected to the power supply, and the gate is connected to the standby terminal 58.
A MOS transistor 30 is additionally provided, and when the standby signal 104 becomes “0” level, the PM
The gates of the OS transistors 25, 26 and 27 are PM
By reducing the current flowing through each stage to 0 by short-circuiting to the power supply through the OS transistor 30, current consumption during standby is reduced.

[0008]

In the above-mentioned conventional reference voltage generating circuit, as shown in FIG. 3, a current flows through each stage indicated by a point 204 in addition to an operating point 203 to be operated. There are no operating points. Therefore, FIG.
In the reference voltage generation circuit having the standby function shown in FIG. 7, the standby signal 104 becomes "0" level, and the gates of the PMOS transistors 25, 26 and 27 are short-circuited by the PMOS transistor 30, and the current of each stage becomes 0. The standby signal 1
04 becomes “1” level and the PMOS transistor 2
Even if the gates of 5, 26 and 27 are disconnected from the power supply, the potential at the node M does not decrease moderately due to the presence of the operating point indicated by the point 204 in FIG. Has the disadvantage of being delayed.

Further, in some cases, the leakage current in each MOS transistor exceeds the operating current, so that even in a reference voltage generating circuit having no standby function as shown in FIG. As in the case where the power supply voltage rises, there is a disadvantage that the generation of the reference voltage to be output is delayed or not output at all.

[0010]

According to a first aspect of the present invention, there is provided a reference voltage generating circuit in which a source is connected to a first power supply, and gates are commonly connected to each other. A fourth MOS transistor having a source connected to the first power supply, a gate connected to the standby terminal, and a drain connected to the gates of the first, second and third first conductivity type MOS transistors; First conductivity type MOS
A predetermined standby signal that is inserted and connected between the transistor, the drain of the first first conductivity type MOS transistor, and the gates of the first, second, and third first conductivity type MOS transistors; A transfer gate that is turned on / off by an inversion signal of the standby signal, a drain is connected to the drain of the first first conductivity type MOS transistor, a gate is connected to the standby inversion terminal, and a source is the second. First connected to power supply
And a second second MOS transistor having a drain connected to the drain of the first first conductivity type MOS transistor and a gate connected to the drain of the second first conductivity type MOS transistor. A conductivity type MOS transistor, a third second conductivity type MOS transistor having a drain and a gate commonly connected to a gate of the second second conductivity type MOS transistor, and a second second conductivity type MOS transistor. A first resistor and N (an integer of 1 or more) parallel diodes connected in series between the source and the second power supply, and the third second conductivity type MO
A second diode connected in series between a source of the S transistor and the second power supply, a drain of the third first conductivity type MOS transistor, and the second power supply; , And at least N (an integer of 1 or more) parallel diodes.
A connection point between the drain of the conductive type MOS transistor and the second resistor is used as an output terminal.

Further, a reference voltage generating circuit according to a second aspect of the present invention comprises:
A depletion second conductivity type MOS transistor having a drain connected to the first power supply and a gate connected to the second power supply, and a source connected to the second power supply,
The first, second and third gates are commonly connected.
The second conductivity type MOS transistor and the drain is the first
The gates of the second and third second conductivity type MOS transistors are connected to each other, and the gates are connected to the source of the depletion second conductivity type MOS transistor and the second second conductivity type M transistor.
The first connected to both the drain of the OS transistor
And a drain and a gate connected to both the source of the depletion second conductivity type MOS transistor and the drain of the second second conductivity type MOS transistor. Connected to the gate of the first conductivity type MOS transistor.
N (an integer of 1 or more) parallel diodes connected in series between a first conductivity type MOS transistor, the first power supply, and a source of the first first conductivity type MOS transistor; A first resistor, the first power supply,
A diode connected between the source of the second first conductivity type MOS transistor, a first power supply, and a series connection between the drain of the third second conductivity type MOS transistor; At least N (an integer of 1 or more) parallel diodes and a second resistor are provided, and a connection point between the second resistor and the drain of the third second conductivity type MOS transistor is used as an output terminal. It is characterized by.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment is an example of a reference voltage generation circuit having a standby function, and includes a mirror circuit including PMOS transistors 1 and 2 having the same gate size and NMOS transistors 4 and 5 having the same gate size. , A gate of which is connected to a standby inverting terminal, a drain of which is connected to a drain of the PMOS transistor 1 and a source of which is grounded; a PMOS transistor 8 having the same gate size as the PMOS transistors 1 and 2;
A transfer gate 6 inserted and connected between the drain of the transistor 1 and the gates of the PMOS transistors 2 and 8; a source connected to the power supply;
A PMOS connected to the gates of the OS transistors 1, 2 and 3 and having the gate connected to the standby terminal 54;
A transistor 7; a resistor 9; a resistor 12 having a resistance value several times as large as the resistor 9;
3 is provided. The diodes 10 and 13 are generally formed by connecting one or more diodes in parallel. However, in FIG. 1, only one diode is shown for simplicity.

In FIG. 1, at the time of standby, a standby signal 101 ("0" level) is input from standby terminals 53 and 54, and an inverted standby signal 10 is input from standby inverting terminals 51 and 52.
2 (“1” level) is input. With this, PMO
Although the S transistor 7 is turned on, the transfer gate 6 is turned off, and the contact M is disconnected from the power supply. The contact M is connected to the ground via the NMOS transistor 3. Therefore, when the standby signal 101 changes from the “0” level to the “1” level and the reference voltage generation circuit shifts from the standby state to the operation state, a finite potential difference is generated between the contact M and the power supply. Then, a finite current flows through the PMOS transistors 1, 2, and 8, respectively. As a result, in the case of the present embodiment, the operating state indicated by the operating point 204 in FIG.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the present invention. This embodiment is an example of a reference voltage generating circuit having no standby function. The mirror circuit includes PMOS transistors 15 and 16 having the same gate size and NMOS transistors 17 and 18 having the same gate size, and the gate is connected to the ground point. A depletion NMOS transistor 14 having a drain connected to the power supply and a source connected to the gates of the PMOS transistors 15 and 16, and NMOS transistors 17 and 1
8, the gate size is equal, the drain is connected to the output terminal 57, and the gates are NMOS transistors 17 and 1.
An NMOS transistor 19 connected to the gate of E.8 and having a source connected to ground; diodes 20, 22 and 23 each connected in a forward direction to the power supply;
It is configured to include a resistor 21 and a resistor 24 having a resistance value several times that of the resistor 21. Note that the diodes 20 and 2 are similar to those in the conventional example and the first embodiment.
In general, each diode 3 is formed by connecting one or more diodes in parallel, but in FIG. 1, only one diode is shown for simplicity.

In FIG. 2, the threshold voltage of the depletion NMOS transistor 14 is set to a value substantially equal to 0 V, and the potential of the contact M remains 0 V when the power supply voltage rises. , A current flows through the depletion NMOS transistor 14, whereby the potential of the contact M is pulled up and a current flows through the PMOS transistors 15 and 16. The operation state of the reference voltage generation circuit is at the operation point 204 in FIG. The operation state shifts from the operation point indicated by the arrow to the operation state indicated by the operation point 203.
Accordingly, the entire reference voltage generating circuit operates at the expected operating point, and when the potential of the contact M rises to a potential sufficiently higher than the potential of the ground point, the current flowing through the depletion NMOS transistor 14 is reduced. This is a sufficiently small value, and hardly affects the reference voltage generating circuit during normal operation.

[0017]

As described above, when the present invention is applied to a reference voltage generating circuit having a standby function, the present invention can be applied to a transition from standby to operation and to a reference voltage generating circuit having no standby function. When applied to a circuit, when the power supply voltage gradually rises, each of the contacts M
Is separated from a predetermined power supply voltage, so that a finite current flows through the MOS transistor forming each stage, thereby generating an expected reference voltage from an operating point where no current flows through each stage. There is an effect that the operation state can be shifted to the operation point.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between I ₁ and I ₂ in a reference voltage generation circuit.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1,2,7,8,15,16,25-27,30,36
To 38 PMOS transistors 3 to 5, 17 to 19, 28, 29, 39, 40 NM
OS transistor 6 Transform gate 9, 12, 21, 24, 31, 34, 41, 44 Resistance 10, 11, 13, 20, 22, 23, 32, 33, 3
5, 42, 43, 45 diodes

Claims (2)

(57) [Claims] 1. A first, second and third first power supply having a source connected to a first power supply and a gate connected in common.
A conductive type MOS transistor, a source connected to the first power supply, a gate connected to the standby terminal, and a drain connected to the gates of the first, second and third first conductive type MOS transistors. A fourth first-conductivity-type MOS transistor; a drain of the first first-conductivity-type MOS transistor; and a gate inserted between the first, second, and third first-conductivity-type MOS transistors. A transfer gate that is on / off controlled by a predetermined standby signal and an inverted signal of the standby signal; a drain connected to the drain of the first first conductivity type MOS transistor; and a gate connected to the standby inversion terminal And the source is connected to the second power source.
A conductivity type MOS transistor, a drain connected to the drain of the first first conductivity type MOS transistor, and a gate connected to the second first conductivity type M transistor.
A second second conductivity type MOS transistor connected to the drain of the OS transistor; a third second conductivity type M having a drain and a gate commonly connected to the gate of the second second conductivity type MOS transistor
An OS transistor; a source of the second second conductivity type MOS transistor;
A first resistor and N (an integer of 1 or more) parallel diodes connected in series between the second power supply, a source of the third second conductivity type MOS transistor, and the second power supply A second resistor and N (an integer of 1 or more) connected in series between the diode connected between the second power supply and a drain of the third first conductivity type MOS transistor and the second power supply. And a parallel diode, wherein a connection point between a drain of the third first conductivity type MOS transistor and the second resistor is used as an output terminal. 2. A depletion second conductivity type MOS transistor having a drain connected to a first power supply and a gate connected to a second power supply, a source connected to the second power supply, and a gate connected to the second power supply. A first, a second, and a third second conductivity type MOS transistor, which are connected in common, and a drain connected to the gates of the first, second, and third second conductivity type MOS transistors, and a gate connected to the display. A first first conductivity type MOS transistor connected to both the source of the second conductivity type MOS transistor and the drain of the second second conductivity type MOS transistor; and a drain and a gate connected to the depletion second MOS transistor. A source of a conductive type MOS transistor and the second second conductive type M
A second first conductivity type MOS transistor connected to both the drain of the OS transistor and connected to a gate of the first first conductivity type MOS transistor; the first power supply; N (an integer of 1 or more) parallel diodes and a first resistor, which are connected in series with the source of the first conductivity type MOS transistor of the first conductivity type, the first power supply, and the second first conductivity type. N (an integer equal to or greater than 1) connected in series between a diode connected between the source of the MOS transistor and the first power supply and a drain of the MOS transistor of the third second conductivity type. A parallel diode and a second resistor, and a connection point between the second resistor and the drain of the third second conductivity type MOS transistor is used as an output terminal. Reference voltage generation circuit.