JPH11150449A - Hysteresis input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure large hysteresis width and to improve stability, even with low voltage by indirectly changing the threshold voltage of a first inverter, constituting a circuit by means of the signal of a second inverter circuit. SOLUTION: When the potential of an input terminal 15 is changed from a low potential to a high potential, an output terminal 17 of inverter circuit constituted of P and N-type MOSFETs 11 and 12 respectively has a low potential, an output terminal 16 has a high potential and the substrates of MOSFETs 11 and 12 have a high potential. Thus, the threshold voltage of P-type MOSFET 11 is changed into a high direction and the threshold voltage of MOSFET 12 to a low direction through back gate effect. Thus, a system goes into a state where the logic level of the inverter circuit changes. When the potential of the input terminal 15 changes from a high potential to a low potential, the threshold voltage of MOSFET 11 and 12 changes to the low direction and the high direction respectively. Thus, the logic level changes in accordance with the change of an input signal, and causes hydsteresist to be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using a MOSFET, and in order to eliminate malfunction or instability due to noise in the input signal, the input signal of the input circuit is changed from a high potential to a low potential, or The present invention relates to a configuration of a circuit for securing a sufficiently large hysteresis width even in the case of a low-voltage power supply, in an input circuit having a logic level with hysteresis when transitioning from a low potential to a high potential.

[0002]

2. Description of the Related Art A conventional input circuit having hysteresis constitutes a circuit equivalent to an inverter circuit, and a P-type MOSFET which is a major factor for determining its logic level.
Of the conductance constant β _P of the N-type MOSFET and the conductance constant β _N of the N-type MOSFET, and the two kinds of β _P and β _N
The circuit configuration changes the ratio in accordance with the previous state.

For example, in FIG. 8, two inverter circuits to which input signals are input are provided, and one of them is turned on (ON) and off (OFF) by a signal in which a previous state is stored, so that β _P and β _N By changing the logic level and changing the logic level, the logic level was different depending on the previous state. In other words, it created hysteresis.

FIG. 9 shows another example of a conventional circuit, which is disclosed in Japanese Patent Application Laid-Open No. 58-182914. This circuit also utilizes a difference in logic level as an inverter circuit due to a difference in β ratio. Creating hysteresis.

[0005]

The input circuit having the above-mentioned conventional hysteresis is an inverter circuit as an equivalent circuit. The logic level of the inverter circuit is, as shown in FIG. 5, of a P-type MOSFET and an N-type MOSFET. If the conductance constants are β _P and β _N respectively, the threshold voltages are V _TP and V _TN , respectively, and the power supply voltage V _DD , the reference ground potential 0 and the logic level are V _GL , then, β _P ( _VDD - _VGL - _VTP ) ² = 1 /
2 · β _N (V _GL −V _TN ) ² is established, and the lock level V _GL is V _GL = ｛V _DD −V _TP + (β _N / β _P ) ^1/2 · V
_TN ｝ / {1+ (β _N / β _P ) ^1/2 }. Therefore, P-type MOSFET and N-type MOSFET
If the shape of the ET is changed and (β _N / β _P ) is changed from 0 to infinity, the logic level changes. Therefore, the logic level is limited to the range of V _TN ≦ V _GL ≦ V _DD −V _TP and the higher logic level V _IH is (β _N / β _P) logic level _{V IL} the V _IH = V _DD -V _TP, and the addition lower when 0 (beta _N /
V _IL = V _TN when β _P ) is infinite. Therefore, the hysteresis width V _WHL is V _WHL = V _DD -V _TP -V _TN . However, as can be seen from the logic level equation, the term (β _N / β _P ) exists in both the numerator and the denominator.
Even if the ratio (β _N / β _P ) is changed, the change in the logic level is small. Therefore, in order to secure a certain hysteresis width, it is necessary to greatly change (β _N / β _P ). Further, since it is impossible in practice to make (β _N / β _P ) 0 or infinity, the hysteresis width is actually smaller than this. Therefore, when the power supply voltage _VDD becomes a low voltage, for example, about 1.0 V, _VTP and _VTN are generally about 0.4 V at the lowest, so that the hysteresis width becomes very small, and the original purpose is not fulfilled. Therefore, the conventional input circuit having hysteresis has a problem that the hysteresis width cannot be increased at a low voltage. FIG. 6 shows this situation simply.

In order to change (β _N / β _P ), the shapes of the P-type MOSFET and the N-type MOSFET become more unnatural,
Occupy a large chip area because it needs to be changed,
There is a problem that the responsiveness is reduced by reducing the driving capability.

Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide an input circuit which has a hysteresis width even at a low voltage.

Another object of the present invention is to provide a circuit capable of realizing an input circuit having a relatively large hysteresis width with an appropriate chip area.

[0009]

A hysteresis input circuit according to the present invention has a first inverter circuit controlled by an input signal and a second inverter circuit storing a previous state. According to the output signal, the first
P-type MOSFET and N-type M constituting the inverter circuit of FIG.
It is characterized in that the substrate potential of the OSFET is controlled.

[0010]

According to the above configuration of the present invention, the logic level of the input circuit is not only the (β _N / β _P ) ratio of the first inverter circuit controlled by the input signal, but also the first inverter circuit stores the previous state. The first by the signal of the second inverter circuit
The threshold voltage changes indirectly (V _TP → V _TP2 , V _TN → V _TN2 ) due to the back gate effect of the P and N MOSFETs constituting the inverter circuit, and the logic level is affected. It has an effect. FIG. 7 simply shows this state.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a circuit diagram showing a first embodiment of a hysteresis input circuit according to the present invention. FIG. 1 uses an SOI (silicon-on-insulator) wafer substrate having a buried oxide film, and the substrates between the MOSFETs are separated in principle. Further, the potential difference between the positive power supply _{+ V DD} and the negative power source _{-V SS} is used at a low power supply voltage of about 0.5V.

In FIG. 1, reference numeral 11 denotes a P-type MOSFET.
T, and the source electrode is connected to the positive power supply + _VDD . 12 is an N-type MOSFET, the source electrode is connected to the power supply _{-V SS} of the negative electrode. P-type MOSFE
The gate electrodes of the T11 and the N-type MOSFET 12 are connected to each other and to the input terminal 15. The drain electrodes are also connected to each other to form an inverter circuit. 13 is a P-type MOSFE
T, and the source electrode is connected to the positive power supply + _VDD . 14 is an N-type MOSFET, the source electrode is connected to the power supply _{-V SS} of the negative electrode. P-type MOSFE
The gate electrodes of the T13 and the N-type MOSFET 14 are connected to each other, and the drain electrodes are also connected to each other to form an inverter circuit. The P-type MO
The gate input of the inverter circuit composed of the SFET 13 and the N-type MOSFET 14 is connected to the drain output 17 of the inverter circuit composed of the P-type MOSFET 11 and the N-type MOSFET 12. Also, the P-type MOSFET 13
And the drain output of the inverter circuit composed of the N-type MOSFET 14 is connected to the output terminal 16 and the P-type MOSFET
It is connected to the substrate of ET11 and the substrate of N-type MOSFET12.

When the potential of the signal applied to the input terminal 15 changes from a low potential (Low) to a high potential (High), the output 17 of the inverter circuit comprising the P-type MOSFET 11 and the N-type MOSFET 12 becomes low, and the output terminal 16
Becomes high potential. The high potential of the output terminal 16 is a P-type MOSF
Since the substrate of the ET11 and the substrate of the N-type MOSFET 12 are set to a high potential, the P-type MOS
The threshold voltage of FET 11 changes in the higher direction,
The threshold voltage of the N-type MOSFET 12 changes in a lower direction. That is, the P-type MOSFET 11 is turned off (OFF), and the N-type MOSFET 12 is turned on (ON). Or P-type MOSFET 11 and N-type M
The logic level of the inverter circuit including the OSFET 12 changes. At this time, the N-type MOSF
High potential + _VDD is applied to the substrate of ET12,
Since the source electrode of the N type MOSFET12 are joined by -V _SS would have applied the diode forward voltage of the N and the substrate P of the source electrode, but the power supply voltage be about 0.5V Since the voltage is lower than the contact potential of the PN diode, no current flows even in the forward direction.

When the potential of the signal applied to the input terminal 15 changes from a high potential (High) to a low potential (Low), the reverse of the above occurs. Therefore, it can be understood that the logic level of the circuit shown in FIG. 1 changes according to whether the transition of the input signal is from a low potential to a high potential or vice versa.

FIG. 2 is a circuit diagram showing a second embodiment of the hysteresis input circuit according to the present invention. FIG. 2 also uses an SOI substrate.

The difference between the circuit of FIG. 2 and the circuit of FIG.
It is. Other P-type MOSFETs 21 and 23 and N-type M
OSFETs 22 and 24 are respectively the P-type MOS of FIG.
The FETs 11 and 13 and the N-type MOSFETs 12 and 14 have substantially the same functions. Now, FIG.
, The gate electrode and the source electrode of the P-type MOSFET 29 are connected to each other and to the substrate of the P-type MOSFET 21. The drain electrode of the P-type MOSFET 29 is connected to the output terminal 26. In addition, N type M
The gate electrode and the source electrode of the OSFET 28 are connected to each other and to the substrate of the N-type MOSFET 22. The drain electrode of the N-type MOSFET 28 is connected to the output terminal 26. This prevents a current from flowing from the substrate toward the output terminal 26. That is,
In the circuit of FIG. 1, when a low potential is applied to the substrate of the P-type MOSFET 11 or a high potential is applied to the substrate of the N-type MOSFET 12, the PN diode between the substrate and the source electrode is in the forward direction. 0.
Although the circuit can be used only with a low power supply voltage of about 5 V, the circuit of FIG.
Since the SFET 28 is inserted to prevent the forward current of the diode from flowing, the circuit can be used with a power supply voltage higher than the contact potential of PN, that is, about 0.5 V or more.

FIG. 3 is a circuit diagram showing a third embodiment of the hysteresis input circuit according to the present invention. FIG. 3 also uses an SOI substrate. Further, the potential difference between the positive power supply _{+ V DD} and the negative power source _{-V SS} is used at a low power supply voltage of about 0.5V.

In FIG. 3, reference numeral 31 denotes a P-type MOSFET.
T, and the source electrode is connected to the positive power supply + _VDD . 32 is an N-type MOSFET, the source electrode is connected to the power supply _{-V SS} of the negative electrode. P-type MOSFE
The gate electrodes of the T31 and the N-type MOSFET 32 are connected to each other and to the input terminal 35. The drain electrodes are also connected to each other to form an inverter circuit.

Reference numerals 39 and 41 denote P-type MOSFETs. The source electrode of the P-type MOSFET 39 has a positive power supply +
_VDD , and the drain electrode is a P-type MOSFET 4
1 source electrode. Also, 40 and 42 are N-type MOSFET, the source electrode of the N type MOSFET40 are connected to the power supply _{-V SS} of the negative electrode, the drain electrode is connected to the source electrode of the N-type MOSFET 42. Drain electrode of P-type MOSFET 41 and N-type MOS
The drain electrodes of the FET 42 are connected to each other and to the drain output 37 of the inverter circuit composed of the P-type MOSFET 31 and the N-type MOSFET 32. The gate electrode of the P-type MOSFET 39 and the N-type MOSFET
The gate electrodes 40 are both connected to the input terminal 35. Reference numeral 33 denotes a P-type MOSFET, and the source electrode is connected to a positive power supply + _VDD . 34 is an N-type MO
A SFET, the source electrode is connected to the power supply _{-V SS} of the negative electrode. P-type MOSFET 33 and N-type MOSFET
Each gate electrode of T34 is connected to each other, and each drain electrode is also connected to each other to form an inverter circuit. The P-type MOSFET 33 and the N-type MO
The gate input of the inverter circuit composed of the SFET 34 is connected to the drain output 37 of the inverter circuit composed of the P-type MOSFET 31 and the N-type MOSFET 32. Further, the P-type MOSFET 33 and the N-type MOSFET 3
The drain output of the inverter circuit consisting of
6 and P-type MOSFETs 31, 39, 41
Substrate and N-type MOSFETs 32, 40, and 42, and P-type MOSFET 41 gate electrode and N-type MOSFET.
It is connected to the gate electrode of ET42.

The above circuit has a hysteresis by switching the inverter circuit having a different β ratio in FIG. 8 of the conventional circuit, and also controls the threshold voltage due to the back gate effect by controlling the substrate potential. , And the hysteresis width is further increased by providing a change in the logic level due to the change in.

FIG. 4 is a circuit diagram showing a fourth embodiment of the hysteresis input circuit according to the present invention. FIG. 4 also uses an SOI substrate.

4 differs from the circuit of FIG. 3 in that a P-type MOSFET 49 and an N-type MOSFET 48
It is. Other P-type MOSFETs 31, 33, 39, 41
And N-type MOSFETs 32, 34, 40 and 42 are shown in FIG.
Have the same role in correspondence with the same numbered MOSFETs.

Now, referring to FIG.
Are connected to each other and to the substrates of the P-type MOSFETs 31, 39 and 41. The drain electrode of the P-type MOSFET 49 is connected to the output terminal 26. The N-type MOSFET 48
Are connected to each other and to the substrates of the N-type MOSFETs 32, 40, and 42. The drain electrode of the N-type MOSFET 48 is connected to the output terminal 46. Thereby, the P-type MO shown in FIG.
Like the SFET 29 and the N-type MOSFET 28, it prevents a current from flowing from the substrate to the output terminal 36. Therefore, the circuit can be used even with a power supply voltage higher than the contact potential of the PN diode, that is, about 0.5 V or more.

In the above description, an embodiment using a wafer of an SOI substrate has been described. However, an SOS (silicon on sapphire) may be used, or a normal bulk wafer may have a triple well structure. The substrate potential can be similarly controlled.

FIGS. 3 and 4 show a conventional example shown in FIG.
Although the example in which the substrate potential is further added to the above circuit is shown, a general hysteresis width can be obtained by adding the substrate potential in a general circuit for switching between the conventional inverter circuits having different β ratios as shown in FIG. I can do it.

[0026]

As described above, according to the present invention, there is an effect that a hysteresis input circuit which can secure a hysteresis width even in a low-voltage power supply can be provided.

Therefore, there is an effect that a hysteresis input circuit resistant to noise can be provided even at a low voltage.

Further, since the method is a method of controlling the substrate potential, there is an effect that the circuit chip area can be reduced as compared with the conventional circuit of changing the β ratio.

Also, unlike the conventional β ratio changing type,
Since the shape of the MOSFET is reasonable, there is an effect that the response can be easily secured.

Further, when used in combination with a conventional circuit of changing the β ratio, there is an effect that a larger hysteresis width can be ensured and a hysteresis input circuit having good low voltage characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an inverter circuit used in the circuit of the present invention and a conventional circuit.

FIG. 6 is an electrical characteristic diagram illustrating a state in which a conventional circuit has hysteresis.

FIG. 7 is an electrical characteristic diagram illustrating a state of the circuit of the present invention having hysteresis.

FIG. 8 is a circuit diagram showing an example of a conventional circuit.

FIG. 9 is a circuit diagram showing an example of a conventional circuit.

[Explanation of symbols]

11, 13, 21, 23, 29, 31, 33, 39, 4
1, 49 ... P-type MOSFETs 12, 14, 22, 24, 28, 32, 34, 40, 4
2, 48 ... N-type MOSFET 15, 25, 35, 45 ... input terminal 16, 26, 36, 46 ... output terminal

Claims (6)

[Claims] A) an input circuit of a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET); b) a first electrode having a source electrode connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
A first N-type MOSFET connected to the first P-type MOSFET and a first N-type MOSFET.
A first inverter circuit having a configuration in which respective gate electrodes are connected to each other and respective drain electrodes are also connected to each other; c) a second inverter circuit in which a source electrode is connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
And a second N-type MOSFET connected to the second P-type MOSFET and a second N-type MOSFET.
And a second inverter circuit having a configuration in which the respective gate electrodes are connected to each other and the respective drain electrodes are also connected to each other. D) An input of the first inverter circuit is connected to an input terminal as an input circuit. The output is connected to the input of the second inverter circuit, and the output of the second inverter circuit is connected to the first P-type MOSFET and the first N-type MOS.
A hysteresis input circuit connected to an FET substrate. 2. The hysteresis input circuit according to claim 1, wherein said semiconductor integrated circuit device is formed of a silicon-on-insulator (SOI). 3. An input circuit of a semiconductor integrated circuit device using a MOSFET, b) a first electrode having a source electrode connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
A first N-type MOSFET connected to the first P-type MOSFET and a first N-type MOSFET.
A first inverter circuit having a configuration in which respective gate electrodes are connected to each other and respective drain electrodes are also connected to each other; c) a second inverter circuit in which a source electrode is connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
And a second N-type MOSFET connected to the second P-type MOSFET and a second N-type MOSFET.
A second inverter circuit having a configuration in which the respective gate electrodes are connected to each other and the respective drain electrodes are also connected to each other; E) a third N-type MOSFET having a drain and a source connected to a first electrode and a gate electrode, and f) an input of the first inverter circuit is connected to an input terminal as an input circuit. The output is connected to the input of the second inverter circuit, and the output of the second inverter circuit is connected to the second electrode of the third P-type MOSFET and the second electrode of the third N-type MOSFET. G) the first electrode of the third P-type MOSFET is the first electrode
And a first electrode of the third N-type MOSFET is connected to the first N-type MOSFET.
A hysteresis input circuit connected to a substrate. 4. An input circuit of a semiconductor integrated circuit device using a MOSFET, b) a first electrode having a source electrode connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
A first N-type MOSFET connected to the first P-type MOSFET and a first N-type MOSFET.
A first inverter circuit having a configuration in which respective gate electrodes are connected to each other and respective drain electrodes are also connected to each other; c) a second inverter circuit in which a source electrode is connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
And a second N-type MOSFET connected to the second P-type MOSFET and a second N-type MOSFET.
A second inverter circuit having a configuration in which the respective gate electrodes are connected to each other and the respective drain electrodes are also connected to each other; and d) a third inverter circuit in which the source electrode is connected to the positive power supply + _VDD .
A fourth P-type MOSFET connected in series with the P-type MOSFET and said third P-type MOSFET of the third N-type MOSFE its source electrode connected to the power supply _{-V SS} of the negative electrode
T and a fourth N-type MOSFET connected in series with the third N-type MOSFET.
And the fourth P-type M
A drain electrode of the OSFET and the fourth N-type MOSFET;
E) an input of the first inverter circuit is connected to an input terminal as an input circuit, and an output is connected to an input of the second inverter circuit; The output of the second inverter circuit is connected to the gate electrode of the fourth P-type MOSFET and the fourth N-type MOSFET.
T, and the first, third,
A fourth P-type MOSFET and first, third, and fourth N-type MOSFETs are also connected to each other; g) the fourth P-type MOSFET and the fourth N-type MO.
The connection point of the drain electrode of the SFET is connected to the output of the first inverter circuit, and the third P-type MOSFET
And a gate electrode of the third N-type MOSFET is connected to an input terminal as the input circuit. 5. The hysteresis input circuit according to claim 4, wherein said semiconductor integrated circuit device is formed of a silicon-on-insulator (SOI). 6. An input circuit of a semiconductor integrated circuit device using a MOSFET, wherein: b) a first electrode having a source electrode connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
A first N-type MOSFET connected to the first P-type MOSFET and a first N-type MOSFET.
A first inverter circuit having a configuration in which respective gate electrodes are connected to each other and respective drain electrodes are also connected to each other; c) a second inverter circuit in which a source electrode is connected to a positive power supply + _VDD .
P-type MOSFET and power supply -V _{SS with} negative electrode
And a second N-type MOSFET connected to the second P-type MOSFET and a second N-type MOSFET.
A second inverter circuit having a configuration in which the respective gate electrodes are connected to each other and the respective drain electrodes are also connected to each other; and d) a third inverter circuit in which the source electrode is connected to the positive power supply + _VDD .
A fourth P-type MOSFET connected in series with the P-type MOSFET and said third P-type MOSFET of the third N-type MOSFE its source electrode connected to the power supply _{-V SS} of the negative electrode
T and a fourth N-type MOSFET connected in series with the third N-type MOSFET.
And the fourth P-type M
A drain electrode of the OSFET and the fourth N-type MOSFET;
A series circuit in which drain electrodes of T are connected to each other; e) a fifth P-type MOSFET in which a first electrode serving as a drain or a source and a gate electrode are connected; f) a first electrode and a gate serving as a drain or a source A fifth N-type MOSFET to which electrodes are connected; g) an input of the first inverter circuit is connected to an input terminal as an input circuit, and an output is connected to an input of the second inverter circuit; h) The output of the second inverter circuit is connected to the gate electrode of the fourth P-type MOSFET and the fourth N-type MOSFET.
And the fifth P-type M
A second electrode of the OSFET and a second electrode of the fifth N-type MOSFET, i) a first electrode of the fifth P-type MOSFET is a substrate of the first, third, and fourth P-type MOSFETs; Connected to
A first electrode of the fifth N-type MOSFET is connected to a substrate of the first, third, and fourth N-type MOSFETs; and j) the fourth P-type MOSFET and the fourth N-type MOSFET are connected.
The connection point of the drain electrode of the SFET is connected to the output of the first inverter circuit, and the third P-type MOSFET
And a gate electrode of the third N-type MOSFET is connected to an input terminal as the input circuit.