JP3024570B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a pull-up resistor and a pull-down resistor (hereinafter, referred to as an "input / output" circuit) for passing a required current.
(Represented by a pull-up resistor).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit having a CMOS structure, for example, it is sometimes required to change a current value in a pull-up resistor provided in an input circuit. FIG.
(A) is an example described in JP-A-61-43016, in which an input terminal 301 is connected to an input terminal D of a latch circuit 302 and a pull-up resistor 303 and a switching PMOS transistor 304 are connected. A high-potential power supply is applied via the power supply. The timing signal generating circuit 3 is connected to the gate of the switching PMOS transistor 304.
The switching of the latch circuit 3 is controlled by the timing signal generation circuit 305.
02, a clock input terminal C is supplied with a latch timing clock from the timing signal generation circuit 305, and an output signal is obtained by a latch operation of the latch circuit 302.

In this pull-up resistor circuit, FIG.
As shown in the timing chart in FIG.
The MOS transistor 304 is periodically turned on at the low level of the pulse signal φ, and repeats a current conduction state and a current blocking state to control the current amount. During the low level period of the pulse signal φ, a pulse signal さ れ る synchronized with the pulse is periodically input from the timing generation circuit 305 to the clock terminal C of the latch circuit 302, and when the pulse signal ψ is at the high level. The latch circuit 302 latches an input signal, and outputs a signal of a conductive state of the switching PMOS transistor 304 to an output terminal of the latch circuit. Therefore, the amount of current at the input terminal can be controlled by periodically turning on / off the switching transistor 304 by a pulse signal from the timing generation circuit 305.

[0004]

In the above-described conventional pull-up resistor circuit, it is possible to achieve low power consumption by controlling the current flowing through the pull-up resistor with time. Since the resistance value of the resistor for use is uniquely determined in the process of fabricating the semiconductor integrated circuit chip, it cannot cope with an application circuit such as an input voltage drop due to one step drop. Therefore, to set the optimal current value for such an application circuit,
It is necessary to control the current value by changing the resistance value of the pull-up resistor, and for that purpose, it is necessary to change the circuit such as the pattern constituting the pull-up resistor and the diffusion concentration of impurities into the semiconductor. It becomes difficult to generalize the integrated circuit. Further, there is a problem that the set resistance value varies depending on the parameter being diffused, and it is difficult to obtain a designed resistance value with high accuracy.

An object of the present invention is to provide a semiconductor integrated circuit in which the resistance value of a pull-up resistor can be arbitrarily varied and set to a current value suitable for various different application circuits. is there.

[0006]

The present invention includes an input / output signal line of a semiconductor integrated circuit, a MOS transistor having a floating gate and a control gate, a voltage application terminal, and a current mirror circuit. MO
It is connected with a voltage application terminal to the control gate of the S transistor, the current drain of the MOS transistor
Connect the signal line to one current path of the mirror circuit , connect the signal line to the other current path of the current mirror circuit, and connect to the voltage application terminal .
The voltage application time is changed to change the voltage of the MOS transistor.
By changing the amount of charge injected into the loading gate,
The current flowing between the source and the drain of the MOS transistor can be controlled to set the current value of the signal line .

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment in which the present invention is applied to a pull-up resistor circuit. In the figure, an input signal is sent from an input terminal 101 to a signal line 10.
2 is input to the buffer 103, and this buffer 1
The signal is input to the internal circuit of the semiconductor integrated circuit through the circuit 03.
Further, a voltage application terminal 104 for controlling the current value of the signal line 102 is provided.
There is provided a current value control block 105 controlled by the current value control block 04. The current value control block 105 has the first dimension of the same dimension whose source is connected to the high potential power supply.
The gates of the PMOS transistor 106 and the second PMOS transistor 107 are connected to each other, and this connection point is connected to the drain of the first PMOS transistor 106 to form a current mirror circuit. The drain of the first PMOS transistor 106 is connected to the drain of an NMOS transistor 110 which will be described in detail later.
Is connected. Also, the second PMOS transistor 1
07 is connected to the signal line 102.

The NMOS transistor 110 is a MOS transistor.
The transistor has a configuration in which a floating gate and a control gate are stacked, the source thereof is grounded, and an arbitrary potential is applied to the control gate from the voltage application terminal 104. This NMOS
The floating gate of the transistor 110 has a structure in which the control gate 112 is in contact with the source and drain channel regions via an oxide film, and part of the floating gate is in contact with the drain region and an extremely thin tunnel oxide film. To the control gate 112, the floating gate 111 rises to a high potential due to the coupling with the control gate 112, the potential difference between the floating gate 111 and the drain increases, and a tunnel current flows through the tunnel oxide film, and the floating gate 111 Electrons are injected into 111.
By varying the amount of electrons injected into the floating gate 111, the degree of channel induction changes, and the threshold voltage changes accordingly.

The amount of electron injection can be controlled by controlling the voltage application time applied to the voltage application terminal 104 according to the equation (1) shown in (Equation 1).

(Equation 1) C: capacitance between floating gate and control gate J: current density injected into floating gate t: time

As a result, the NMOS transistor 110
Operates as a resistance value setting transistor, and the source / drain current of the NMOS transistor 110 is controlled to change according to the voltage application time of the voltage application terminal 104. As a result, the source / drain current of the first PMOS transistor 106 is changed and controlled to follow. Here, the first and second PMOS transistors 106 and 107 are
Even if the potential difference between the source and the drain is different depending on the current-voltage characteristics of the MOS transistor, the same gate potential is obtained. Therefore, the current mirror operation causes the signal lines 108 and 102 connected to each MOS transistor to be connected to each other. The flowing current value always becomes the same value. That is, the current of the signal line 102 becomes the same as the source / drain current of the NMOS transistor, and as a result, the
The current value of the signal line 102 can be controlled by the transistor 110.

Therefore, in this embodiment, the NMOS
By controlling the source / drain current of the transistor 110, the resistance value of the NMOS transistor in the signal line 108 can be equivalently changed, and accordingly, the current value of the signal line 102 is changed. The value can be set to an optimum value required by the application circuit. For this reason, it is not necessary to preset the resistance value of the bull-up resistor at the time of manufacturing the semiconductor integrated circuit, and design and manufacturing for that purpose are not required. Further, it is possible to obtain a highly accurate resistor only by controlling the voltage application without causing a variation in resistance value due to uneven diffusion as in the case where a resistor is formed by impurity diffusion.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of a second embodiment in which the present invention is applied to a bull-down resistor circuit. In the figure, an input signal is sent from an input terminal 201 to a signal line 202.
And input to the input buffer 203, and to the internal circuit of the semiconductor integrated circuit. Further, in order to control the current value of the signal line 202, a voltage application terminal 204 and a current value control block 205 are provided. The current value control block is configured to have a polarity opposite to that of the first embodiment, and the first NMOS transistor 206 and the second NMOS transistor 207 having the same dimensions and having the source connected to the ground potential power supply. And a current mirror circuit in which the gates are connected to each other, and are connected to the signal lines 202 and 208, respectively. Therefore, even if the potential difference between the source and the drain of each of the first and second NMOS transistors 206 and 207 has a different value due to the current-voltage characteristics of these NMOS transistors, the same gate potential is obtained. And the current value flowing through the signal line 202 always becomes the same value.

The source / drain of a PMOS transistor 210 having a floating gate 211 whose resistance can be varied is connected to the signal line 208. The voltage application terminal 204 is connected to the gate of the PMOS transistor 210. ing. This PMO
The structure of the S transistor 210 is the same as that of the NMO of the first embodiment.
It is the same as the S transistor. When a constant voltage higher than the drain voltage is applied to the control gate 212 from the voltage application terminal 204, the floating gate 211 rises to a high potential due to the coupling with the control gate 212, and the potential difference between the floating gate 211 and the drain is reduced. As the tunnel current increases, electrons are injected into the floating gate 211. In the case where the amount of electrons injected into the floating gate 211 is made variable, the voltage application time at the voltage application terminal 204 is controlled by the equation (1) of (Equation 1) shown in the first embodiment. Thus, the amount of electron injection can be controlled.

As described above, in the second embodiment, the amount of source / drain current in the PMOS transistor 210 can be varied by controlling the voltage application time at the voltage application terminal 204, and the PMOS transistor 210 is pulled down. It is possible to operate as a resistance setting transistor as a resistor. By changing the resistance value of the PMOS transistor 210, the current value on the signal line 202 to which the input signal is input can be set to an optimum value required by the application circuit.

[0015]

As described above, the present invention provides a MOS
Is connected with a voltage application terminal to the control gate of the transistor, a drain connected to the MOS transistor on one current path of the current mirror circuit, to connect the signal line to the other current path of the current mirror circuit, to the voltage application terminal Electric
Voltage application time to change the flow of the MOS transistor.
Changing the amount of charge injected into the
Te, wherein controlling the current flowing between the source and the drain of the MOS transistor, since the structure <br/> formed which can set the current value of the signal line, the input voltage drop or the like according to one-step drop,
The current value of the input signal can be set to an optimum value for various application circuits. Therefore, it is not necessary to manufacture a pull-up resistor or a pull-down resistor having a predetermined resistance value when manufacturing a semiconductor integrated circuit, and there may be a variation in resistance value due to a diffusion variation generated when manufacturing a resistor by diffusion. Therefore, a highly accurate pull-up or pull-down resistor can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining a conventional input circuit having a pull-up resistor and its operation.

[Explanation of symbols]

101, 201 input terminal 102, 202 signal line 103, 203 input buffer 104, 204 voltage application terminal 106, 107 PMOS transistor 110 NMOS transistor with floating gate 206, 207 NMOS transistor 210 PMOS transistor with floating gate 111, 211 floating gate 112, 212 Control gate

Claims (3)

(57) [Claims] An input / output signal line for a semiconductor integrated circuit;
A MOS transistor having a floating gate and a control gate; a voltage application terminal; and a current mirror circuit. The voltage application terminal is connected to a control gate of the MOS transistor, and a drain of the MOS transistor is connected to the current mirror circuit. Connected to one of the current paths,
Connecting the signal line to the other current path of the current mirror circuit changes the voltage application time to the voltage application terminal, before
Charge to floating gate of MOS transistor
A semiconductor integrated circuit characterized in that a current flowing between a source and a drain of the MOS transistor is controlled by changing an injection amount, and a current value of the signal line can be set . 2. A pull-up or pull-down resistor circuit in a semiconductor integrated circuit, comprising: a first potential power supply, a second potential power supply, a voltage application terminal, an input / output terminal, and a first conductivity type channel. First
MOS transistor, a second MOS transistor having a first conductivity type channel having the same dimensions as the first MOS transistor, and a third MOS transistor having a floating gate, a control gate, and a second conductivity type channel A first MOS transistor; and a second MOS transistor.
A source of the transistor is connected to the first potential power source, the first MOS transistor, and the second MOS
Connecting the gates of the transistors to each other,
The first MOS transistor and the third MOS transistor are connected via a current path connecting the gate and the drain of the S transistor.
Connecting the source of the third MOS transistor to a second potential power supply; connecting the control gate of the third MOS transistor to the voltage application terminal; A semiconductor integrated circuit, wherein a current path connected to a drain of a MOS transistor is connected to the input / output terminal via the signal line. 3. A floating gate of the MOS transistor , wherein a voltage application time to the voltage application terminal is changed.
3. The semiconductor integrated circuit according to claim 2, wherein a current flowing between the source and the drain of the MOS transistor is controlled by changing a charge injection amount into the MOS transistor, and a current value of the signal line can be set. 4. circuit.