JPH07121255A - Constant current source circuit - Google Patents

Constant current source circuit

Info

Publication number
JPH07121255A
JPH07121255A JP29263393A JP29263393A JPH07121255A JP H07121255 A JPH07121255 A JP H07121255A JP 29263393 A JP29263393 A JP 29263393A JP 29263393 A JP29263393 A JP 29263393A JP H07121255 A JPH07121255 A JP H07121255A
Authority
JP
Japan
Prior art keywords
current
circuit
node
transistor
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29263393A
Other languages
Japanese (ja)
Inventor
Hidenao Satou
英直 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29263393A priority Critical patent/JPH07121255A/en
Priority to EP19940116889 priority patent/EP0651311A2/en
Publication of JPH07121255A publication Critical patent/JPH07121255A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26Current mirrors
    • G05F3/262Current mirrors using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE:To enable the constant-current source circuit to actuate itself automatically and stably without making any consumable current to an actuating circuit itself. CONSTITUTION:In the silicon band gap type constant-current source circuit consisting of two current mirror circuits M1 and M2 and a resistance R1 which determines the current gains of those current mirror circuits, plural diode- connected transistors(TR) T5-T9 are connected in series between the output node N1 and low power source potential VSS of the circuit. The threshold value of the whole series-connected circuit is set higher than the voltage at the node N1 in a normal state, and consequently this series-connected circuit turns OFF in the normal state to have no current consumption and turns ON only at the time of actuation after the source voltage drops, so that the circuit can be actuated again.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は定電流源回路に関し、特
にCMOS集積回路における定電流源回路を自励式に起
動するめたの回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current source circuit, and more particularly to a circuit for starting a constant current source circuit in a CMOS integrated circuit by self-excitation.

【0002】[0002]

【従来の技術】従来の定電流源回路の1例としてCMO
S構造を用い、シリコンのバンドギャップを利用して定
電流を発生させる回路があり、図2にその回路例を示し
ている。
2. Description of the Related Art A CMO is an example of a conventional constant current source circuit.
There is a circuit that uses the S structure to generate a constant current by utilizing the bandgap of silicon. FIG. 2 shows an example of the circuit.

【0003】図2の回路は基本的には、2つのカレント
ミラー回路M1,M2と、これ等カレントミラー回路の
電流利得を定める抵抗R1とからなる。
The circuit of FIG. 2 basically comprises two current mirror circuits M1 and M2 and a resistor R1 which determines the current gain of these current mirror circuits.

【0004】カレントミラー回路M1は、ゲートとドレ
インとが接続されたダイオード構成のNMOS(Nチャ
ンネルMOS)トランジスタT2と、このトランジスタ
T2のゲートとゲートが共通接続されたNMOSトラン
ジスT1とからなる。そして、ノードN2に供給される
トランジスタT2のドレイン電流I2に応じた電流I3
がトランジスタT1のドレイン電流となり、ノードN1
へ供給される。
The current mirror circuit M1 comprises a diode-structured NMOS (N-channel MOS) transistor T2 having a gate and a drain connected to each other, and an NMOS transistor T1 having the gate and the gate of the transistor T2 commonly connected to each other. Then, a current I3 corresponding to the drain current I2 of the transistor T2 supplied to the node N2
Becomes the drain current of the transistor T1, and the node N1
Is supplied to.

【0005】電流I2とI3との関係はこのカレントミ
ラー回路M1の電流利得により定まり、抵抗R1により
決定される。
The relationship between the currents I2 and I3 is determined by the current gain of the current mirror circuit M1 and is determined by the resistor R1.

【0006】カレントミラー回路M2は、ゲートとドレ
インとが接続されたダイオード構成のPMOS(Pチャ
ンネルMOS)トランジスタT3と、このトランジスタ
T3のゲートにゲートが共通接続されたPMOSトラン
ジスタT4とからなる。そして、ノードN1に供給され
るトランジスタT3のドレイン電流I1に応じた電流I
2がトランジスタT4のドレイン電流となり、ノードN
2へ供給される。
The current mirror circuit M2 comprises a diode-structured PMOS (P-channel MOS) transistor T3 having a gate and a drain connected to each other, and a PMOS transistor T4 having a gate commonly connected to the gate of the transistor T3. Then, a current I corresponding to the drain current I1 of the transistor T3 supplied to the node N1
2 becomes the drain current of the transistor T4, and the node N
2 is supplied.

【0007】更に、このノードN1にゲートが接続され
たPMOSトランジスタT11が設けられており、この
トランジスタT11とトランジスタT3とにより出力導
出用のカレントミラー回路が構成されている。このトラ
ンジスタT11のドレイン電流I0が出力電流として用
いられるが、本例では、負荷用NMOSトランジスタT
10を用いてこの出力電流I0を導出している。
Further, a PMOS transistor T11 having a gate connected to the node N1 is provided, and the transistor T11 and the transistor T3 constitute a current mirror circuit for deriving an output. The drain current I0 of the transistor T11 is used as the output current, but in the present example, the load NMOS transistor T
This output current I0 is derived using 10.

【0008】そして、ノードN1と基準低電位VSSとの
間に、起動用のNMOSトランジスタT12が設けられ
ており、このトランジスタT12のゲートへ起動用のリ
セット信号が印加されるようになっている。
A starting NMOS transistor T12 is provided between the node N1 and the reference low potential VSS, and a starting reset signal is applied to the gate of the transistor T12.

【0009】尚、トランジスタは全てエンハンスメント
型であるとする。
It is assumed that all the transistors are enhancement type.

【0010】かかる回路を起動する場合、基準高電位V
DDが供給されると共に、トランジスタT12のゲートに
起動信号が供給される。すると、NMOSトランジスタ
T1,T2及びPMOSトランジスタT3,T4がオン
となり、カレントミラー回路M2の電流利得と、抵抗R
1により定まるカレントミラー回路M1の電流利得との
積が1になる動作点で安定することになる。
When activating such a circuit, the reference high potential V
The DD is supplied and the activation signal is supplied to the gate of the transistor T12. Then, the NMOS transistors T1 and T2 and the PMOS transistors T3 and T4 are turned on, and the current gain of the current mirror circuit M2 and the resistance R
It becomes stable at the operating point where the product of the current gain of the current mirror circuit M1 determined by 1 becomes 1.

【0011】この安定状態において、両カレントミラー
回路M1,M2及び抵抗R1からなる閉ループ回路に流
れる電流が、トランジスタT11を用いたカレントミラ
ー回路により定電流I0として取出されるのである。
In this stable state, the current flowing in the closed loop circuit composed of both current mirror circuits M1 and M2 and the resistor R1 is taken out as a constant current I0 by the current mirror circuit using the transistor T11.

【0012】この回路では、起動時に電源投入検出を行
って起動信号をトランジスタT12のゲート入力とする
必要があり、また電源変動時、特に電源電圧の急激な低
下により、トランジスタT1〜T4の全てがカットオフ
となって安定してしまい、定電流I0を発生できなくな
る。
In this circuit, it is necessary to detect the power-on at the time of start-up and use the start-up signal as the gate input of the transistor T12. Also, when the power supply fluctuates, all of the transistors T1 to T4 are all affected by a sudden drop in the power supply voltage. It becomes a cutoff and becomes stable, and the constant current I0 cannot be generated.

【0013】そこで、自励式の起動回路を付加した定電
流源回路が特開平4−111008号公報に開示されて
おり、その構成を図3に示す。図3において図2と同等
部分は同一符号により示している。
Therefore, a constant current source circuit to which a self-excited starter circuit is added is disclosed in Japanese Patent Laid-Open No. 4-111008, and its configuration is shown in FIG. 3, the same parts as those in FIG. 2 are designated by the same reference numerals.

【0014】図3においては、図2の回路にオフリーク
電流供給用のNMOSトランジスタT13とPMOSト
ランジスタT14とを、各ノードN2,N1と電源VS
S,VDDとの間に夫々設けており、起動時や起動後の電
源低下後の自起動時に、トランジスタT13,T14の
オフリーク電流を各ノードN2,N1へ夫々供給するこ
とにより、自励起動を行うようになっている。尚、その
動作の詳細は上記公開公報に示されている。
In FIG. 3, the circuit of FIG. 2 is provided with an NMOS transistor T13 and a PMOS transistor T14 for supplying an off-leak current, nodes N2 and N1 and a power source VS.
They are provided between S and VDD, respectively, and the self-excitation operation is performed by supplying the off-leakage currents of the transistors T13 and T14 to the nodes N2 and N1 at the time of start-up or at the time of self-starting after the power supply is lowered after the start-up. I am supposed to do it. The details of the operation are shown in the above-mentioned publication.

【0015】[0015]

【発明が解決しようとする課題】図3に示す自励式の定
電流源回路では、カレントミラー回路M1,M2の各入
出力ノードN1,N2に、常時オフ状態のトランジスタ
T13,T14を介してオフリーク電流を供給する方式
であるので、回路の定常時にも回路中に当該オフリーク
電流が常に流れていることになり、消費電力増大という
問題の他に、このオフリーク電流を見込んだ回路設計が
必要となり、設計の困難さを伴うという欠点がある。
In the self-excited constant current source circuit shown in FIG. 3, the off-leakage occurs in the input / output nodes N1 and N2 of the current mirror circuits M1 and M2 through the transistors T13 and T14 which are always off. Since it is a method of supplying current, the off-leakage current always flows in the circuit even when the circuit is in a steady state, and in addition to the problem of increased power consumption, it is necessary to design the circuit considering this off-leakage current. It has the drawback of being difficult to design.

【0016】本発明の目的は、起動時にのみ自励用電流
を流し定常時は何等自励回路に電流が流れない定電流源
回路を提供することである。
An object of the present invention is to provide a constant current source circuit in which a self-exciting current is supplied only at the time of starting and no current flows in the self-exciting circuit in a steady state.

【0017】[0017]

【課題を解決するための手段】本発明によれば、第1及
び第2のノードと、前記第1のノードに第1の電流を、
前記第2のノードに電流利得に応じた第2の電流を夫々
供給する第1のカレントミラー回路と、前記第2のノー
ドに前記第2の電流を、前記第1のノードに電流利得に
応じた第3の電流を夫々供給する第2のカレントミラー
回路と、前記第2のカレントミラー回路の電流利得を定
める抵抗素子とを含む定電流源回路であって、前記第1
のノードと基準電位点との間に、この第1のノードの通
常動作時の電圧よりも大なる閾値を有するスイッチング
回路を有することを特徴とする定電流源回路が得られ
る。
According to the present invention, first and second nodes, and a first current at the first node,
A first current mirror circuit that supplies a second current corresponding to the current gain to the second node, and a second current to the second node and a current gain to the first node. A constant current source circuit including a second current mirror circuit for respectively supplying a third current, and a resistance element that determines a current gain of the second current mirror circuit,
A constant current source circuit is obtained which has a switching circuit having a threshold value larger than the voltage of the first node at the time of normal operation, between the node and the reference potential point.

【0018】[0018]

【実施例】以下に本発明の実施例を図面を用いて説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

【0019】図1は本発明の実施例の回路図であり、図
2と同等部分は同一符号にて示している。図2と異なる
部分について述べると、本例では、ノードN1と基準低
電源電位VSSとの間に、ダイオード接続構成のNMOS
トランジスタT5〜T9を複数個直列接続して設けた構
成であり、他の構成は図2のそれと同一であってその説
明は省略する。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. To describe the part different from FIG. 2, in this example, an NMOS with a diode connection configuration is provided between the node N1 and the reference low power supply potential VSS.
It has a configuration in which a plurality of transistors T5 to T9 are connected in series, and the other configuration is the same as that of FIG. 2 and its description is omitted.

【0020】ここで、高電源電位VDDを5V,低電源電
位VSSを0Vとする。この回路において、2つのカレン
トミラー回路M1,M2で生じる電流利得の積が1とな
って安定状態となることは従来例と同様である。
Here, the high power supply potential VDD is 5V and the low power supply potential VSS is 0V. In this circuit, the product of the current gains generated in the two current mirror circuits M1 and M2 becomes 1 and the stable state is achieved, as in the conventional example.

【0021】ノードN1における電流I1の値は、トラ
ンジスタT1,T2とトランジスタT3,T4の各ゲー
ト幅Wと、ゲート長Lと、抵抗R1の値とにより決定さ
れ、ノードN1の電流I1によりノードN1の電圧VN1
は5V〜0Vの間の電圧となる。
The value of the current I1 at the node N1 is determined by the gate width W of each of the transistors T1 and T2 and the transistors T3 and T4, the gate length L, and the value of the resistor R1. Voltage VN1
Is a voltage between 5V and 0V.

【0022】電源投入時や電源電圧の急激な低下等によ
り、ノードN2の電圧VN2がトランジスタT2の閾値V
T2より低くなり、またノードN1の電圧VN1がトランジ
スタT3の閾値VT3より低くなると、これ等トランジス
タはカットオフ状態となり、I1及びI2の各電流は流
れなくなる。
The voltage VN2 at the node N2 changes to the threshold value V of the transistor T2 when the power is turned on or the power supply voltage suddenly drops.
When it becomes lower than T2 and the voltage VN1 of the node N1 becomes lower than the threshold VT3 of the transistor T3, these transistors are cut off and the currents I1 and I2 stop flowing.

【0023】しかしながら、カットオフ状態によってノ
ードN1の電圧VN1が電源電圧VDDに近づこうとし、ダ
イオード接続されたスイッチング回路としてのトランジ
スタT5〜T9の各閾値の総和VT0を越えると、このス
イッチング回路(トランジスタT5〜T9の直列回路)
はオン状態となり、ノードN1の電圧VN1は電圧降下を
起こすことになる。
However, when the voltage VN1 of the node N1 tries to approach the power supply voltage VDD due to the cut-off state and exceeds the sum VT0 of the threshold values of the transistors T5 to T9 as diode-connected switching circuits, this switching circuit (transistor T5 ~ T9 series circuit)
Is turned on, and the voltage VN1 of the node N1 causes a voltage drop.

【0024】カレントミラー回路M1,M2及び抵抗R
1からなる閉ループ回路においては、このノードN1の
電圧降下によりノードN1の電流にI1が流れ始め、帰
還回路である2つのカレントミラー回路M1,M2の電
流利得の積が1となった状態で安定状態に戻るのであ
る。
Current mirror circuits M1 and M2 and resistor R
In the closed loop circuit composed of 1, the voltage drop of the node N1 causes I1 to start flowing in the current of the node N1 and is stable in a state where the product of the current gains of the two current mirror circuits M1 and M2, which is the feedback circuit, is 1. It returns to the state.

【0025】ダイオード接続されたトランジスタT5〜
T9の直列接続段数は、これ等各トランジスタの閾値の
総和VT0が安定状態時のノードN1の電圧VN1より高電
位になる様に定められるものとする。これは、定電流源
回路が安定動作時に、ダイオード接続されたトランジス
タT5〜T9をカットオフとしておくためである。
Diode-connected transistor T5
The number of serially connected stages of T9 is set so that the sum VT0 of the thresholds of these transistors becomes higher than the voltage VN1 of the node N1 in the stable state. This is because the diode-connected transistors T5 to T9 are cut off during the stable operation of the constant current source circuit.

【0026】[0026]

【発明の効果】叙上の如く、本発明によれば、定常時に
は完全にオフ状態で起動時にのみオンとなるスイッチン
グ回路を付加して自励式としたので、安定した定電流を
得ることができると共に、自励回路には定常電流が流れ
ないという効果がある。
As described above, according to the present invention, a switching circuit which is completely in an off state in a steady state and is turned on only at the time of starting is added to be a self-excited type, so that a stable constant current can be obtained. At the same time, there is an effect that a steady current does not flow in the self-excited circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】従来の定電流源回路の一例を示す回路図であ
る。
FIG. 2 is a circuit diagram showing an example of a conventional constant current source circuit.

【図3】従来の定電流源回路の他の例を示す回路図であ
る。
FIG. 3 is a circuit diagram showing another example of a conventional constant current source circuit.

【符号の説明】[Explanation of symbols]

M1,M2 カレントミラー回路 T1〜T4 カレントミラートランジスタ T5〜T9 ダイオード構成のトランジスタ T10 負荷トランジスタ T11 定電流導出用トランジスタ N1,N2 ノード R1 抵抗素子 M1 and M2 current mirror circuit T1 to T4 current mirror transistor T5 to T9 diode configuration transistor T10 load transistor T11 constant current deriving transistor N1 and N2 node R1 resistance element

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1及び第2のノードと、前記第1のノ
ードに第1の電流を、前記第2のノードに電流利得に応
じた第2の電流を夫々供給する第1のカレントミラー回
路と、前記第2のノードに前記第2の電流を、前記第1
のノードに電流利得に応じた第3の電流を夫々供給する
第2のカレントミラー回路と、前記第2のカレントミラ
ー回路の電流利得を定める抵抗素子とを含む定電流源回
路であって、前記第1のノードと基準電位点との間に、
この第1のノードの通常動作時の電圧よりも大なる閾値
を有するスイッチング回路を有することを特徴とする定
電流源回路。
1. A first current mirror for supplying first and second nodes, and a first current to the first node and a second current to the second node according to a current gain, respectively. A circuit, the second current to the second node, the first current
A constant current source circuit including a second current mirror circuit for respectively supplying a third current according to a current gain to the node of, and a resistance element for determining a current gain of the second current mirror circuit, Between the first node and the reference potential point,
A constant current source circuit having a switching circuit having a threshold value higher than the voltage of the first node during normal operation.
【請求項2】 前記スイッチング回路は、ダイオード接
続構成のトランジスタ素子が複数個直列接続されている
ことを特徴とする請求項1記載の定電流源回路。
2. The constant current source circuit according to claim 1, wherein the switching circuit has a plurality of diode-connected transistor elements connected in series.
JP29263393A 1993-10-27 1993-10-27 Constant current source circuit Pending JPH07121255A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP29263393A JPH07121255A (en) 1993-10-27 1993-10-27 Constant current source circuit
EP19940116889 EP0651311A2 (en) 1993-10-27 1994-10-26 Self-exciting constant current circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29263393A JPH07121255A (en) 1993-10-27 1993-10-27 Constant current source circuit

Publications (1)

Publication Number Publication Date
JPH07121255A true JPH07121255A (en) 1995-05-12

Family

ID=17784322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29263393A Pending JPH07121255A (en) 1993-10-27 1993-10-27 Constant current source circuit

Country Status (2)

Country Link
EP (1) EP0651311A2 (en)
JP (1) JPH07121255A (en)

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US6498528B2 (en) 2000-02-08 2002-12-24 Matsushita Electric Industrial Co., Ltd. Reference voltage generation circuit
KR100685090B1 (en) * 2006-01-05 2007-02-22 주식회사 케이이씨 Constant current driving circuit
JP2007507027A (en) * 2003-09-26 2007-03-22 アトメル グルノーブル Integrated circuit with automatic start function
JP2007279957A (en) * 2006-04-05 2007-10-25 Seiko Epson Corp Current source circuit and comparator having the same
US8933682B2 (en) 2009-08-14 2015-01-13 Spansion Llc Bandgap voltage reference circuit

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Publication number Priority date Publication date Assignee Title
SE9801116D0 (en) * 1998-03-30 1998-03-30 Astra Ab Electrical device
JP4878243B2 (en) 2006-08-28 2012-02-15 ルネサスエレクトロニクス株式会社 Constant current circuit

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JPS59133618A (en) * 1983-01-21 1984-08-01 Hitachi Ltd Bias generating circuit
JPS616717A (en) * 1984-06-21 1986-01-13 Matsushita Electric Ind Co Ltd Reference output circuit

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JPS59133618A (en) * 1983-01-21 1984-08-01 Hitachi Ltd Bias generating circuit
JPS616717A (en) * 1984-06-21 1986-01-13 Matsushita Electric Ind Co Ltd Reference output circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498528B2 (en) 2000-02-08 2002-12-24 Matsushita Electric Industrial Co., Ltd. Reference voltage generation circuit
US6806764B2 (en) 2000-02-08 2004-10-19 Matsushita Electric Industrial Co., Ltd. Reference voltage generation circuit
JP2007507027A (en) * 2003-09-26 2007-03-22 アトメル グルノーブル Integrated circuit with automatic start function
KR100685090B1 (en) * 2006-01-05 2007-02-22 주식회사 케이이씨 Constant current driving circuit
JP2007279957A (en) * 2006-04-05 2007-10-25 Seiko Epson Corp Current source circuit and comparator having the same
US8933682B2 (en) 2009-08-14 2015-01-13 Spansion Llc Bandgap voltage reference circuit

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