JPS59133618A - Bias generating circuit - Google Patents

Abstract

PURPOSE:To eliminate operation defects at a start time, by providing a starting circuit, which consists of a diode-connected N-channel MISFET, for the purpose of securing the operation at the power-on time of a bias circuit. CONSTITUTION:For the purpose of securing the operation at the power-on time of the bias circuit consisting of MISFETs T1-T5, the starting circuit consisting of a diode-connected N-channel MISFETT6 is provided. If the potential of a node N2 does not rise to enough value to make the FETT1 conductive though the power source is turned on, the voltage detecting means T6 is made conductive in accordance with this potential to raise the potential of the node N2. Thus, if enough capacity divided voltage to make the FETT1 conductive appears in the node N2 though the capacity divided voltage appearing between gates and sources of FETs T4 and T5 is lower than a threshold voltage, a bias current is given to the FETT4 by the FETT1 which is made conductive. Consequently, the circuit consisting of FETs T1-T5 enters into the operating state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias generation circuit using a mechanical SI'BT, and particularly to improvement of circuit operation at startup.

A patent application has been filed regarding a reference voltage generating circuit which is composed of a 0M08 circuit and has excellent temperature characteristics. (%Application No. 56-119072) The inventor of the present invention has studied such circuits and found that, even though the power is turned on, the circuits often do not start operating. FIG. 1 is a specific circuit diagram thereof.

Therefore, one object of the present invention is to provide a bias generation circuit which eliminates malfunctions at startup.

One object of the present invention is to provide a bias generation circuit that has a startup circuit and is applicable to a wide power supply range.

One object of the present invention is to obtain P 8 RR (pnwer 8u
p-p17 Rejeclon Rat;io)
That is, the object of the present invention is to provide a bias generation circuit that has a good power supply pull rejection ratio, and that starts up reliably.

One object of the present invention is to provide a bias generation circuit whose bias output voltage has little dependence on hot water temperature and which can be activated reliably.

The cause of startup failure in such a bias generation circuit will be explained with reference to FIG. In the same figure, the gate electrode is made of T2 P+ type polysilicon layer (T2).
5FET (hereinafter P'-gate N-channel M OFF!
(referred to as T), and the others are H-channel M spg'r with gate electrodes made of normal N+ type polysilicon layers.
(referred to as N-bottom N-channel M-8FBT) and a gate consisting of a P+ type polysilicon layer) 1! It is a P channel M type 8FET with fief. The circuit is T4+T
According to the current mirror composed of 5, t is proportional to each other.
The purpose is to supply a current to T, , T, and obtain a bias voltage approximately corresponding to the vth (threshold voltage) difference between T1 and T, that is, the band gap. According to the analysis by the present inventor, V due to process variations
In 4 cases, it is clear that there is a mode in which such a circuit does not start up due to variations or fluctuations in th, etc. That is, in the illustrated circuit, when the power supply voltage is not applied, the divided voltage created by the unillustrated parasitic capacitance between vDD and N1 and between the ground and N is applied between the node N and the power supply terminal ■DD. will appear. Similarly, VD
A voltage that fluctuates due to the parasitic capacitance not shown between 'D' and y and between the ground and N2 will appear between the node N2 and the ground point. However, in the source condition,
TI and T4 remain off because the voltages applied between their respective sources and gates do not reach their respective V th , and in exactly the same way T, , TII remain off. As a result, the circuit will not start up forever.

FIG. 2 is a circuit diagram of a hole bias generation circuit provided with a start-up circuit to ensure circuit start-up.

In the same figure, T is P (ge) - N channel M18'g
BIT and others are normal N game) N Chisenel M Engineering S 7
1! ! T and P gate P channel MIEIFET. According to the normal 0MO8 integrated circuit process, the P channel FFtTT*, T8 is fabricated on an N-type S1 substrate. N gate Ncha wood F'KT 'r,
, T, ,'I'6 are formed on a P-type well region formed on an N short-day substrate, and their gates are made of polycrystalline 81 doped to N-type, such as 511.

On the other hand, P+ gate N channel FFl! T T2 (the gate electrode is indicated by a bold line in the figure) is formed in the P-type well region, and most of the gate is made of P-type doped polycrystalline S1.
It's getting better. When a power supply voltage is applied to such a circuit, under the worst condition, as shown in FIG.
Voltage between Nt -vl)D.

N! - The voltage between ground is 7Vth(5), Vth(
1) (hereinafter, vth' of FEIT T)
It is indicated by evth(N). ) As a result, TI + T5
If the switch does not turn on, it tends to get wet.

Referring to FIG. 2, an explanation will be given of the operation when the power is applied to the hole. First, a case will be described in which the circuit starts up without the starting switch FET 'r6 being activated.

Parasitic capacitance exists between the node N and the terminal vDD and between the node N and the ground terminal. Engineering 5F1nT T4. A capacitive divided voltage appears between the gate and source of l1ll+. Similarly, a capacitance-divided voltage appears between the node N2 and the ground terminal due to the parasitic capacitance between the node 1 and the vDD terminal and the parasitic capacitance between the node N1 and the ground terminal. MI day FF! T'r4. 'r, the capacitive divided voltage appearing between the gate and source of these MI days FF! T'r4.
If it is larger than the threshold voltage of T8, this causes the M5FBT T,,'r8 to start conducting. A bias current is applied to T2 by the electrically connected transistor 5FFiTT5, so that a bias voltage is generated.

M Engineering EIFI! It is conductive by the bias voltage supplied from the iT'r and the 5FKTT. As a result M
A bias current is applied to the 5FET. In this way, 7547 consisting of MI day FET T+ or T5
7 circuits are activated.

Similarly, even if the capacitance-divided voltage appearing between the gate and source of, for example, M-8FKT T, 'r, is smaller than the threshold voltage of these M-8FKT 711', T T4, 'r, by υ, If a capacitance-divided voltage sufficient to make fc conductive appears at node N2, 10Mf8F1nTT becomes conductive.
One bias current is given by IT'r. Therefore, in this case as well, the circuits M5FFfTTt and T are in the operating state.

However, the capacitance-divided voltage applied to the nodes N, , N changes due to changes in the power supply voltage and variations in parasitic capacitance. The threshold voltage of each M-process EINET fluctuates according to moderate process variations. Therefore, the capacitance divided voltage given to node N1 is
'r4. There are times when the capacitor-divided voltage applied to the node N does not reach a sufficient value to make the MEC EIF TT1 conductive. Therefore, when the voltage values applied to nodes N and N2 are determined only by the capacitor-divided voltage, M8F1! IT T4 ,'r,,'r, are left non-conducting.

In other words, the bias circuit consisting of M5FFiT T or T does not become operational even when the power is turned on.

In the circuit shown in Figure 2, M 8FET 'r, no L
- A diode-connected N-channel M
A starting circuit consisting of 5FKTT is provided.

Next, a case in which the starting circuit operates, that is, a case in which the circuit shown in FIG. 2 does not start up with only the original bias circuit will be explained.

Node N despite being powered on.

When the potential of the node N has not risen to a level sufficient to make the M5FET conductive, the voltage detection and setting means T6 becomes conductive and raises the potential of the node N. In this way, M-EIII'ET 'r, , 'r8
The capacitance partial pressure that appears between the gate and source of these MT days F]nT'r4. 'r,'s [1. Even if it is smaller than the threshold voltage, the force and capacitance divided voltage and voltage are sufficient to make M 8FKTT conductive.
Necessary, M Engineering SFI! IT 'r4 is in conductive state tB
The bias current is increased by tM 8F'BITTl. Therefore, in this case as well, M-engineer 8FETT+
The circuit consisting of Ts to Ts becomes operational.

FIG. 3 is a specific circuit diagram of a reference voltage generation circuit according to an embodiment of the present invention. This circuit is an improvement of the circuit shown in FIG. 2 above as follows.

That is, in the circuit of FIG. 2, the output voltage V.

In order to maintain MISFF! at the desired value, MISFF! TTI
and T? It is important to maintain the current flowing through the capacitor at a constant value.

In the circuit of FIG. 2, M engineering SF'BTT, and T! If the current ratio is maintained at the desired value, the output voltage.

Pressure vo is practically M engineering SFI! ! It is equal to the V th difference between T'r and T. The M-type EIFET 'r, formed by IC technology, and the substrate No. 1- (i.e., P-type well region) of T2 are made to have the same characteristics as each other, and
Since the gate insulating films are made of the same material and have the same thickness, the above vth difference is
The gates of T and T are applied with a force substantially equal to the film level difference between the Hp polysilicon layer and the P+ type polysilicon layer constituting the pole. By making the conductivity type determining impurities in each polysilicon layer sufficiently high, the vth difference becomes 5, which is substantially equal to the band width of silicon.

As a result, the output voltage V. υ, which is substantially equal to the bandgap of silicon, is no longer affected by the variations in the respective vt)1 of the M5FET and Tz.

In the circuit of FIG. 2, also, M E]FFtTT1
MI day FETT considering the size ratio of and TI.

By setting the ratio of currents flowing through T and T to an appropriate value, it is possible to obtain an output voltage Vo with sufficiently small temperature dependence, regardless of the temperature dependence of the band gap of silicon.

In the circuit shown in Fig. 2, when the power supply voltage vDD is in a relatively low range, the M'I EIF'
At T6, the circuit stays in the OFF state during operation.

As a result, M Engineering SFI! ! The current ratio of T T and T2 is
M engineering SFF that makes up the current mirror! T T4 and T,
is maintained at a constant value as determined by the dimensional ratio of

However, if the power supply voltage VD is relatively large, that is, the power supply voltage vDI is
If the value is greater than the sum of V t h and MISFEiT 'r6, then MI day FB'l'T
, will be conductive even during operation of the circuit. In addition, M Engineering EIFI! If we follow the normal 0M0S process of creating iT T, , 'r6 at the same time, these MI days FI
T T and V th of T6 are relatively small. Therefore,
As the power supply voltage increases, the possibility that the startup FET remains in a conductive state increases even if the circuit enters an operating state. In this way, there is an undesired 1! on the output side of the current mirror circuit. Naturally, it is difficult to obtain the desired reference voltage output in the current state.

In the circuit shown in Fig. 2, in order to increase the upper limit of the power supply voltage, it is possible to consider increasing the vt, h of the MIFET, but in this case, in order to ensure startup of the circuit, the power supply In order to widen the allowable power supply voltage range and prevent undesired lightning and stagnation as mentioned above, it is necessary to raise the lower limit of the voltage.TI! and T,
It has become clear to the inventor that it is advantageous to insert a suitable resistor or an element or circuit acting as a resistor 7 between the resistors. In the same figure, FF! When TT is conductive L7, a voltage drop appears across the resistor R1. This voltage drop value is set so that the voltage across T6 is smaller than vth(6) during normal operation. If you configure it like this.

Fill! T'rs,'r1! is off, node N! The potential of - is determined regardless of the value of R. Therefore, when the circuit is not activated, T6 becomes conductive and the entire bias circuit can be brought into operation. Furthermore, when the bias circuit enters normal operation, the voltage across T6 becomes below V□ (6) Ja due to the voltage drop that occurs across the resistor R, and as a result -J
uM engineering SFI! This prevents undesired current from flowing into the iTT from sources other than the current mirror circuit. Therefore, according to the present invention, it is possible to provide a highly accurate bias generation circuit that can be applied to a wide power supply voltage range. In the above explanation, a resistive element was shown as the resistance means, but it can also be constructed from other circuits that act as a resistor. Next, an example will be shown in which other functional circuits are used as the resistor means and L7.

FIG. 4 is a specific circuit diagram of another embodiment of the present invention. In the figure, a comparator A1 compares the potentials of the input and output points N, , N, of the Karen mirror 11, and supplies an output voltage corresponding to the difference to the gate of the variable resistance means T7.1.7. Due to the voltage drop between the source and drain of the above nodes Nl, N
! The potential difference between I and I is reduced. As a result, the current mirror circuit consisting of T4 and T11 is able to maintain a current of a predetermined specific height 1t-
I can do it. That is, the drain NR of the M5FET changes in response to changes in the voltage between the drain and source due to the so-called channel length modulation effect. In contrast to the circuit of the embodiment shown in FIG. 4, in the case of the circuit shown in FIG. maintained whereas MI811'l! ! T'
The drain-source voltage of rs is at node N! Since the potential of DD is maintained at a value determined by the diode-connected MIEIFIIITT, if the power source voltage DD changes, it changes accordingly. Therefore, in the case of the circuit shown in FIG. 1, the current amplification circuit of the current mirror circuit changes in response to changes in the power supply voltage.

In the case of the embodiment shown in FIG. 4, Ml: EIFFiTT4 and T5
As mentioned above, the drain-source voltages of the two transistors are practically maintained at the same value regardless of fluctuations in the power supply voltage. As a result, the current amplification output is maintained at a constant value, determined only by the dimensional ratio of M, T, and T, regardless of variations in the source voltage.

As a result, good PEIRR% properties can be obtained.

In this way, by using the circuit for reducing the dependence of current amplification on the power source voltage of the current mirror circuit as a resistor element, a bias generation circuit with a starting circuit can be created without using extra elements. The operating power supply voltage can be widened.

In the same figure, T8 is the node N? considering the case where T7 is off when the startup FIT Tg operates. ni'r
6. A resistive element for supplying ■DD via 'rP. In other words, T7 and T form one variable resistance element. That is, in the illustrated circuit, if the potential rise characteristics at nodes N1 and Nll are not appropriate when the power is turned on, and if the comparator A has an undesired offset value, then when the power is turned on, the MIflFK
The possibility arises that TT is left off. M engineering SFI as a resistance element! When ITTIl is not provided, MSFmTT7 may be undesirably turned off.
The circuit shown in Figure 1 does not start up even though the power is turned on. M18F111TTs have 3 and N! on the nodes! Between! forming a flow path, node N,
The bias voltage required for starting the circuit is applied to the circuit. In addition, M Engineering 8711! '1'rs, comparator A is active and node N is controlled by MlSF'FITT7.

In order to make it possible to control the potential of , the conductance is designed to have a sufficiently high conductance tJ-i.

As explained above, according to the present invention, by adding a start-up switch that operates only when the circuit falls into an undesired state, fluctuations in the output voltage can be reduced and
It is possible to provide a base voltage generation circuit that completely eliminates startup failures. Further, when the present invention is applied to an ordinary complementary semiconductor integrated circuit, it can be a highly integrated semiconductor circuit because there are few additional circuits. In the above description, it has been implicitly assumed that the probability of malfunction at startup is relatively high, but the magnitude of this occurrence rate does not affect the effectiveness of the present invention in any way. In other words, even if the incidence of defects is very small, 1
For example, in a system such as a digital telephone exchange that uses a large number of the same semiconductor integrated circuits, the occurrence of such defects poses a serious problem to the system as a whole. Although this may not always occur, it is very important when the power supply itself is constantly turned on and off by external signals. Furthermore, even when used as a circuit, the base voltage is important for the good operation of various functional circuits, and is also important for ensuring the reliability of the overall operation of semiconductor circuits, etc. becomes.

In the above description, the basic voltage generation circuit was explained for convenience, but the present invention is not limited to this, but can be applied to any circuit that can perform a state in which no current flows through the current mirror circuit at startup. . In addition, in the description of the present invention, PPT and N-type gate N-chaffle M are used from P gate N channel M.
Although the case where a voltage approximately equal to the vth difference of F chicken T is outputted has been described, it goes without saying that the present invention is not limited to straw.

It does not matter if the output voltage is obtained from the drain of the M5FInT T2 in FIGS. 3 and 4. In this case, the drain voltage of the M-SPEτT mushroom is an N-channel constant [1Ml8
This is the optimum gate bias voltage for 7IllT. In other words, if vth of the constant current M-factor SFFIT (not shown) varies, the same variation will occur in the M-factor 5F.
This also occurs in the vth of KTTz. As a result, the constant current flow M5FET (not shown) generates a constant current regardless of variations in vt□. Similarly, M-works OFF! T
The drain-source voltage of T4 may be used as a bias voltage for a full constant current P transistor (not shown).

[Brief explanation of drawings]

FIG. 1 is a specific circuit diagram of a conventional basic single voltage generation circuit, FIG. 2 is a specific circuit diagram of a first embodiment of the present invention, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a specific circuit diagram of another embodiment of the present invention. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. (a) first and second power supply terminals; (b) first and second nodes; and (0) the first. is arranged between a second node and the first t source terminal, and by inputting the current flowing through the first node, the current flowing through the second node is proportional to the current at the first node. (d) a current mirror circuit that outputs a current having a value of - a first motor S that generates a bias voltage in response to a bias current supplied through the L2 node;
F]l[fT and (θ) have their drains supplied to the first node, their Saone terminals coupled to the second power supply terminals via resistance means, and their gates connected to the first nodes. The second (DMISFI) which generates the bias current to be passed through the first node by being supplied with a bias voltage;
'! :T and (f) a startup circuit coupled to at least one of the first node and the second node, wherein the potential of at least one of the first and second nodes at least when the power is turned on is a circuit startup circuit. The start-up circuit ensures that the second node and the first MEC EIFET
7. A bias generating circuit characterized in that a second resistance means is connected between the drain of the bias generating circuit and the drain of the bias generating circuit. 2. The bias circuit according to claim 1, wherein the starting circuit is a first rank detection setting means that becomes conductive when the voltage between the terminals exceeds a predetermined value. 3. The bias circuit according to claim 2, wherein the potential detection and setting means comprises a diode-connected 8FET. 4.% Allowance In the bias generation circuit according to claim 1, the second resistance means is a variable resistance means that changes so as to equalize the potentials of the first node and the output point of the current mirror circuit. A bias generation circuit that has a startup circuit that is specially designed to