JP3187299B2 - Power-on reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device using an OS transistor, and more particularly to a power-on reset circuit that generates a reset pulse when power is turned on.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a power-on reset circuit for setting an internal state to an initial state when power is turned on has been widely used. However, recently, it has been required to be able to cope with the widening of the used power supply voltage, the variation in the rising time of the used power supply voltage, the high temperature, and the like, and the conventionally used power-on reset circuit generates a desired pulse. May not be available.

FIG. 9 shows an example of a conventional flip-flop type power-on reset circuit (Japanese Patent Publication No. 2-139).
64, etc.). This circuit comprises capacitors C1,
The nodes N1 and # 2 of the flip-flop are fixed to Vcc and Vss by C2, and a reset signal inside LS # is generated by an external reset pulse.

However, this kind of circuit has the following problems. That is, when the power supply voltage Vcc rises slowly, the node N1 rises due to the capacitor C1, but the sub-threshold leakage current of the nMOS transistor Qn1 in the flip-flop, which should be in the off state, increases, and the node # 1 increases. No longer rise, Vcc
The node N1 to be set on the side is not set to Vcc due to the subthreshold leak, and there is a possibility that a pulse for resetting the inside of the integrated circuit cannot be obtained.

[0005] In addition, variations in the threshold value and processing of the flip-flop transistors (misalignment of contacts, etc.) cause imbalance in the transistors in the flip-flop. For example, the threshold value of the nΜOS transistor is shallow, and that of the pΜΟS transistor is small. If the threshold value is high, the node # 1 that should be set on the Vcc side has nΜO
Since the S transistor Qn1 is turned on earlier than the pMOS transistor Qp1, the S transistor Qn1 is set to the Vss side, and a desired reset pulse may not be obtained. Further, even when the power-on reset circuit is operated under a high temperature condition, a desired reset pulse may not be obtained.

[0006]

As described above, in the conventional power-on reset circuit, when the power supply voltage Vcc rises slowly or when the temperature is high, a desired reset pulse is generated under the influence of the sub-threshold leakage current. Therefore, there is a problem that the inside of the integrated circuit cannot be reliably reset.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a sub-threshold leakage current which becomes a problem when the power supply voltage Vcc rises slowly or when the temperature is high. Regardless, an object of the present invention is to provide a power-on reset circuit which can obtain a desired reset pulse value and can surely reset the inside of an integrated circuit.

[0008]

In order to solve the above problems, the present invention employs the following configuration. That is, according to the present invention (claim 1), in a power-on reset circuit having a MOS structure, a D-type nMOS having a gate connected to a ground terminal Vss, a drain connected to a power supply terminal Vcc, and a source connected to a node N1 is provided. A transistor and a source connected to the power supply terminal Vcc, a gate connected to the node N1,
A pMOS transistor having a drain connected to the node N2.
When the voltage becomes equal to or higher than the voltage determined by the sum of the threshold value of the OS transistor and the threshold value of the pMOS transistor, pM
The OS transistor is turned on to invert the potential of the node N2, and the inversion is used to generate a reset pulse.

Here, preferred embodiments of the present invention include the following. (1) A device serving as a leak path is connected to the node N1 in order to suppress a subthreshold leak current of the nMOS transistor. (2) In order to suppress the sub-threshold leak current of the pMOS transistor, an element serving as a leak path is connected to the node N2. (3) The element serving as a leak path is a MOS transistor having a gate and a drain connected. (4) A MOS transistor for cutting off the current when the pulse is reset must be connected so that a current does not always flow between Vcc and Vss even after generation of the reset pulse.

The present invention (claim 4) provides a power-on reset circuit using a current mirror circuit.
A first nMOS transistor connected between the input terminal of the current mirror circuit and the ground terminal Vss and having a gate as a node N1, an output terminal of the current mirror circuit and a ground terminal Vss;
ss, a second nMOS transistor having a gate as a node N2, a D-type nMOS having a gate connected to the ground terminal Vss, a drain connected to the power supply terminal Vcc, and a source connected to the node N1. A transistor and a pMOS transistor having a source connected to the power supply terminal Vcc and a gate and a drain commonly connected to the node N2.
The potential of the output terminal of the current mirror circuit is inverted when the potential of the current mirror circuit 1 is overtaken, and a reset pulse is generated using the inversion.

Here, preferred embodiments of the present invention include the following. (1) An element serving as a leak path is connected to the node N1 in order to suppress the sub-threshold leak current of the D-type nMOS transistor. (2) A MOS transistor for cutting off the current when the pulse is reset must be connected so that a current does not always flow between Vcc and Vss even after the generation of the reset pulse.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a circuit diagram showing a power-on reset circuit according to a first embodiment of the present invention.
This circuit includes a depletion type (D type) n @ S transistor M1 for generating a reference potential, an enhancement type (E type) p @ S transistor M2, and an E type nMO for a subthreshold current leak path.
S transistors M3, M4, M5 and inverter I
1, I2, I3, I4, and I5.
The sub-threshold current leakage path source is ΜO
A high resistance, a diode (reverse direction), or the like may be used instead of the S transistor.

Specifically, the gate of the nMOS transistor M1 is connected to Vss, the drain is connected to Vcc,
The source is connected to the node N1. The source of the pMOS transistor M2 is connected to Vcc, the gate is connected to the node N1, and the drain is connected to the node N2. The gate and the drain of the nMOS transistor M3 are commonly connected to the node N1, and the source is connected to Vss. The drain of the nMOS transistor M4 is connected to the node N2
And the source is connected to Vss. nMOS
The gate and drain of the transistor M5 are commonly connected to the gate of M4, and the source is connected to Vss.

The inverters I1 to I5 are connected in series with the node N2 as an input, and each of the inverters I1 to I5 may be composed of a well-known pMOS transistor and nMOS transistor. The output of the inverter I3 is output from the node N5 to the outside, and the output of the inverter I5 is applied to the gate of the nMOS transistor M4.

Next, the operation of this embodiment will be described with reference to the operation waveform diagram of FIG. If the power supply voltage Vcc is the same as Vss, all contacts are at Vss in the equilibrium state. At the moment when the power is turned on, node # 2 is at Vss,
When the power supply voltage Vcc is increased from 0 V, pM
Since the OS transistor M2 is off, the potential of the node N2 remains at 0 V without increasing, and the inverter I1
, The nMOS transistor of the inverter I2, and the pMOS transistor of the inverter I3 are turned on, and the output node # 5 rises with Vcc.

Here, the pMOS transistor and the nMOS transistor of the inverter I1 have a reduced on-resistance of the pMOS so that the pMOS is easily turned on first, and nΜO
In order to increase the ON resistance of S, it is better to increase the gate length of the transistor or to reduce the channel width. Further, a difference may be given by a threshold value by changing channel implantation.

In this embodiment, the output node # 5 rising with Vcc is reset to generate a pulse for resetting the inside of the integrated circuit. For this purpose, a D-type nMOS transistor attached to this circuit is used. M1 and the E-type pMOS transistor M2 must be turned on. The method is described below.

By fixing the gate voltage of the D-type n @ S transistor M1 to Vss, as the power supply voltage Vcc on the drain side of M1 rises, the node # 1 on the source side of M1 depends on the characteristics of the D-type nMOS transistor. , Vss-Vth (threshold of M1) almost simultaneously with the power supply voltage Vcc. Since the node N1 on the source side of M1 is connected to the gate of the pMOS transistor M2, M2 still has a gate
The source is off because it is at the same potential. And
When node # 1 reaches Vss-Vth, node # 1 remains at Vss-Vth even if power supply voltage Vcc subsequently rises.

Here, due to the subthreshold leakage of the nMOS transistor M1, there is a possibility that the node # 1, which is constant at Vss-Vth, will rise, especially when the rise time of the power supply voltage Vcc is slow. Therefore, in order to suppress the rise of node # 1 due to the subthreshold leak, n @ OS transistor M3 is connected to node # 1.
To make a leak path. It is preferable to increase the on-resistance so that the node of N1 is not excessively lowered by connecting the transistor M3.

The node N1 is connected to the gate of the pMOS transistor M2. Since the gate voltage of the node M2 is constant, when the source potential Vcc of the pMOS transistor M2 rises, the gate / source of the node M2 is increased. There is a difference by the threshold value of M2 between them. Then, the pMOS transistor M2 turns on, and the potential of the node N2 on the drain side of M2 rises from Vss, so that the inverters I1, I2, I2
3 is inverted and the output node N5 changes from Vcc to Vss, thereby generating a pulse for resetting each circuit.

Also at this time, since the node # 2 is floating until the pMOS transistor M2 is turned on, especially when the rise of the power supply voltage Vcc is slow or at a high temperature, the node # 2 is disconnected due to the subthreshold leakage of the pMOS transistor M2. De N2 may rise.
Therefore, the node に よ り
In order to suppress the rise of the node 2, an nMOS transistor M4 is connected to the node # 2 to form a leak path.

In order to reset the inside of the integrated circuit, the generated reset pulse voltage is applied to a CMOS pMOS or nMOS.
The larger of the absolute values of the MOS threshold values is required. In the circuit of this embodiment, the reset pulse turns on the pMOS transistor after exceeding the reference potential determined by the D-type n @ OS transistor.
It is determined by the sum of OS thresholds.

The sub-threshold leakage current which becomes a problem when the rise of the power supply voltage Vcc is slow or at a high temperature can be reduced by forming a leakage path using the n @ OS transistors M3 and M4.
It is possible to suppress an increase in potential due to a leak current of 1, N2. Therefore, a stable reset pulse can be obtained without depending on the rising of the power supply or the temperature. (Embodiment 2) FIG. 3 is a circuit diagram showing a power-on reset circuit according to a second embodiment of the present invention.

The present embodiment is basically the same as the first embodiment, but differs from the first embodiment in that a gate is connected between the drain of the D-type nMOS transistor M1 and Vcc. E-type nMOS with N5 connected
That is, the transistor M6 is inserted.

With such a configuration, the same effect as that of the first embodiment can be obtained, and the through current is cut off by the nΜOS transistor M6 when the reset pulse falls. Through current during normal operation after power-on can be prevented. (Embodiment 3) FIG. 4 is a circuit diagram showing a power-on reset circuit according to a third embodiment of the present invention.

The present embodiment is basically the same as the first embodiment, except that the potential of the node N1 determined by the D-type nMOS transistor M1 and the E-type nMOS transistor M3 is different from the first embodiment. Is the E type pM
This is what is received by the inverter composed of the OS transistor M2 and the E-type nMOS transistor M4.

In such a configuration, since the node N1 is a gate input, at the beginning of the rise of the power supply voltage,
First, the nMOS transistor M4 is turned on, then N1 becomes constant, and then the pMOS transistor M2
The pMOS transistor M2 is turned on when a difference corresponding to the threshold value occurs between the gate and the source.

Here, since the node N1 is set at a low potential (about 1 V), the nMOS transistor M
4. Since the pMOS transistor M2 is in the ON state, if the pMOS transistor M2 is ON, pMO
The on-resistance of the nMOS transistor M4 is increased so that the S transistor M2 wins.

As described above, in this embodiment, after the nMOS transistor M4 is turned on, the pMOS transistor M2
Is turned on, it is possible to suppress an increase in voltage due to sub-threshold leakage that tends to occur at high temperatures. (Embodiment 4) FIG. 5 is a circuit diagram showing a power-on reset circuit according to a fourth embodiment of the present invention.

This circuit comprises a current mirror composed of E type pMOS transistors Mp1 and Mp2, an E type nMOS transistor Mn1 connected to the input terminal of the current mirror, and an E type nMOS transistor Mn1 connected to the output terminal of the current mirror. nΜOS transistor Mn2, D-type nMOS transistor MN3 for determining the input potential of the gate of Mn1, E-type pMOS transistor Mp3 for determining the input potential of the gate of Mn2, and E-type nMOS for the leakage path of the subthreshold current It is composed of a transistor Mn4 and inverters I1 and I2 that receive a current mirror output and output a reset pulse.

Next, the operation of this embodiment will be described with reference to the operation waveform diagram of FIG. The input potential node N1 of the nMOS transistor Mn1 connected to the input terminal of the current mirror is formed by a D-type n @ OS transistor Mn3. By fixing the gate voltage of the D-type n @ OS transistor Mn3 to Vss, as the power supply voltage Vcc on the drain side of Mn3 increases, the node N1 on the source side of Mn3 also increases to Vss-Vth simultaneously with Vcc. When the potential Vss-Vth is reached, the node N1 becomes constant at Vss-Vth even if Vcc subsequently rises.

NM connected to the output terminal of the current mirror
The input potential node N2 of the OS transistor Mn2 is formed by an E-type pMOS transistor Mp3.
The source voltage of the OS transistor Mp3 is Vcc, and the gate and the drain are connected to the same potential. The power supply voltage V
When cc is increased from 0 V, a difference corresponding to the threshold value of Mp3 occurs between the gate and the source, the p @ OS transistor Mp3 is turned on, and the node # 2 rises with a threshold value delayed from the drain potential Vcc.

As described above, the potential of the node # 2 becomes the node N
It rises later than 1. Since the current mirror type is used, when the node # 2 overtakes the node N1, the on-resistance of the nMOS transistor Mn2 becomes nMOS
It becomes smaller than the on-resistance of the transistor Mn1, and V
Node # 3, which has risen to cc, becomes Vss, output N5 also becomes Vss, and a reset pulse can be obtained. (Embodiment 5) FIG. 7 is a circuit diagram showing a power-on reset circuit according to a fifth embodiment of the present invention.

This embodiment is basically the same as the fourth embodiment, but differs from the fourth embodiment only in the nMO.
Between the S transistor Mn1 and Vss, the node N is connected to the gate.
5, an E-type nMOS transistor Mn5 having a gate connected to Vcc is inserted between the nMOS transistor Mn2 and Vss.
That is, n6 was inserted. As shown in FIG. 8, a circuit CI1 including pMOS transistors Mp4 and Mp5, an nMOS transistor Mn7, and inverters I3 and I4 is connected to the gate of the nMOS transistor Mn2.

With this configuration, the same effect as that of the fourth embodiment can be obtained, and the through current is cut off by the nΜOS transistor Mn5 when the reset pulse falls. Through current during normal operation after power-on can be prevented.

[0036]

As described above, according to the present invention, a desired reset pulse value can be obtained regardless of the sub-threshold leakage current which becomes a problem when the power supply voltage Vcc rises slowly or when the temperature is high. Since the reset pulse value does not become lower than the reference potential determined by the depletion type nΜΟS transistor, the inside of the integrated circuit can be reliably reset.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a power-on reset circuit according to a first embodiment.

FIG. 2 is an operation waveform diagram for explaining an operation in the circuit of FIG. 1;

FIG. 3 is a circuit configuration diagram showing a power-on reset circuit according to a second embodiment.

FIG. 4 is a circuit diagram showing a power-on reset circuit according to a third embodiment.

FIG. 5 is a circuit diagram illustrating a power-on reset circuit according to a fourth embodiment.

FIG. 6 is an operation waveform diagram for explaining an operation in the circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a power-on reset circuit according to a fifth embodiment.

FIG. 8 is a circuit configuration diagram specifically showing a circuit CI1 in FIG. 7;

FIG. 9 is a circuit diagram showing a power-on reset circuit according to the related art.

[Explanation of symbols]

M1, Mn3 ... D type n @ OS transistor M2, Mp1 to Mp5 ... E type p @ S transistor M3 to M6, Mn1, Mn2, Mn4 to Mn7 ... E type nMO
S transistors I1 to I5 ... inverters N1 to N5 ... nodes

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-139914 (JP, A) JP-A-4-148316 (JP, A) JP-A-64-44618 (JP, A) JP-A-6-446 196989 (JP, A) JP-A-6-244696 (JP, A) Japanese Utility Model Application Sho 62-73634 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17 / 70

Claims (5)

(57) [Claims] 1. A D-type nMOS transistor having a gate connected to the ground terminal Vss, a drain connected to the power terminal Vcc, a source connected to the node N1, a source connected to the power terminal Vcc, and a gate connected to the node N1 And a pMOS transistor having a drain connected to the node N2. When the power is turned on, the power supply terminal Vcc becomes higher than a voltage determined by the sum of the threshold value of the nMOS transistor and the threshold value of the pMOS transistor. A power-on / reset circuit which turns on the pMOS transistor to invert the potential of the node N2 and generates a reset pulse using the inversion. 2. The power-on reset circuit according to claim 1, wherein an element serving as a leak path is connected to the node N1 in order to suppress a sub-threshold leak current of said nMOS transistor. 3. The power-on reset circuit according to claim 1, wherein an element serving as a leak path is connected to a node N2 to suppress a sub-threshold leak current of said pMOS transistor. 4. An input terminal of a current mirror circuit and a ground terminal Vss.
And a first n whose gate is a node N1
A MOS transistor, connected between the output terminal of the current mirror circuit and the ground terminal Vss, and having a gate connected to the node N2
A D-type nMOS transistor having a gate connected to the ground terminal Vss, a drain connected to the power supply terminal Vcc, a source connected to the node N1, a source connected to the power supply terminal Vcc, A pMOS transistor having a gate and a drain commonly connected to the node N2, inverting the potential of the output terminal of the current mirror circuit when the potential of the node N2 exceeds the potential of the node N1 by turning on the power; A power-on reset circuit which generates a reset pulse by utilizing this inversion. 5. A node N1 for suppressing a sub-threshold leakage current of said D-type nMOS transistor.
5. The power-on reset circuit according to claim 4, wherein an element serving as a leak path is connected to the power-on reset circuit.