JPH0482844U - - Google Patents

Info

Publication number
JPH0482844U
JPH0482844U JP12793290U JP12793290U JPH0482844U JP H0482844 U JPH0482844 U JP H0482844U JP 12793290 U JP12793290 U JP 12793290U JP 12793290 U JP12793290 U JP 12793290U JP H0482844 U JPH0482844 U JP H0482844U
Authority
JP
Japan
Prior art keywords
via hole
semiconductor device
chip
pattern
indicates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12793290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12793290U priority Critical patent/JPH0482844U/ja
Publication of JPH0482844U publication Critical patent/JPH0482844U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例である半導体装置
の単一チツプパターンを示す平面図、第2図は第
1図の単一チツプパターンを複数個繰返し形成し
た場合の平面図、第3図は第1図の実施例の優位
性を説明するための他の実施例を示す平面図、第
4図は従来のGaAs FETの斜視図、第5図
は第4図の平面図である。 図において、1はソース電極、2はゲート電極
、3はドレイン電極、6はビア・ホール、8は突
起部を示す。なお、図中、同一符号は同一、また
は相当部分を示す。
FIG. 1 is a plan view showing a single chip pattern of a semiconductor device which is an embodiment of this invention, FIG. 2 is a plan view of a case where the single chip pattern shown in FIG. 1 is repeatedly formed, and FIG. 4 is a perspective view of a conventional GaAs FET, and FIG. 5 is a plan view of FIG. 4. FIG. 4 is a perspective view of a conventional GaAs FET. In the figure, 1 is a source electrode, 2 is a gate electrode, 3 is a drain electrode, 6 is a via hole, and 8 is a protrusion. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

補正 平3.6.14 図面の簡単な説明を次のように補正する。 明細書第7頁第7行〜第8行の「6はビア・ホ
ール、8は突起部を示す。」を「6ビア・ホール
、7はクラツク、8は突起部を示す。」と訂正す
る。
Amendment 3/6/14 The brief description of the drawing is amended as follows. "6 indicates a via hole, 8 indicates a protrusion" on page 7, lines 7 to 8 of the specification is corrected to "6 indicates a via hole, 7 indicates a crack, and 8 indicates a protrusion." .

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ビア・ホール構造を有する半導体装置において
、前記ビア・ホール部と対向するチツプ端面部が
他の部分より突出して突起部を形成され、前記半
導体チツプを複数個繰返し作成するマスクパター
ンが隣接する対の前記チツプパターンの突起部を
互い違いに作成したことを特徴とする半導体装置
In a semiconductor device having a via hole structure, an end face portion of the chip facing the via hole portion protrudes from other portions to form a protruding portion, and a mask pattern for repeatedly forming a plurality of semiconductor chips is formed between adjacent pairs. A semiconductor device characterized in that the protrusions of the chip pattern are formed alternately.
JP12793290U 1990-11-28 1990-11-28 Pending JPH0482844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12793290U JPH0482844U (en) 1990-11-28 1990-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12793290U JPH0482844U (en) 1990-11-28 1990-11-28

Publications (1)

Publication Number Publication Date
JPH0482844U true JPH0482844U (en) 1992-07-20

Family

ID=31875414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12793290U Pending JPH0482844U (en) 1990-11-28 1990-11-28

Country Status (1)

Country Link
JP (1) JPH0482844U (en)

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