JPH0343741U - - Google Patents
Info
- Publication number
- JPH0343741U JPH0343741U JP10356389U JP10356389U JPH0343741U JP H0343741 U JPH0343741 U JP H0343741U JP 10356389 U JP10356389 U JP 10356389U JP 10356389 U JP10356389 U JP 10356389U JP H0343741 U JPH0343741 U JP H0343741U
- Authority
- JP
- Japan
- Prior art keywords
- board
- mounting lead
- soldered
- hole
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000037431 insertion Effects 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の実施例を示す図で、第１図ａ
は要部斜視図、第１図ｂはその方向矢視図、第
１図ｃは対応する基板のパターンを示す図、第２
図は本考案の他の実施例を示す図で、第２図ａは
要部斜視図、第２図ｂはその方向矢視図、第２
図ｃは対応する基板のパターンを示す図、第３図
は本考案のさらに他の実施例を示す図で、第３図
ａは要部斜視図、第３図ｂはその方向矢視図、
第３図ｃは対応する基板のパターンを示す図であ
る。
第１図において、１……基板、２……スルーホ
ール、３……挿入実装用リード、４……フツトパ
ターン、５……表面実装用リードである。
Figure 1 is a diagram showing an embodiment of the present invention, and Figure 1a
1B is a perspective view of the main part, FIG. 1B is a view taken in the direction of arrows, FIG.
The figures show other embodiments of the present invention, in which Fig. 2a is a perspective view of the main part, Fig. 2b is a view taken in the direction of arrows, and Fig.
Figure c is a diagram showing the pattern of the corresponding substrate, Figure 3 is a diagram showing still another embodiment of the present invention, Figure 3a is a perspective view of the main part, Figure 3b is a view taken in the direction of the arrow,
FIG. 3c shows the pattern of the corresponding substrate. In FIG. 1, 1... substrate, 2... through hole, 3... lead for insertion mounting, 4... foot pattern, 5... lead for surface mounting.
Claims (1)
される挿入実装用リード３と、基板１のフツトパ
ターン４上に半田付けされる表面実装用リード５
とを混在させてなる半導体素子のパツケージ。 An insertion mounting lead 3 that is inserted into the through hole 2 of the board 1 and soldered, and a surface mounting lead 5 that is soldered onto the foot pattern 4 of the board 1.
A package of semiconductor elements that is a mixture of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10356389U JPH0343741U (en) | 1989-09-05 | 1989-09-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10356389U JPH0343741U (en) | 1989-09-05 | 1989-09-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0343741U true JPH0343741U (en) | 1991-04-24 |
Family
ID=31652393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10356389U Pending JPH0343741U (en) | 1989-09-05 | 1989-09-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0343741U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234680A (en) * | 2006-02-27 | 2007-09-13 | Kyocera Corp | Electronic circuit board and electronic device |
-
1989
- 1989-09-05 JP JP10356389U patent/JPH0343741U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234680A (en) * | 2006-02-27 | 2007-09-13 | Kyocera Corp | Electronic circuit board and electronic device |
| JP4671426B2 (en) * | 2006-02-27 | 2011-04-20 | 京セラ株式会社 | Electronics |