JPH0418459U - - Google Patents

Info

Publication number
JPH0418459U
JPH0418459U JP5992390U JP5992390U JPH0418459U JP H0418459 U JPH0418459 U JP H0418459U JP 5992390 U JP5992390 U JP 5992390U JP 5992390 U JP5992390 U JP 5992390U JP H0418459 U JPH0418459 U JP H0418459U
Authority
JP
Japan
Prior art keywords
high frequency
transistor
utility
spaced apart
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5992390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5992390U priority Critical patent/JPH0418459U/ja
Publication of JPH0418459U publication Critical patent/JPH0418459U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例である高周波高出
力トランジスタの平面図、第2図は従来の高周波
高出力トランジスタの平面図である。 図において、1はトランジスタチツプ、2はト
ランジスタパツケージ、3はMOS−C、4はワ
イヤを示す。なお、図中、同一符号は同一、もし
くは相当部分を示す。
FIG. 1 is a plan view of a high frequency, high power transistor which is an embodiment of this invention, and FIG. 2 is a plan view of a conventional high frequency, high power transistor. In the figure, 1 is a transistor chip, 2 is a transistor package, 3 is a MOS-C, and 4 is a wire. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランジスタチツプを交互に互いに離して並べ
たことを特徴とする高周波高出力トランジスタ。
A high frequency, high output transistor characterized by transistor chips arranged alternately and spaced apart from each other.
JP5992390U 1990-06-05 1990-06-05 Pending JPH0418459U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5992390U JPH0418459U (en) 1990-06-05 1990-06-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5992390U JPH0418459U (en) 1990-06-05 1990-06-05

Publications (1)

Publication Number Publication Date
JPH0418459U true JPH0418459U (en) 1992-02-17

Family

ID=31586852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5992390U Pending JPH0418459U (en) 1990-06-05 1990-06-05

Country Status (1)

Country Link
JP (1) JPH0418459U (en)

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