JPH0482846U - - Google Patents
Info
- Publication number
- JPH0482846U JPH0482846U JP1990127928U JP12792890U JPH0482846U JP H0482846 U JPH0482846 U JP H0482846U JP 1990127928 U JP1990127928 U JP 1990127928U JP 12792890 U JP12792890 U JP 12792890U JP H0482846 U JPH0482846 U JP H0482846U
- Authority
- JP
- Japan
- Prior art keywords
- wires
- utility
- scope
- registration request
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Microwave Amplifiers (AREA)
Description
第1図は本考案の一実施例である高周波高出力
トランジスタの平面図、第2図は第1図の側面図
、第3図は従来のトランジスタの平面図、第4図
は第3図の側面図である。
図において、1はトランジスタチツプ、2は内
部リード、3はMOS−C、4はワイヤー、5は
外部リード、6はパツケージを示す。なお、図中
、同一符号は同一、又は相当部分を示す。
Figure 1 is a plan view of a high-frequency, high-output transistor that is an embodiment of the present invention, Figure 2 is a side view of Figure 1, Figure 3 is a plane view of a conventional transistor, and Figure 4 is the same as Figure 3. FIG. In the figure, 1 is a transistor chip, 2 is an internal lead, 3 is a MOS-C, 4 is a wire, 5 is an external lead, and 6 is a package. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
れぞれを結ぶループ形状の異なるワイヤーとを備
えたことを特徴とする高周波高出力トランジスタ
。 A high frequency, high output transistor characterized by being equipped with a transistor chip, a MOS type capacitor, and wires with different loop shapes connecting each.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990127928U JPH0482846U (en) | 1990-11-28 | 1990-11-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990127928U JPH0482846U (en) | 1990-11-28 | 1990-11-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0482846U true JPH0482846U (en) | 1992-07-20 |
Family
ID=31875410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990127928U Pending JPH0482846U (en) | 1990-11-28 | 1990-11-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0482846U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432778B2 (en) | 2001-02-28 | 2008-10-07 | Freescale Semiconductor, Inc. | Arrangement and method impedance matching |
-
1990
- 1990-11-28 JP JP1990127928U patent/JPH0482846U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432778B2 (en) | 2001-02-28 | 2008-10-07 | Freescale Semiconductor, Inc. | Arrangement and method impedance matching |