JPS6379651U - - Google Patents

Info

Publication number
JPS6379651U
JPS6379651U JP1986173852U JP17385286U JPS6379651U JP S6379651 U JPS6379651 U JP S6379651U JP 1986173852 U JP1986173852 U JP 1986173852U JP 17385286 U JP17385286 U JP 17385286U JP S6379651 U JPS6379651 U JP S6379651U
Authority
JP
Japan
Prior art keywords
lead frame
groove
protrusion
semiconductor device
circumferential surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986173852U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986173852U priority Critical patent/JPS6379651U/ja
Publication of JPS6379651U publication Critical patent/JPS6379651U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のリードフレームの一実施例を
示す横断面図である。第２図は従来のリードフレ
ームの一実施例を示す横断面図である。 １：トランジスターチツプ、２：半田、３：Ｖ
溝、４：リードフレーム、５：ダイパツト部、６
：溝、７：突堤。 FIG. 1 is a cross-sectional view showing one embodiment of the lead frame of the present invention. FIG. 2 is a cross-sectional view showing an example of a conventional lead frame. 1: Transistor chip, 2: Solder, 3: V
Groove, 4: Lead frame, 5: Die part, 6
: Ditch, 7: Jetty.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードフレームのダイパツト部のトランジスタ
ーチツプが搭載される部面の周面に、溝と更にそ
の外側に突堤とを有することを特徴とする半導体
装置用リードフレーム。 A lead frame for a semiconductor device, comprising a groove and a protrusion on the outside of the groove on the circumferential surface of a die pad portion of the lead frame on which a transistor chip is mounted.
JP1986173852U 1986-11-12 1986-11-12 Pending JPS6379651U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986173852U JPS6379651U (en) 1986-11-12 1986-11-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986173852U JPS6379651U (en) 1986-11-12 1986-11-12

Publications (1)

Publication Number Publication Date
JPS6379651U true JPS6379651U (en) 1988-05-26

Family

ID=31111700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986173852U Pending JPS6379651U (en) 1986-11-12 1986-11-12

Country Status (1)

Country Link
JP (1) JPS6379651U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303216A (en) * 2005-04-21 2006-11-02 Denso Corp Resin-sealed semiconductor device
JP2008177496A (en) * 2007-01-22 2008-07-31 Matsushita Electric Ind Co Ltd Lead frame, package component, semiconductor apparatus, and production method therefor
JP4738983B2 (en) * 2005-11-08 2011-08-03 ローム株式会社 Semiconductor device
JP2014060211A (en) * 2012-09-14 2014-04-03 Omron Corp Substrate structure, semiconductor chip mounting method and solid state relay
CN111916420A (en) * 2019-05-08 2020-11-10 三菱电机株式会社 Semiconductor device and method for manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303216A (en) * 2005-04-21 2006-11-02 Denso Corp Resin-sealed semiconductor device
JP4609172B2 (en) * 2005-04-21 2011-01-12 株式会社デンソー Resin-sealed semiconductor device
JP4738983B2 (en) * 2005-11-08 2011-08-03 ローム株式会社 Semiconductor device
JP2008177496A (en) * 2007-01-22 2008-07-31 Matsushita Electric Ind Co Ltd Lead frame, package component, semiconductor apparatus, and production method therefor
JP2014060211A (en) * 2012-09-14 2014-04-03 Omron Corp Substrate structure, semiconductor chip mounting method and solid state relay
CN111916420A (en) * 2019-05-08 2020-11-10 三菱电机株式会社 Semiconductor device and method for manufacturing the same

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