JPH0474868B2 - - Google Patents
Info
- Publication number
- JPH0474868B2 JPH0474868B2 JP58052431A JP5243183A JPH0474868B2 JP H0474868 B2 JPH0474868 B2 JP H0474868B2 JP 58052431 A JP58052431 A JP 58052431A JP 5243183 A JP5243183 A JP 5243183A JP H0474868 B2 JPH0474868 B2 JP H0474868B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- substrate
- network
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002131 composite material Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 11
- 239000006247 magnetic powder Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 230000035699 permeability Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】 本発明は複合部品の構造に関する。[Detailed description of the invention] The present invention relates to the construction of composite parts.
複合部品は多数の電子素子を基板上へ塔載し、
素子間の配線を行うことにより構成されるもので
あるが、電子素子を個々に基板に取付けていたの
では非常に能率が悪い。また、集積回路（IC）
を組込む場合に、その分布誘導などの影響により
外部回路と集積回路との間に干渉が生じるなどの
問題があつた。 Composite parts have many electronic elements mounted on a substrate,
Although it is constructed by wiring between the elements, it is extremely inefficient to attach the electronic elements individually to the board. Also, integrated circuits (ICs)
When incorporating the integrated circuit, there were problems such as interference between the external circuit and the integrated circuit due to the influence of its distributed induction.
本発明の目的はこれらの欠陥の主な部分または
全部を除去することにある。 The purpose of the present invention is to eliminate a major part or all of these defects.
簡単に述べると、本発明の複合電子部品は、電
子素子を塔載する基板として複数個のコンデンサ
を内蔵し且つ周辺にその引出端を有するコンデン
サネツトワーク基板を用いる。次に、この基板の
一方の面に、複合部品の構成に必要な複数個の抵
抗素子を含む抵抗ネツトワークを形成し、その引
出端を基板体の周辺に引出す。この基板の他方の
面には集積回路チツプを塔載し、その引出端をワ
イヤボンデイング、フエースボンデイング等によ
り基板の周辺に引出す。少くとも集積回路チツプ
の表面には高透磁率磁性粉末を混合した樹脂を塗
布または吹付けて磁気シールド層を形成する。上
記の構成により、複合部品の製造工程が著しく簡
略化される。また複合部品の構造自体も非常に単
純となり品質の安定化に役立つことになる。 Briefly stated, the composite electronic component of the present invention uses a capacitor network board containing a plurality of capacitors and having a lead-out end at the periphery as a board on which electronic elements are mounted. Next, a resistance network including a plurality of resistance elements necessary for constructing the composite component is formed on one surface of this substrate, and its lead end is drawn out around the substrate body. An integrated circuit chip is mounted on the other side of the board, and its lead end is led out to the periphery of the board by wire bonding, face bonding, or the like. At least on the surface of the integrated circuit chip, a magnetic shielding layer is formed by coating or spraying a resin mixed with high magnetic permeability magnetic powder. The above configuration significantly simplifies the manufacturing process of the composite part. Furthermore, the structure of the composite part itself is extremely simple, which helps stabilize quality.
図面を参照するに、第１図はコンデンサネツト
ワークを内蔵する積層誘導体基板１を示す。基板
１は、誘導体粉末をバインダーで練つてペースト
化した誘導体層と、Ag、Ag−Ptなどの導電金属
粉末をペースト化したコンデンサ用電極層及び配
線層とを、交互に積層し、一体焼結し、配線層を
積層誘導体の周辺に引出した部分に外部端子を同
じ金属ペーストまたは低温焼付型導電ペーストで
焼付けて形成される。こうして得られた基板１
は、誘導体部分２、その内部に形成されている複
数個のコンデンサ３、コンデンサ３の相互接続や
引出しを行う配線導体４、及びこれらの導体４の
引出端に接続された複数の外部端子５より成る。 Referring to the drawings, FIG. 1 shows a multilayer dielectric substrate 1 incorporating a capacitor network. The substrate 1 is made by laminating alternately a dielectric layer made by kneading dielectric powder with a binder into a paste, and a capacitor electrode layer and wiring layer made of a paste made of conductive metal powder such as Ag or Ag-Pt, and integrally sintering them. Then, external terminals are formed by baking the same metal paste or low-temperature baking type conductive paste onto the portion where the wiring layer is drawn out around the laminated dielectric. Substrate 1 thus obtained
is from the dielectric portion 2, a plurality of capacitors 3 formed therein, a wiring conductor 4 for interconnecting and drawing out the capacitors 3, and a plurality of external terminals 5 connected to the drawing ends of these conductors 4. Become.
第２図に示すように、この誘導体基板１の片面
には抵抗ネツトワークが形成される。この抵抗ネ
ツトワークは、複数個の抵抗６及び配線導体７か
ら成り、抵抗６は抵抗体粉末のペーストからの印
刷で、また配線導体７は上記と同様の、または低
温焼付型導電体より形成される。引出線は外部端
子に接続され、こうして形成された抵抗ネツトワ
ークは高温または低温焼付けにより基板１へ一体
化される。 As shown in FIG. 2, a resistance network is formed on one side of this dielectric substrate 1. This resistor network consists of a plurality of resistors 6 and wiring conductors 7, where the resistors 6 are printed from a resistor powder paste and the wiring conductors 7 are formed from the same as above or from a low-temperature baking conductor. Ru. The lead wires are connected to external terminals, and the resistor network thus formed is integrated into the substrate 1 by high-temperature or low-temperature baking.
次に、第３図に示すように、基板１の反対側の
面には集積回路（IC）チツプ８が塔載され、引
出ワイヤ９がワイヤボンデイングによりチツプ８
と引出導体５との間に接続される。なお、この接
続はフエースボンデイング等公知の他の方法によ
り行うこともできる。 Next, as shown in FIG. 3, an integrated circuit (IC) chip 8 is mounted on the opposite surface of the substrate 1, and lead wires 9 are attached to the chip 8 by wire bonding.
and the lead-out conductor 5. Note that this connection can also be made by other known methods such as face bonding.
さらに、第４図のように抵抗ネツトワーク面に
は樹脂中に高透磁性磁性粉を混合したペーストを
吹付け加工するか、モールドするかして保護層１
０を形成し、また第５図のように、集積回路チツ
プ８側には同様の磁性ペーストのモールドにより
整形と同時に磁気シールド１１を行う。 Furthermore, as shown in Fig. 4, a protective layer 1 is formed on the resistor network surface by spraying or molding a paste containing highly permeable magnetic powder mixed in resin.
0, and as shown in FIG. 5, a magnetic shield 11 is formed on the integrated circuit chip 8 side by molding a similar magnetic paste at the same time as shaping.
以上のように構成した複合部品は、例えば第６
図に示すような回路を実現することができる。 For example, the composite part configured as described above is
A circuit as shown in the figure can be realized.
以上のように構成したから、本発明の複合部品
は回路構成を単純化できる。従来の構造では集積
回路チツプ、抵抗及びコンデンサが同じ面に塔載
されたため回路を複雑化して製造が困難であつた
が、本発明ではコンデンサネツトワークは基板内
部に、抵抗ネツトワークは基板片面のみに、また
集積回路チツプは他面に別々に形成または塔載し
たので構造が単純化し、製造が容易になつた。 Since the composite component of the present invention is configured as described above, the circuit configuration can be simplified. In the conventional structure, the integrated circuit chip, resistor, and capacitor were mounted on the same side, which made the circuit complicated and difficult to manufacture. However, in the present invention, the capacitor network is inside the board, and the resistor network is only on one side of the board. In addition, the integrated circuit chip was formed separately or mounted on the other side, simplifying the structure and making it easier to manufacture.
第１図は本発明の基板を示す斜視図、第２図は
基板片面上に抵抗ネツトワークを塔載したものの
平面図、第３図は基板他面上に集積回路チツプを
塔載したものの平面図、第４図は本願複合部品の
抵抗ネツトワーク側の外観斜視図、第５図は本願
複合部品の集積回路側の外観斜視図、及び第６図
は本願複合部品の回路側を示す図である。
図中主な部分は次の通り。１：誘電体基板、
２：誘導体、３：コンデンサ、４：配線導体、
５：外部端子、６：抵抗、７：配線導体、８：集
積回路チツプ、９：ワイヤ、１０：磁気シール
ド、１１：磁気シールド。
Fig. 1 is a perspective view showing a substrate of the present invention, Fig. 2 is a plan view of a substrate with a resistor network mounted on one side, and Fig. 3 is a plan view of a substrate with an integrated circuit chip mounted on the other side. 4 is an external perspective view of the resistance network side of the composite component of the present invention, FIG. 5 is a perspective view of the external appearance of the integrated circuit side of the composite component of the present invention, and FIG. 6 is a diagram showing the circuit side of the composite component of the present invention. be. The main parts in the diagram are as follows. 1: dielectric substrate,
2: dielectric, 3: capacitor, 4: wiring conductor,
5: external terminal, 6: resistor, 7: wiring conductor, 8: integrated circuit chip, 9: wire, 10: magnetic shield, 11: magnetic shield.
Claims (1)
導体とよりなるコンデンサネツトワークを内蔵し
た一体焼結誘電体積層体の表面に集積回路チツプ
を搭載して前記電極の引出し導体及び集積回路チ
ツプの引出し導体を積層体周辺に引出し、前記集
積回路チツプを覆つて前記表面に高透磁率磁性粉
末を混合した樹脂の層を設け、更に前記積層体の
裏面に複数の抵抗とそれらの配線導体とよりなる
抵抗ネツトワークを構成してなる複合部品。1. An integrated circuit chip is mounted on the surface of an integral sintered dielectric laminate containing a capacitor network consisting of multiple sets of capacitor electrodes and their connecting conductors, and the lead conductors of the electrodes and the lead conductors of the integrated circuit chip are is drawn out around the laminate, a layer of resin mixed with high permeability magnetic powder is provided on the surface to cover the integrated circuit chip, and a resistor consisting of a plurality of resistors and their wiring conductors is provided on the back surface of the laminate. Composite parts that make up a network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5243183A JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5243183A JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59178768A JPS59178768A (en) | 1984-10-11 |
| JPH0474868B2 true JPH0474868B2 (en) | 1992-11-27 |
Family
ID=12914566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5243183A Granted JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59178768A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261904A (en) * | 1987-04-20 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit for detecting carrier |
| JPS6413137U (en) * | 1987-06-23 | 1989-01-24 | ||
| JP2571389B2 (en) * | 1987-09-03 | 1997-01-16 | ティーディーケイ株式会社 | Stacked hybrid integrated circuit components |
| JP2790640B2 (en) * | 1989-01-14 | 1998-08-27 | ティーディーケイ株式会社 | Structure of hybrid integrated circuit components |
| JPH02102737U (en) * | 1989-02-02 | 1990-08-15 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49120160A (en) * | 1973-03-26 | 1974-11-16 | ||
| JPS568854A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Package for semiconductor device |
-
1983
- 1983-03-30 JP JP5243183A patent/JPS59178768A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49120160A (en) * | 1973-03-26 | 1974-11-16 | ||
| JPS568854A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Package for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59178768A (en) | 1984-10-11 |
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