JPS59178768A - Composite component parts - Google Patents
Composite component partsInfo
- Publication number
- JPS59178768A JPS59178768A JP5243183A JP5243183A JPS59178768A JP S59178768 A JPS59178768 A JP S59178768A JP 5243183 A JP5243183 A JP 5243183A JP 5243183 A JP5243183 A JP 5243183A JP S59178768 A JPS59178768 A JP S59178768A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- dielectric
- composite component
- composite
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】 本発明は複合部品の構造に関する。[Detailed description of the invention] The present invention relates to the construction of composite parts.
複合部品は多数の電子素子を基板上へ塔載し、素子間の
配線を行うことにより構成されるものであるが、電子素
子を個々に基板に取付けていたのでは非常に能率が悪い
。また、集積回路(IC)を組込む場合に、その分布誘
導などの影響により外部回路と集積回路との間に干渉が
生じるなどの問題があった。Composite parts are constructed by mounting a large number of electronic elements on a substrate and wiring between the elements, but it is extremely inefficient to attach the electronic elements individually to the substrate. Furthermore, when an integrated circuit (IC) is incorporated, there is a problem in that interference occurs between an external circuit and the integrated circuit due to the influence of its distributed induction.
本発明の目的はこれらの欠陥の主な部分または全部を除
去することにある。The purpose of the present invention is to eliminate a major part or all of these defects.
簡単に述べると、本発明の複合電子部品は、電子素子を
塔載する基板として複数個のコンデンサを内蔵し且つ周
辺にその引出端を有するコンデンサネットワーク基板を
用いる。次に、この基板の一方の面に、複合部品の構成
に必要な複数個の抵抗素子を含む抵抗ネットワークを形
成し、その引出端を基板体の周辺に引出す。この基板の
他方の面には集積回路チップを塔載し、その引出端をワ
イヤボンディング、フェースボンディング等により基板
の周辺に引出す。必要に応じて少くとも集積回路チップ
の表面には高透磁率磁性粉末を混合した樹脂を塗布また
は吹付けて磁気シールド層を形成する。上記の構成によ
り、複合部品の製造工程が著しく簡略化される。また複
合部品の構造自体も非常に単純となり品質の安定化に役
立つことになる。Briefly stated, the composite electronic component of the present invention uses a capacitor network board containing a plurality of capacitors and having a lead-out end at the periphery as a board on which electronic elements are mounted. Next, a resistance network including a plurality of resistance elements necessary for constructing the composite component is formed on one surface of this substrate, and its lead end is drawn out around the substrate body. An integrated circuit chip is mounted on the other side of the substrate, and its lead end is led out to the periphery of the substrate by wire bonding, face bonding, or the like. If necessary, at least the surface of the integrated circuit chip is coated or sprayed with a resin mixed with high permeability magnetic powder to form a magnetic shield layer. The above configuration significantly simplifies the manufacturing process of the composite part. Furthermore, the structure of the composite part itself is extremely simple, which helps stabilize quality.
図面を参照するに、第1図はコンデンサネットワークを
内蔵する積層誘電体基板1を示す。基板1は、誘電体粉
末をバインダーで練ってペースト化化した誘電体層と、
Ag、Ag−Ptなどの導電金属粉末をペースト化した
コンデンサ用電極層及び配線層とを、交互に積層し、一
体焼結し、配線層を積層誘電体の周辺にiJ1出した部
分に外部端子を同じ金属ペーストまたは低温焼付型導電
ペーストで焼付けて形成される。こうして得られた基板
1は、誘電体部分2、その内部に形成されている複数個
のコンデンサ3、コンデンサ3の相互接続や引出しを行
う配線導体4、及びこれらの導体4の引出端に接続され
た複数の外部端子5より成る。Referring to the drawings, FIG. 1 shows a laminated dielectric substrate 1 incorporating a capacitor network. The substrate 1 includes a dielectric layer made by kneading dielectric powder with a binder and turning it into a paste;
Capacitor electrode layers and wiring layers made of a paste of conductive metal powder such as Ag or Ag-Pt are laminated alternately and sintered together, and external terminals are attached to the portions of the wiring layers that are exposed at iJ1 around the laminated dielectric. It is formed by baking with the same metal paste or low-temperature baking type conductive paste. The substrate 1 thus obtained includes a dielectric portion 2, a plurality of capacitors 3 formed therein, wiring conductors 4 for interconnecting and drawing out the capacitors 3, and connections to the drawing ends of these conductors 4. It consists of a plurality of external terminals 5.
第2図に示すように、この誘電体基板1の片面には抵抗
ネットワークが形成される。この抵抗ネットワークは、
複数個の抵抗6及び配線導体7から成り、抵抗6は抵抗
体粉末のペーストからの印刷で、また配線導体7は上記
と同様の、または低温焼付型導電体より形成される。引
出線は外部端子に接続され、こうして形成された抵抗ネ
ットワークは高温または低温焼付けにより基板1へ一体
化される。As shown in FIG. 2, a resistor network is formed on one side of the dielectric substrate 1. As shown in FIG. This resistance network is
It consists of a plurality of resistors 6 and wiring conductors 7, the resistors 6 being printed from resistor powder paste, and the wiring conductors 7 being formed from the same as above or from a low-temperature baking type conductor. The lead wires are connected to external terminals, and the resistor network thus formed is integrated into the substrate 1 by high-temperature or low-temperature baking.
次に、第3図に示すように、基板1の反対側の面には集
積回路(IC)チップ8が塔載され、引出ワイヤ9がワ
イヤボンディングによりチップ8と引出導体5との間に
接続される。なお、この接続はフェースポンディング等
公知の他の方法により行うこともできる。Next, as shown in FIG. 3, an integrated circuit (IC) chip 8 is mounted on the opposite surface of the substrate 1, and a lead wire 9 is connected between the chip 8 and the lead conductor 5 by wire bonding. be done. Note that this connection can also be made by other known methods such as face bonding.
さらに、第4図のように抵抗ネットワーク面には樹脂中
に高透磁性磁性粉を混合したペーストを吹付は加工する
か、モールドするかして保護層10を形成し、また第5
図のように、集積回路チップ8側には同様の磁性ペース
トのモールドにより整形と同時に磁気シールド11を行
う。Furthermore, as shown in FIG. 4, a protective layer 10 is formed on the surface of the resistor network by spraying or molding a paste containing highly permeable magnetic powder mixed in resin.
As shown in the figure, a magnetic shield 11 is applied to the integrated circuit chip 8 side at the same time as shaping by molding a similar magnetic paste.
以上のように構成した複合部品は、例えば第6図に示す
ような回路を実現Tることができる。The composite component configured as described above can realize a circuit as shown in FIG. 6, for example.
以上のように構成したから、本発明の複合部品は回路構
成を単純化できる。従来の構造では集積回路チップ、抵
抗及びコンデンサが同じ面に塔載されたため回路が複雑
化して製造が困難であったが、本発明ではコンデンサネ
ットワークは基板内部に、抵抗ネットワークは基板片面
のみに、また集積回路チップは他面に別々に形成または
塔載したので構造が単純化し、製造が容易になった。Since the composite component of the present invention is configured as described above, the circuit configuration can be simplified. In the conventional structure, the integrated circuit chip, resistor, and capacitor were mounted on the same side, making the circuit complicated and difficult to manufacture. However, in the present invention, the capacitor network is inside the board, and the resistor network is only on one side of the board. In addition, since the integrated circuit chip is formed separately or mounted on the other side, the structure is simplified and manufacturing is facilitated.
第1図は本発明の基板を示す斜視図、第2図は基板片面
上に抵抗ネットワークを塔載したものの平面図、紀、3
図は基板他面上に集積回路チップを塔載したものの平面
図、第4図は本願複合部品の抵抗ネットワーク側の外観
斜視図、第5図は本願複合部品の集積回路側の外観斜視
図、及び第6図は本願複合部品の回路側を示す図である
。
図中主な部分は次の通り。
1:誘電体基板
2:NノF% 体
6:コンデンサ
4:配線導体
5;外部端子
6:抵抗
7:配線導体
8:集積回路チップ
9:ワイヤ
10:磁気シールド
11:磁気シールドFIG. 1 is a perspective view showing a substrate of the present invention, and FIG. 2 is a plan view of a substrate with a resistor network mounted on one side.
The figure is a plan view of an integrated circuit chip mounted on the other side of the substrate, FIG. 4 is a perspective view of the resistor network side of the composite component of the present invention, and FIG. 5 is a perspective view of the integrated circuit side of the composite component of the present invention. and FIG. 6 are diagrams showing the circuit side of the composite component of the present application. The main parts in the diagram are as follows. 1: Dielectric substrate 2: NnoF% Body 6: Capacitor 4: Wiring conductor 5; External terminal 6: Resistor 7: Wiring conductor 8: Integrated circuit chip 9: Wire 10: Magnetic shield 11: Magnetic shield
Claims (2)
層体の表面に集積回路チップを塔載してその引出導体を
積層体周辺に引出し、前記積層体の裏面に抵抗ネットワ
ークを構成して成る複合部品。(1) A composite in which an integrated circuit chip is mounted on the surface of a dielectric laminate containing a plurality of capacitor electrodes, its lead conductors are drawn out around the laminate, and a resistor network is configured on the back surface of the laminate. parts.
した樹脂の表面層を有する前記第1項記載の複合部品。(2) The composite component according to item 1 above, wherein the integrated circuit chip on the surface has a surface layer of resin mixed with high permeability magnetic powder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5243183A JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5243183A JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59178768A true JPS59178768A (en) | 1984-10-11 |
JPH0474868B2 JPH0474868B2 (en) | 1992-11-27 |
Family
ID=12914566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5243183A Granted JPS59178768A (en) | 1983-03-30 | 1983-03-30 | Composite component parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59178768A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63261904A (en) * | 1987-04-20 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit for detecting carrier |
JPS6413137U (en) * | 1987-06-23 | 1989-01-24 | ||
JPS6464240A (en) * | 1987-09-03 | 1989-03-10 | Tdk Corp | Ic package |
JPH02102737U (en) * | 1989-02-02 | 1990-08-15 | ||
EP0789390A3 (en) * | 1989-01-14 | 1998-01-14 | TDK Corporation | A method for producing multilayer hybrid circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49120160A (en) * | 1973-03-26 | 1974-11-16 | ||
JPS568854A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Package for semiconductor device |
-
1983
- 1983-03-30 JP JP5243183A patent/JPS59178768A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49120160A (en) * | 1973-03-26 | 1974-11-16 | ||
JPS568854A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Package for semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63261904A (en) * | 1987-04-20 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit for detecting carrier |
JPS6413137U (en) * | 1987-06-23 | 1989-01-24 | ||
JPS6464240A (en) * | 1987-09-03 | 1989-03-10 | Tdk Corp | Ic package |
EP0789390A3 (en) * | 1989-01-14 | 1998-01-14 | TDK Corporation | A method for producing multilayer hybrid circuit |
JPH02102737U (en) * | 1989-02-02 | 1990-08-15 |
Also Published As
Publication number | Publication date |
---|---|
JPH0474868B2 (en) | 1992-11-27 |
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