JPS63194395A - Thick film hybrid integrated circuit device - Google Patents
Thick film hybrid integrated circuit deviceInfo
- Publication number
- JPS63194395A JPS63194395A JP62026427A JP2642787A JPS63194395A JP S63194395 A JPS63194395 A JP S63194395A JP 62026427 A JP62026427 A JP 62026427A JP 2642787 A JP2642787 A JP 2642787A JP S63194395 A JPS63194395 A JP S63194395A
- Authority
- JP
- Japan
- Prior art keywords
- wiring conductor
- layer wiring
- integrated circuit
- layer
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 31
- 239000012212 insulator Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 239000011230 binding agent Substances 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000010304 firing Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- METKIMKYRPQLGS-UHFFFAOYSA-N atenolol Chemical compound CC(C)NCC(O)COC1=CC=C(CC(N)=O)C=C1 METKIMKYRPQLGS-UHFFFAOYSA-N 0.000 description 1
- ZADPBFCGQRWHPN-UHFFFAOYSA-N boronic acid Chemical compound OBO ZADPBFCGQRWHPN-UHFFFAOYSA-N 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- 229910000464 lead oxide Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical group [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積密度を高めたｒ！Ｉ−膜混成集積回路装
置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides r! The present invention relates to an I-film hybrid integrated circuit device.
・従来の厚膜混成集積回路装置の回路板の電極多層配線
は絶縁体をホウゲイ酸鉛を主成分とする材料で形成し、
電極多層配線の上層配線導体は銀・バラジューム（Ａｇ
−Ｐｄ）とホウケイ酸鉛ガラスを主成分とする導体を用
いζいるため、該上層配線には半田付接続しない構造と
なっていた。この種の１￥、膜混成集積回路装置として
は、例えば西１・・１孟部著「混成集積回路」 （昭和
４５年）ロ刊工業新開社発行、Ｐ、１０３〜１０４、Ｐ
、２０５〜２０６に記載されているものが挙げられる。・In the electrode multilayer wiring of the circuit board of conventional thick-film hybrid integrated circuit devices, the insulator is formed of a material whose main component is lead boronate.
The upper layer wiring conductor of the electrode multilayer wiring is silver/baladium (Ag
-Pd) and borosilicate lead glass as main components, the structure is such that no solder connection is made to the upper layer wiring. This type of membrane hybrid integrated circuit device includes, for example, "Hybrid Integrated Circuit" by Nishi 1.1 Mengbe (1971), published by Kogyo Shinkaisha, p. 103-104, p.
, 205-206.
上記従来技術においては、電極多層配線を有する回路板
の上層配線を、ディスクリート回路部品のリードに直接
に半【口付等の手段により接続することについて配慮が
なされておらず、直接接続することが困知であった。In the above-mentioned conventional technology, no consideration is given to directly connecting the upper layer wiring of the circuit board having the electrode multilayer wiring to the leads of the discrete circuit components by means such as half-fitting, and direct connection is not possible. It was confusing.
そのため、従来では上記上層配線を下層配線に接続して
からリードに接続しなければならず接続に要するスペー
スを要し、集積密度を向上できないという問題があった
。Therefore, in the past, the above-mentioned upper layer wiring had to be connected to the lower layer wiring and then connected to the leads, which required a space for connection, and there was a problem that the integration density could not be improved.
本発明は、電極多層配線を有する回路基板の上層配線に
、半田付性等の接続活性を（＝Ｊ与増強せしめて、ディ
スクリート回路部品のリードを直接に半田（１等の手段
により接続して、集積密度を向上させることのできる厚
膜混成集積回路装置を提供することを目的とする。The present invention improves the connection activity such as solderability (=J) to the upper layer wiring of a circuit board having multilayer electrode wiring, and connects the leads of discrete circuit components directly by means of soldering (1). An object of the present invention is to provide a thick film hybrid integrated circuit device that can improve integration density.
上記目的は、回路配線の上層の配線導体に半ｔｎ付性を
付与するために、上層のΔｇ、Ｐｄとボウケイ酸鉛ガラ
スを主成分とする導体にガラスが過剰に溶融拡散して、
半田洩れ性がｍなわれることがないように、上記導体の
下部構造となる絶縁体として、■）ｄを含まない結晶化
ガラスを適用することにより達成される。The above purpose is to provide semi-tn adhesion to the wiring conductor in the upper layer of the circuit wiring, by excessively melting and diffusing glass into the upper layer conductor whose main components are Δg, Pd and lead borosilicate glass.
In order to prevent solder leakage, this can be achieved by (1) using crystallized glass that does not contain d as the insulator that forms the lower structure of the conductor.
厚膜混成集積回路基板の上層配線導体に直接外部リード
又は部品リードを接続できることにより、Ｆ記集積回路
基板に重ねて他の回路素子又は回路装置を多重に配置で
き集積密度が向上する。By being able to connect external leads or component leads directly to the upper layer wiring conductor of the thick film hybrid integrated circuit board, other circuit elements or circuit devices can be arranged in multiple layers on top of the F integrated circuit board, improving the integration density.
以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明による厚膜混成集積回路装置の一実施例
を示す要部断面図であって、１はセラミック基板、２は
第１層配線導体、３は第１層絶縁体、４は第２層配線導
体、５は抵抗体、６は第２層絶縁体、７は第３層配線ｍ
体、８は半田」レジスト、９は半田、１０は部品リード
、１１はディスクリート回路部品である。FIG. 1 is a sectional view of essential parts showing an embodiment of a thick film hybrid integrated circuit device according to the present invention, in which 1 is a ceramic substrate, 2 is a first layer wiring conductor, 3 is a first layer insulator, and 4 is a 2nd layer wiring conductor, 5 is a resistor, 6 is a 2nd layer insulator, 7 is a 3rd layer wiring m
8 is a solder resist, 9 is solder, 10 is a component lead, and 11 is a discrete circuit component.
同図において、セラミック基１反１上にＡｇ、ｒ’ｄを
主成分とする導体ペーストを印刷し、８００〜１０００
°Ｃで焼成して第１層配線導体２を形成する。In the same figure, a conductive paste containing Ag and r'd as main components was printed on one ceramic substrate, and
The first layer wiring conductor 2 is formed by firing at °C.
その後、ボウゲイ酸鉛等を主成分とする結晶化ガラスか
らなる絶縁体ペーストを２回重畳印刷し、８００〜１０
００°Ｃで焼成して第１層絶縁体３を形成し、その」二
にΔｇ＋ Ｐｄを主成分とする導体ペーストを印刷し
、８００〜１０００”Ｃで焼成し°Ｃ第２層配線ｍ体４
を形成する。After that, an insulating paste made of crystallized glass whose main component is lead oxide etc. is printed twice, and
The first layer insulator 3 is formed by firing at 00°C, and a conductor paste containing Δg+Pd as a main component is printed on the second layer, and the insulation is fired at 800 to 1000°C to form the second layer wiring body. 4
form.
これは、」―記第１ＷＪ配綿導体２、第１層絶縁体３と
第２層配線導体４により、いわゆるクロスオーバ配線を
構成する。The first WJ cotton conductor 2, the first layer insulator 3, and the second layer wiring conductor 4 constitute a so-called crossover wiring.
また、必要に応じ°Ｃ所望の位置にＲｕ Ｏを等を主成
分とする抵抗ペーストを印刷し、７５０〜９５０°Ｃで
焼成して抵抗体５を形成する。Further, if necessary, a resistor paste containing RuO as a main component is printed at a desired position and fired at 750 to 950°C to form the resistor 5.
更に、上記クロスオーバ配線と抵抗体５を覆うように、
組成が重量％表示で５ｉｏ２：５〜２０、ＡｌｔＯｌ：
０．５〜１０、ＺｎＯ：５２〜６５．８ｇ０３ ：
１５〜３０、Ｎ ａ ｔ Ｏ又はに！Ｏ又はＬ ｉ ｚ
Ｏ： ０．１〜２、ＭＢＯ又はＣａＯ又は３ａＯ：
０．５〜Ｉ Ｏｌ”Ｉ’ｉ０！又はＳｎＯ，：Ｑ〜５の
結晶化ガラスを８５〜９５％、アルミナ（へ１意０、）
、ジルニ１ン（ＺｒＯ８・５ｉＯ２）、コージェライト
（２ＭｇＯ・２ＡｌｚＯａ ・５ＳｉＯ□）のうち
少なくとも１種からなるフィラーを５〜１５％混合比に
て含有する絶縁体ペーストを２〜３回重畳印刷し、５５
０〜６５０’Ｃで焼成して第２１台絶縁体６を形成する
。Furthermore, so as to cover the crossover wiring and the resistor 5,
Composition is 5io2:5-20 in weight%, AltOl:
0.5-10, ZnO: 52-65.8g03:
15-30, Nat O or! O or L i z
O: 0.1-2, MBO or CaO or 3aO:
0.5~IOl"I'i0! or SnO,: 85~95% of Q~5 crystallized glass, alumina (H1~0,)
An insulating paste containing a filler consisting of at least one of Zirnin (ZrO8.5iO2) and cordierite (2MgO.2AlzOa.5SiO□) at a mixing ratio of 5 to 15% is overprinted two to three times. , 55
The 21st insulator 6 is formed by firing at 0 to 650'C.
この第２層絶縁体６上にＡｇ、Ｉ’ｄとホウケイ酸鉛ガ
ラスを主成分とする導体ペーストを印刷し、５５０〜６
５０”Ｃで焼成し”ζ第３層配線導体゛７を形成する。A conductor paste containing Ag, I'd and lead borosilicate glass as main components is printed on this second layer insulator 6, and
It is fired at 50"C to form a third layer wiring conductor"7.
その後、エポキシ変性シリコーン樹脂を主成分とする絶
縁性レジンペーストもしくは非晶質ガラスペーストを印
刷し、１２０〜２５０’Ｃで硬化して半田レジスト８を
形成した回路基板に、ディスクリート回路部品１１の部
品リードＩＯを半ＩＤ９により接続して厚膜混成集積回
路装置を形成する。Thereafter, an insulating resin paste or an amorphous glass paste containing epoxy-modified silicone resin as a main component is printed and cured at 120 to 250'C to form a solder resist 8. The components of the discrete circuit component 11 are then printed on the circuit board. Leads IO are connected by half ID9 to form a thick film hybrid integrated circuit device.
以上説明したように、本発明によれば、電極多１０配線
を有する回路基板の上Ｐｉ導体に直接半［ｎ伺けができ
るため、部品リードを半＋１１付けすることにより接続
配線距１ｒｉ１［が短かくなって、配線インピーダンス
を低減することにより回路特性を改善する効果がある。As explained above, according to the present invention, half [n leads can be directly connected to the upper Pi conductor of the circuit board having 10 wirings for electrodes. This has the effect of improving circuit characteristics by reducing wiring impedance.
また、部品リードの半田（＝Ｊけランドを、特に基板生
地面上に設けずに、上層配線の」二に没けられるため部
品取付けのための配線スペースを狭くすることができ、
集積密度を向上させることができる。In addition, the solder land of the component lead can be sunk into the upper layer wiring without providing it on the board fabric surface, making it possible to narrow the wiring space for mounting the component.
Integration density can be improved.
第１図は本発明による厚膜混成集積回路装置の一実施例
を示す要部断面図である。
１・−−−−−−セラミック基板、２−・−・−第１層
配線導体、３−・・・−第１層絶縁体、４−−−一第２
層配線ｍ体、５−一一一−−−抵抗体、６一−−第２層
絶縁体、７−−〜−第３層配線導体、８−−−−半田レ
シスト、９−−−一−−−半ｆｌ＋、１０− ・一部品
リード、１１−一−−−−ディスクリート回路部２：Ｈ
畳配線導体７二オ３畳配線導体
５：抵↑Ｉ′Ｌ体FIG. 1 is a sectional view of essential parts of an embodiment of a thick film hybrid integrated circuit device according to the present invention. 1. --- Ceramic substrate, 2 --- First layer wiring conductor, 3 --- First layer insulator, 4 --- First layer
Layer wiring m body, 5-111---resistor, 61--second layer insulator, 7---third layer wiring conductor, 8----solder resist, 9--1 --- Half fl+, 10- ・One component lead, 11-1 --- Discrete circuit section 2: H
Tatami wiring conductor 7 2o 3 tatami wiring conductor 5: Resistor ↑I'L body
Claims (1)
１層配線導体の一部を覆うように第１層絶縁体を設け、
この第１層絶縁体上に第２層配線導体を設け、また前記
第１層配線導体の一部に接続するように抵抗体をセラミ
ック基板上に設け、これら第１層配線導体、第１層絶縁
体、第２層配線導体及び抵抗体それぞれの全体もしくは
一部を覆うように第２層絶縁体を設け、前記第１層配線
導体と第２層配線導体の両方もしくはいずれか一方に接
続するように、上記第２層絶縁体上に第３層配線導体を
設け、この第３層配線導体上の一部に半田レジストを設
け、前記第１層配線導体及び第３層配線導体に外部リー
ドもしくは部品のリードを半田付けもしくはワイヤボン
ディング接続してなる厚膜混成集積回路装置において、
前記第２層絶縁体は５５０〜６５００°Ｃの結晶化温度
を有し、しかも鉛元素を含まない結晶化ガラスとフィラ
ーとを主成分とし、かつ前記第３層配線導体はバインダ
ガラスとして鉛元素を含み、集積回路の上層配線導体上
に部品リードを直接に接続する様に構成したことを特徴
とする厚膜混成集積回路装置。1. A first layer wiring conductor is provided on a ceramic substrate, a first layer insulator is provided so as to cover a part of this first layer wiring conductor,
A second layer wiring conductor is provided on the first layer insulator, and a resistor is provided on the ceramic substrate so as to be connected to a part of the first layer wiring conductor. A second layer insulator is provided to cover all or part of each of the insulator, the second layer wiring conductor, and the resistor, and is connected to both or either of the first layer wiring conductor and the second layer wiring conductor. A third layer wiring conductor is provided on the second layer insulator, a solder resist is provided on a part of the third layer wiring conductor, and an external lead is provided on the first layer wiring conductor and the third layer wiring conductor. Or in a thick film hybrid integrated circuit device in which component leads are connected by soldering or wire bonding,
The second layer insulator has a crystallization temperature of 550 to 6,500°C and is mainly composed of crystallized glass and filler that do not contain lead elements, and the third layer wiring conductor has a lead element as a binder glass. What is claimed is: 1. A thick film hybrid integrated circuit device comprising: a thick film hybrid integrated circuit device comprising: a thick film hybrid integrated circuit device comprising: a thick film hybrid integrated circuit device having a structure in which a component lead is directly connected to an upper layer wiring conductor of the integrated circuit;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62026427A JPS63194395A (en) | 1987-02-09 | 1987-02-09 | Thick film hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62026427A JPS63194395A (en) | 1987-02-09 | 1987-02-09 | Thick film hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63194395A true JPS63194395A (en) | 1988-08-11 |
Family
ID=12193217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62026427A Pending JPS63194395A (en) | 1987-02-09 | 1987-02-09 | Thick film hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63194395A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005223809A (en) * | 2004-02-09 | 2005-08-18 | Murata Mfg Co Ltd | Manufacturing method of electronic component |
| US7146719B2 (en) | 2000-06-15 | 2006-12-12 | Murata Manufacturing Co., Ltd. | Multilayer circuit component and method for manufacturing the same |
-
1987
- 1987-02-09 JP JP62026427A patent/JPS63194395A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7146719B2 (en) | 2000-06-15 | 2006-12-12 | Murata Manufacturing Co., Ltd. | Multilayer circuit component and method for manufacturing the same |
| JP2005223809A (en) * | 2004-02-09 | 2005-08-18 | Murata Mfg Co Ltd | Manufacturing method of electronic component |
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