JPH0472672A - Thin-film transistor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase an integration density by a method wherein the channel region of a memory transistor and the channel region of a selective transistor are connected at a part corresponding to the side edge of a lower-part gate electrode. CONSTITUTION:A lower-part gate electrode G, whose shape is the same as that of a gate insulating film 4 for memory transistor is formed on it; and its line part is wired on a substrate 1. The insulating film 4 is formed also under the line part of the lower-part gate electrode G1 over its whole length. Selective transistors T2 are constituted of the following: a semiconductor layer 2; a source electrode and a drain electrode S, D; a gate insulating film 5 for selective transistor use; and an upper-part gate electrode G2. Since a transistor T1 and two transistors T2 situated on both sides of the transistor T1 are formed it is possible to reduce the area of a transistor memory constituted of the transistor T1 and the transistors T2 and to increase an integration density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor memory and a method for manufacturing the same.

[Conventional technology]

Recently, E2FR that can be electrically written, erased, and read
As a memory such as an OM, a thin film transistor memory is considered in which a memory transistor and a selection transistor for selecting the memory transistor are thin film transistors.

Conventionally, this thin film transistor memory is formed by forming a thin film transistor for memory (hereinafter referred to as a memory transistor) and a thin film transistor for selection (hereinafter referred to as a selection transistor) adjacent to each other on an insulating substrate made of glass or the like. A transistor memory is known in which a transistor and a selection transistor are connected in series through a connection wiring that connects the source electrode of one transistor and the drain electrode of the other transistor. Note that the memory transistor and the selection transistor are, for example, Cobraner thin film transistors in which a semiconductor layer, source and drain electrodes, a gate insulating film, and a gate electrode are laminated, and the gate insulating film of the memory transistor is The gate insulating film of the selection transistor is formed of an insulating film having a memory function and has no charge storage function.

[Problem to be solved by the invention]

However, the conventional thin film transistor memory
A memory transistor and a selection transistor are formed adjacent to each other on a substrate, and the memory transistor and selection transistor are connected in series by connection wiring, so a transistor memory composed of a memory transistor and a selection transistor is The problem is that the area is large, and therefore it is difficult to increase the degree of integration of a memory matrix formed by arranging transistor memories vertically and horizontally.

The present invention has been made in view of the above circumstances, and its purpose is to provide a thin film transistor that can reduce the area of a transistor memory composed of a memory transistor and a selection transistor and increase the degree of integration. An object of the present invention is to provide a memory and also a manufacturing method thereof.

[Means to solve the problem]

The thin film transistor memory of the present invention includes a semiconductor layer formed on an insulating substrate, source and drain electrodes formed on both sides of the semiconductor layer, and at least the semiconductor layer formed on a portion of the semiconductor layer. A gate insulating film for a memory transistor having a charge storage function at the interface with the semiconductor layer, a lower gate electrode formed in the same shape as the gate insulating film for the memory transistor, and the lower gate electrode and the semiconductor. a gate insulating film for a selection transistor without a charge storage function covering the layer; and an upper gate electrode formed on the gate insulating film for the selection transistor so as to face at least the entire region between the source and drain electrodes of the semiconductor layer. A memory transistor is configured by the semiconductor layer, the source and drain electrodes, the memory transistor gate insulating film, and the lower gate electrode, the semiconductor layer and the source,
The present invention is characterized in that a selection transistor is constituted by a drain electrode, the selection transistor gate insulating film, and the upper gate electrode.

Further, the method for manufacturing a thin film transistor memory of the present invention includes the steps of: forming a semiconductor layer on an insulating substrate; forming a source, a drain electrode, a source, and a drain electrode on both sides of the semiconductor layer; A gate insulating film for a memory transistor having a charge storage function and a metal film for a lower gate electrode are sequentially deposited on at least the interface with the semiconductor layer, and the metal film and the gate insulating film for a memory transistor are bonded to the semiconductor layer. a step of patterning into a shape corresponding to a part of the layer; a step of depositing a gate insulating film for a selection transistor without a charge storage function on the lower gate electrode and the semiconductor layer; and forming an upper gate electrode facing at least the entire region between the source and drain electrodes of the semiconductor layer.

[Effect]

That is, in the thin film transistor memory of the present invention, one thin film transistor has an upper gate electrode facing at least the entire region between the source and drain electrodes of the semiconductor layer;
A lower gate electrode provided between the upper gate electrode and the semiconductor layer and facing a part of the semiconductor layer.
The lower gate electrode is formed on a gate insulating film for a memory transistor having a charge storage function, which is provided on a portion of the semiconductor layer at least at the interface with the semiconductor layer. The upper gate electrode is formed on a gate insulating film for a selection transistor having no charge storage function, which is laminated on a semiconductor layer and covering the lower gate electrode. A memory transistor and a selection transistor, which share a semiconductor layer and source and drain electrodes, are connected in series in the semiconductor layer.

In this thin film transistor memory, the portion of the semiconductor layer where the lower gate electrodes are opposed becomes the channel region of the memory transistor, and the portion where the lower gate electrodes are not opposed and only the upper gate electrodes are opposed is the channel region of the memory transistor. Since this becomes the channel region of the selection transistor, the selection transistor operates by applying a gate voltage to the upper gate electrode, and the memory transistor operates by applying a gate voltage to the lower gate electrode. Further, the channel region of the memory transistor and the channel region of the selection transistor are formed so as not to be mutually separated at a portion corresponding to a side edge of the lower gate electrode.

Furthermore, in this thin film transistor memory, the upper gate electrode also acts as an electrode that shields the gate voltage applied to the semiconductor layer from the lower gate electrode, which is the gate electrode of the memory transistor, or the upper gate electrode, which is the gate electrode of the selection transistor. The memory transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
After forming a semiconductor layer on an insulating substrate and forming source and drain electrodes on both sides of this semiconductor layer, a gate insulating film for a memory transistor with a charge storage function and a metal film for a lower gate electrode are formed thereon. By sequentially depositing the metal film and the gate insulating film for the memory transistor in a shape corresponding to a part of the semiconductor layer, the gate insulating film for the memory transistor and the lower gate electrode constituting the memory transistor are simultaneously formed. After this, a gate insulating film for a selection transistor having no charge storage function is deposited on the lower gate electrode and the semiconductor layer, and an upper gate electrode is formed thereon, thereby manufacturing the thin film transistor of the present invention. It is something.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 show a first embodiment of the present invention, and FIG. 1 is a sectional view of a thin film transistor memory.

To explain the structure of this thin film transistor memory, numeral 1 in the figure is an insulating substrate made of glass or the like, and on this substrate 1, a semiconductor layer 2 made of i-type amorphous ASKON (ia-a-Si) is formed in a predetermined manner. formed into a shape. Note that the thickness of this semiconductor layer 2 is 1000 layers. and,
On both sides of this semiconductor layer 2, n-type amorphous
Source and drain electrodes S and D are formed via an ohmic contact layer 3 made of silicon (n"-a-Sl). Note that line portions (not shown) of the source and drain electrodes S and D are formed. is formed on the substrate 1, and the ohmic contact layer 3 is formed over the entire length under this line portion.Furthermore, on the central portion of the semiconductor layer 2, a layer for a memory transistor is formed. A gate insulating film 4 is provided.The gate insulating film 4 for the memory transistor is provided with a memory insulating film 4 having a charge storage function. It is a two-layer film consisting of a memory film 4a with a thickness of 100 and a pressure-resistant film 4b with a thickness of 900 and laminated thereon.
b is formed in the same shape. The memory film 4a and the voltage-resistant film 4b are both silicon nitride (SIN) films, and the voltage-resistant film 4b has a composition ratio of silicon atoms Si to nitrogen atoms N (Si/N) that is a stoichiometric ratio. The memory film 4 is made of silicon nitride, which does not have a charge storage function to the same extent, and the memory film 4 is made of silicon nitride, which has a charge storage function by increasing the silicon atomic weight compared to the stoichiometric ratio. Note that the width of the lower gate electrode 4 made of the memory film 4a and the breakdown voltage film 4b in the left-right direction in the drawing is approximately 1/3 of the distance between the source and drain electrodes S and D, and the width in the front and back directions of the paper in the drawing. is formed in an area approximately equal to the width of the semiconductor layer 2.

Moreover, on the gate insulating film 4 for memory transistor,
A lower gate electrode G1 having the same shape as this is formed, and its line portion (not shown) is wired on the substrate 1. Note that the memory transistor gate insulating film 4
is formed also under the line portion of the lower gate electrode G1 over its entire length. 5 is the lower gate electrode G
, a gate insulating film for a selection transistor formed on the substrate 1 to cover the line portion thereof and the semiconductor layer 2, and the gate insulating film 5 for the selection transistor is formed of silicon nitride without a charge storage function. . The film thickness of this selection transistor gate insulating film 5 is 2000 mm. On this selection transistor gate insulating film 5, at least the source and drain electrodes S of the semiconductor layer 2 are provided.
, D. An upper gate electrode G2 and its line portion (not shown) are formed to face the entire region between G2 and D. In this embodiment, the upper gate electrode G2 is formed to be slightly smaller than the semiconductor layer 2, and to have both side edges facing the central portions of the source electrode S and the drain electrode. Further, the line portion of the upper gate electrode G2 is formed at a position that does not vertically overlap with the lower gate electrode G1.

The central part of the thin film transistor memory of this embodiment is a memory transistor T1, and both sides thereof are selection transistors T2, and the memory transistor T has a semiconductor layer 2, a source electrode, a drain electrode S,
D, a gate insulating film 5 for a memory transistor whose interface with the semiconductor layer 2 is a memory film 4a having a charge storage function, and a lower gate electrode G. Further, both sides of this memory transistor T are respectively used as selection transistors G2, and this selection transistor G
2 is the semiconductor layer 2 and the source.

It is composed of drain electrodes S and D, a gate insulating film 5 for a selection transistor, and an upper gate electrode G2. This memory transistor T and the two selection transistors T2 on both sides thereof are formed by a semiconductor layer 2 which is also used for both of them.
are connected in series through. That is, the entire region of the region between the source electrode S and the drain electrode of the semiconductor layer 2, where the lower gate electrode G1 faces, becomes the channel region C1 of the memory transistor T1, and the lower gate electrode G1 becomes the channel region C1 of the memory transistor T1. In the part where only the upper gate electrode G2 is not opposed, the entire area is the selection transistor T.
The channel region C1 of the memory transistor T1 and the channel region G2 of the selection transistor T2 are connected to the lower gate electrode G1.
Since the memory transistor T1 and the two selection transistors T2 on both sides are connected to each other at the portions corresponding to the side edges of the semiconductor layer 2, the memory transistor T1 and the two selection transistors T2 on both sides of the semiconductor layer They are connected in series with conductivity. Also, memory transistor T1
Since the two selection transistors T2 on both sides have a common gate electrode (upper gate electrode) G2, they are turned on and off at the same time.

FIG. 2 shows a method for manufacturing the thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, as shown in FIG. 2(a), a semiconductor layer 2 is formed on a substrate 1 in a predetermined shape. This semiconductor layer 2 is a substrate 1
Type 1 amorphous silicon is deposited thereon to a thickness of 1000 nm, and this i type amorphous silicon layer is formed by patterning.

Next, as shown in FIG. 2(b), an ohmic contact layer 3 and source and drain electrodes S and D are formed on both sides of the semiconductor layer 2, and at the same time, the source and drain electrodes S and D are formed on the substrate 1. , forming line portions of drain electrodes S and D. The source and drain electrodes S and D, their line parts, and the ohmic contact layer 3 are made of n-type amorphous silicon and metal such as chromium on the substrate 1 by 250 people and 500 people.
The metal film and the n-type amorphous silicon layer are sequentially deposited to a thickness of 0.00 mm, and the source and drain electrodes S,
It is formed by patterning in the shape of D and its line portion.

Next, as shown in FIG. 2(c), a memory film (a silicon nitride film with a charge storage function) 4a, which will become the gate insulating film 4 for the memory transistor, and a breakdown voltage film (a silicon nitride film without a charge storage function) are placed on the substrate 1. silicon nitride film) 4b and 100 people, 900
The metal film M for the lower gate electrode, such as chromium, is deposited on top of this to a thickness of 500 mm.

Next, as shown in FIG. 2(d), the metal film M, the gate insulating film 4 for a memory transistor consisting of a memory film 4a and a breakdown voltage film 4b are formed into a shape corresponding to the central part of the semiconductor layer 2. The lower gate electrode G1 made of the metal film M and its line portion, and the gate insulating film 4 for a memory transistor having the same shape as the lower gate electrode G1 are completed.

Next, as shown in FIG. 2(e), a selection transistor gate insulating film (silicon nitride film without charge storage function) 5 is formed over the entire surface of the substrate 1 on the lower gate electrode G1 and the semiconductor layer 2. deposited to a thickness of 2,000 people,
Next, on this selection transistor gate insulating film 5,
The above-mentioned thin film transistor memory is completed by depositing a metal such as chromium to a thickness of 1000 nm and patterning this metal film to form the upper gate electrode G2 and its line portion.

That is, the thin film transistor memory of this embodiment has 1
In one thin film transistor, an upper gate electrode G2 facing at least the entire region between the source and drain electrodes S and D of the semiconductor layer 2, and this upper gate electrode G2 and the semiconductor layer 2 are provided.
and a lower gate electrode G1 provided between and facing the central portion of the semiconductor layer 2, and the lower gate electrode G1 is provided above the central portion of the semiconductor layer 2, The upper gate electrode G2 is formed in the same shape as the memory transistor gate insulating film 4 having a charge storage function at the interface with the semiconductor layer 2, and the upper gate electrode G2 covers the lower gate electrode G1. A gate insulating film 5 for a selection transistor having no charge storage function and laminated thereon.
By forming the memory transistor T1 and the selection transistor T2, which share the semiconductor layer 2 and the source and drain electrodes S and D, in one thin film transistor, the memory transistor T1 and the selection transistor T2 are connected in series in the semiconductor layer 2. It was formed.

According to this thin film transistor memory, a memory transistor T1 and two selection transistors T2 located on both sides of the memory transistor T1 are formed in one thin film transistor. The area of the constructed transistor memory can be reduced and the degree of integration can be increased.

In this thin film transistor memory, the part of the semiconductor layer 2 that is opposed to the lower gate electrode G1 becomes the channel region C1 of the memory transistor T1, and the lower gate electrode G is not opposed to it, but only the upper gate electrode G2. The part facing the selection transistor T2
Since the channel region C2 becomes the upper gate electrode G2
The selection transistor T2 can be operated by applying a gate voltage to the lower gate electrode GI, and the memory transistor T1 can be operated by applying a gate voltage to the lower gate electrode GI.

Further, since the upper gate electrode G2, which is the gate electrode of the selection transistor T2, is formed by wrapping the lower gate electrode G1, which is the gate electrode of the memory transistor T1, the channel region C1 of the memory transistor T1
and the channel region C2 of the selection transistor T2 are formed in a state where they are connected to each other at the portion corresponding to the side edge of the lower gate electrode G, so that the conductivity between the memory transistor T1 and the selection transistor T2 is also good. It is.

Moreover, in this thin film transistor memory, the lower gate electrode G1, which is the gate electrode of the memory transistor T1, also acts as an electrode that shields the gate voltage applied to the semiconductor layer 2 from the lower gate electrode G2, which is the gate electrode of the selection transistor T2. Therefore, the upper gate electrode G
The memory transistor T1 will not malfunction due to the influence of the gate voltage applied to the gate voltage applied to the memory transistor T1. It is possible to perform stable writing, erasing, and reading by operating the memory.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

That is, FIG. 3 is an equivalent circuit diagram of the thin film transistor memory, in which (a) is when writing, (b) is when erasing, (
c) shows the voltage application state during reading.

First, to explain about writing, when writing, Figure 3 (
As shown in a), the source electrode S and the drain electrode are grounded (GND), and the selection transistor T2
On-voltage VON is applied to the gate electrode (upper gate electrode) G2 of
is applied, and a write voltage +VP is applied to the gate electrode (lower gate electrode) G1 of the memory transistor T1. When such a voltage is applied, the two selection transistors T2
are turned on at the same time, and the write voltage +vP applied between the gate electrode G1 of the memory transistor T1 and the semiconductor layer 2 causes the memory transistor gate insulating film 4 to be removed from the semiconductor layer 2.
A charge is injected into the memory transistor gate insulating film 4 at the interface with the semiconductor layer 2 (memory film 4a).
), and the memory transistor T1 enters the write state (off state).

Further, during erasing, as shown in FIG. 3(b), the source electrode S and the drain electrode are grounded (GND), and the on-voltage V is applied to the gate electrode G2 of the selection transistor T2.
oN is applied to the gate electrode G of the memory transistor T1.
, an erase voltage -vP having a potential opposite to the write voltage +VP is applied. When such a voltage is applied, the two selection transistors T2 are turned on simultaneously, and the memory transistor T2 is turned on simultaneously.
Due to the erase voltage -■ applied between the gate electrode G1 of the memory transistor T1 and the semiconductor layer 2, the charges trapped in the memory insulating film 4 are released to the semiconductor layer 2, and the memory transistor T
, becomes an erased state (on state).

On the other hand, during reading, as shown in FIG. 3(c), the gate electrode G and source electrode S of the memory transistor T1 are grounded (GND), and the on-voltage VON is applied to the gate electrode G2 of the selection transistor T2. Then, a read voltage V is applied to the drain electrode. When such a voltage is applied, if the memory transistor T1 is in the erase state (on state), current flows from the drain electrode to the source electrode S due to the two selection transistors T2 being turned on, and the memory transistor T1 is in the write state (on state). In the off state), the current does not flow even if the selection transistor T2 is turned on, so read data is output depending on the presence or absence of a current flowing from the source electrode S to the line portion.

Note that the thin film transistor memory of the above embodiment includes one memory transistor T1 and two selection transistors T2.
However, the present invention can also be applied to a thin film transistor memory that includes one memory transistor T and one selection transistor T2.

4 and 5 show a second embodiment of the present invention, in which FIG. 4 is a sectional view of a thin film transistor memory, and FIG. 5 is an equivalent circuit diagram thereof.

The thin film transistor memory of this embodiment has a memory film 4a.
A gate insulating film 4 for a memory transistor consisting of a withstand voltage film 4b is formed so as to have an area approximately half that of the semiconductor layer 2, and this gate insulating film 4 for a memory transistor is formed to face a half area from the center of the semiconductor layer 2. In addition, a lower gate electrode G, which is the gate electrode of the memory transistor T,
1 is formed on the gate insulating film 4 for the memory transistor in the same shape as this. That is, in the thin film transistor memory of this embodiment, the negative half is the memory transistor T1, and the other half is the selection transistor T2.
That is. Note that the thin film transistor memory of this embodiment has only one selection transistor T2, and the basic configuration is the same as that of the first embodiment.
A detailed description of the structure will be omitted by attaching the same reference numerals to the figures. Further, the thin film transistor memory of this embodiment can be manufactured by a method similar to the manufacturing method described above, and the writing and
Erasing and reading can also be performed in the same manner as in the thin film transistor memory of the first embodiment.

Note that in this embodiment, the upper gate electrode G2 is
However, since the effective part of this upper gate electrode G2 is a part that does not overlap with the lower gate electrode G1, the part of this upper gate electrode G2 that overlaps with the lower gate electrode G1 is the lower gate electrode G
The area may be smaller than 1, and even in that case, if the side edge of the upper gate electrode G2 on the lower gate electrode G1 side overlaps the lower gate electrode G even slightly, the channel region C1 of the memory transistor T1 and the selection transistor T
Since the two channel regions C2 are connected to each other, conductivity between the memory transistor T1 and the selection transistor T2 can be ensured.

Further, in the above embodiment, the gate insulating film 4 for the memory transistor is a two-layer film consisting of the memory film 4a and the breakdown voltage film 4b, but the gate insulating film 4 for the memory transistor is
Since it is sufficient that at least the interface with the semiconductor layer 2 has a charge storage function and sufficient voltage resistance, the gate insulating film 4 for the memory transistor is made entirely of a single film such as silicon nitride that has a charge storage function. It may also be a layered film.

Further, in the above embodiment, the semiconductor layer 2 and the ohmic contact layer 3 are made of amorphous silicon, but the semiconductor layer 2 and the ohmic contact layer 3 may be made of polysilicon (poly-3i). By forming the semiconductor layer 2 and the ohmic contact layer 3 from polysilicon in this manner, the operating speed of the memory transistor T1 and the selection transistor T2 can be increased.

〔Effect of the invention〕

According to the thin film transistor memory of the present invention, since the memory transistor and the selection transistor are formed in one thin film transistor, the area of the transistor memory composed of the memory transistor and the selection transistor is reduced and the degree of integration is increased. be able to. Furthermore, in this thin film transistor memory, the portion of the semiconductor layer where the lower gate electrodes are opposed becomes the channel region of the memory transistor, and the portion where the lower gate electrodes are not opposed and only the upper gate electrodes are opposed is the channel region of the memory transistor. Since it becomes the channel region of the selection transistor, the selection transistor can be operated by applying a gate voltage to the upper gate electrode, and the memory transistor can be operated by applying a gate voltage to the lower gate electrode.
Since the channel region of the memory transistor and the channel region of the selection transistor are connected to each other at the portion corresponding to the side edge of the upper gate electrode, the conductivity between the memory transistor and the selection transistor is also good. It is. Moreover, in this thin film transistor memory, the lower gate electrode, which is the gate electrode of the memory transistor, also acts as an electrode that shields the gate voltage applied to the semiconductor layer from the upper gate electrode, which is the gate electrode of the selection transistor. Since the memory transistor does not malfunction due to the influence of the gate voltage applied to the electrode, even though the memory transistor and the selection transistor are formed in one thin film transistor, the memory transistor can operate normally and be stable. Writing, erasing, and reading can be performed.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
After forming a semiconductor layer on an insulating substrate and forming source and drain electrodes on both sides of this semiconductor layer, a gate insulating film for a memory transistor with a charge storage function and a metal film for a lower gate electrode are formed thereon. By sequentially depositing the metal film and the gate insulating film for the memory transistor in a shape corresponding to a part of the semiconductor layer, the gate insulating film for the memory transistor and the lower gate electrode constituting the memory transistor are simultaneously formed. After that, a gate insulating film for a selection transistor without a charge storage function is deposited on the lower gate electrode and the semiconductor layer, and an upper gate electrode is formed thereon.
The thin film transistor of the present invention can be easily manufactured.

[Brief explanation of the drawing]

1 to 3 show a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a thin film transistor memory, FIG. 2 is a manufacturing process diagram of a thin film transistor memory, and FIG. 3 is a diagram of a thin film transistor memory. It is an equivalent circuit diagram. 4 and 5 are a sectional view and an equivalent circuit diagram of a thin film transistor memory showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Semiconductor layer, 3... Ohmic contact layer, S... Source electrode, D... Drain electrode, 4... Gate insulating film for memory transistor, 4
a... Memory film, 4b... Withstand voltage film, G1... Lower gate electrode, 5... Gate insulating film for selection transistor, G2... Upper gate electrode, T1... Memory transistor, C1... ...Channel region, T2...Selection transistor, C2...Channel region. Applicant: Casio Computer Co., Ltd. 1+l atmosphere-I'A1 Figure 5

Claims (2)

[Claims] (1) A semiconductor layer formed on an insulating substrate, source and drain electrodes formed on both sides of the semiconductor layer, and at least the semiconductor layer formed on a portion of the semiconductor layer. A gate insulating film for a memory transistor having a charge storage function at the interface, a lower gate electrode formed in the same shape as the gate insulating film for the memory transistor, and a charge covering the lower gate electrode and the semiconductor layer. comprising a gate insulating film for a selection transistor having no storage function; and an upper gate electrode formed on the gate insulating film for the selection transistor so as to face at least the entire region between the source and drain electrodes of the semiconductor layer; A memory transistor is constituted by the semiconductor layer, the source and drain electrodes, the memory transistor gate insulating film, and the lower gate electrode, the semiconductor layer, the source and drain electrodes, the selection transistor gate insulating film, and the upper gate electrode. A thin film transistor memory characterized in that a selection transistor is configured with and. (2) forming a semiconductor layer on an insulating substrate; forming source and drain electrodes on both sides of the semiconductor layer; and forming a charge on the substrate at least at the interface with the semiconductor layer. a step of sequentially depositing a gate insulating film for a memory transistor having a storage function and a metal film for a lower gate electrode, and patterning the metal film and the gate insulating film for the memory transistor into a shape corresponding to a portion of the semiconductor layer; depositing a gate insulating film for a selection transistor without a charge storage function on the lower gate electrode and the semiconductor layer; depositing a region between at least the source and drain electrodes of the semiconductor layer on the gate insulating film for the selection transistor; 1. A method for manufacturing a thin film transistor memory, comprising the steps of: forming upper gate electrodes that face each other throughout;