JP2001298100A - Nonvolatile memory, semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory which can be formed together with other semiconductor devices and miniaturized. SOLUTION: Memory TFTs forming a nonvolatile memory, switching TFTs and other peripheral circuits composed of TFTs are formed together on a substrate. The memory TFTs and the switching TFTs are formed on the same semiconductor active layer, and the semiconductor active layer of the memory TFTs is made thinner than the semiconductor active layer of other TFTs. Thus, a low-voltage write/erase of the memory TFT can be realized to provide a nonvolatile memory which is hardly deteriorates and miniaturizable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to SOI (Silicon).
The present invention relates to a nonvolatile memory including a thin film transistor (hereinafter, referred to as a TFT) formed by using an On Insulator technology and a manufacturing method thereof. In particular, a non-volatile memory, particularly an EEPROM (Electrically Erasable), integrally formed on a substrate having an insulating surface together with peripheral circuits such as a driving circuit thereof.
rasable and Programmable Read Only Memory). In addition, the present invention relates to a semiconductor device including a nonvolatile memory integrally formed on a substrate having an insulating surface together with an arbitrary circuit including a thin film transistor (TFT).

[0002] In this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics. For example, an electro-optical device represented by a liquid crystal display device and an EL display device, and an electro-optical device mounted thereon. Electronic equipment in its category.

[0003]

2. Description of the Related Art In recent years, semiconductor devices have rapidly become multifunctional, highly functional, and miniaturized, and accordingly, the frequency of use of memories in various semiconductor devices has been increasing.
Against the background of such demand, high performance, high storage capacity, high reliability, and a small memory have been demanded.

At present, a semiconductor nonvolatile memory made of a magnetic disk or bulk silicon is most often used as a storage device of a semiconductor device.

The magnetic disk is one of the storage devices having the largest storage capacity among the storage devices used for the semiconductor device, but has a drawback that it is difficult to reduce the size and the writing / reading speed is slow.

On the other hand, a semiconductor nonvolatile memory is inferior to a magnetic disk in terms of current storage capacity, but its writing / reading speed is several tens of times that of a magnetic disk. In addition, a semiconductor nonvolatile memory having a sufficient performance with respect to the number of times of rewriting and the data retention time has been developed. Against this background, there has recently been an increasing trend to use semiconductor memories as substitutes for magnetic disks.

[0007]

A conventional semiconductor non-volatile memory is manufactured using bulk silicon and housed in a package. Therefore, when such a semiconductor non-volatile memory is mounted on a semiconductor device, a process is required. In addition, the package size has been increasing, which has hindered miniaturization of semiconductor devices.

The present invention has been made in view of the above circumstances, and can be formed integrally with components of another semiconductor device.
It is an object to provide a nonvolatile memory which can be reduced in size. Another object is to provide a semiconductor device including a nonvolatile memory which can be reduced in size.

[0009]

As a means for solving the above-mentioned problems, the present invention provides a nonvolatile memory using an SOI.
(Silicon On Insulator) is formed using a thin film transistor (TFT) formed using the technology.

According to the present invention, the nonvolatile memory can be integrally formed on an insulating substrate together with an arbitrary circuit constituted by a thin film transistor (TFT). In particular, by integrally forming a memory cell, its driving circuit (typically, an address decoder), and other peripheral circuits on an insulating substrate, a nonvolatile memory that can be reduced in size can be provided. . Still further, by being integrally formed on an insulating substrate together with an arbitrary circuit including a TFT which constitutes another semiconductor device, it is possible to provide a semiconductor device including a nonvolatile memory which can be reduced in size. Becomes

More specifically, the nonvolatile memory of the present invention has a memory cell array in which memory cells are arranged in a matrix, and each memory cell includes a memory TFT and a switching TFT. Further, a driving circuit of the memory cell and other peripheral circuits may be included.

In the present invention, the semiconductor active layers of the memory TFT and the switching TFT constituting each memory cell are continuously connected. In other words, the memory TFT and the switching TFT of each memory cell are formed on the same semiconductor active layer. With such a structure, the memory cell area can be reduced as compared with the case where the memory TFT and the switching TFT forming each memory cell are formed on different semiconductor active layers.

The semiconductor active layer of the memory TFT is thinner than the semiconductor active layer of the switching TFT, or has a thickness of 1 to 100 nm (preferably 1 to 50 nm, more preferably 10 to 40 nm). It is formed. By forming the semiconductor active layer of the memory TFT thin in this manner, writing can be performed more efficiently than when the film thickness is large. This also means that writing can be performed with a lower driving voltage, and at the same time, the structure can withstand a larger number of rewrites.

Further, in the manufacturing process of the non-volatile memory of the present invention, a step of forming a first amorphous semiconductor layer and a second amorphous semiconductor layer on an insulating substrate; Crystallizing the crystalline semiconductor layer to form a crystalline semiconductor layer including a region having a first thickness and a region having a second thickness.

In the thus formed crystalline semiconductor layer, a memory TFT having a region having a first thickness as a semiconductor active layer is formed, and a region having a second thickness as a semiconductor active layer. By forming the switching TFT, a nonvolatile memory having a memory cell in which the memory TFT and the semiconductor active layer of the switching TFT are continuously connected can be manufactured. Further, the first film thickness is smaller than the second film thickness, or the first film thickness is 1 to 1
00 nm (preferably 1 to 50 nm, more preferably 10 to
40 nm), the nonvolatile memory of the present invention can be manufactured.

The configuration of the present invention will be described below.

A non-volatile memory including at least a memory cell array in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, wherein the memory TFT includes a first semiconductor active layer formed on an insulating substrate. A switching layer, a first insulating film, a floating gate electrode, a second insulating film, and a control gate electrode, wherein the switching TFT is a second semiconductor formed on the insulating substrate. An active layer, a gate insulating film, and a gate electrode,
The memory TFT and the switching TFT are integrally formed on the insulating substrate, and the first semiconductor active layer and the second semiconductor active layer are continuously connected to each other, and the first semiconductor active layer is connected to the first semiconductor active layer. A nonvolatile memory is provided, wherein the thickness of the layer is smaller than the thickness of the second semiconductor active layer.

The thickness of the first and second semiconductor active layers is preferably 1 to 150 nm.

A nonvolatile memory in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, wherein the memory TFT includes a first semiconductor active layer formed on an insulating substrate; At least an insulating film, a floating gate electrode, a second insulating film, and a control gate electrode, wherein the switching TFT comprises a second semiconductor active layer formed on the insulating substrate; At least a film and a gate electrode, wherein the memory TFT and the switching TFT are integrally formed on the insulating substrate,
And the second semiconductor active layer are continuously connected, and the thickness of the first semiconductor active layer is:
1 to 100 nm; and the thickness of the second semiconductor active layer is 1 to 150 nm.

The thickness of the first semiconductor active layer is 1 to 50.
nm, and the thickness of the second semiconductor active layer is 10 to 10 nm.
Preferably, it is 0 nm.

The thickness of the first semiconductor active layer is 10 to 4
More preferably, it is 0 nm.

It is preferable that the first semiconductor active layer has a thickness in which impact ionization is more likely to occur than the second semiconductor active layer.

The first tunnel current flowing between the floating gate electrode of the memory TFT and the first semiconductor active layer is applied to the gate electrode of the switching TFT and the second tunnel current.
Of the second tunnel current flowing between the semiconductor
It is preferably at least two times.

The memory TFT and the switching T
The FT is preferably a p-channel TFT.

[0025] A nonvolatile memory is provided, comprising at least a memory cell drive circuit, wherein the memory cell array and the memory cell drive circuit are formed integrally on the insulating substrate.

A semiconductor comprising at least a pixel circuit in which a plurality of pixel TFTs are arranged in a matrix on an insulating substrate, a driving circuit including TFTs for driving the plurality of pixel TFTs, and the nonvolatile memory The device, wherein the pixel circuit, the drive circuit, and the nonvolatile memory,
A semiconductor device integrally formed on the insulating substrate is provided.

As the semiconductor device, a liquid crystal display device or an EL (electroluminescence) display device is provided. An EL display device is also called a light-emitting device or a light-emitting diode. Further, the EL device in this specification includes a triplet and a singlet light emitting device.

As the semiconductor device, a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, a car audio and the like are provided.

A method of manufacturing a nonvolatile memory including at least a memory cell array in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, comprising: a first amorphous semiconductor layer on an insulating substrate; Forming a second amorphous semiconductor layer, crystallizing the first amorphous semiconductor layer and the second amorphous semiconductor layer, and forming a region having a first thickness. Forming a crystalline semiconductor layer comprising a region having a second thickness; and forming a memory TFT in the crystalline semiconductor layer, wherein the region having the first thickness is a first semiconductor active layer. Forming a switching TFT using the region having the second film thickness as a second semiconductor active layer, wherein the first film thickness is ,
A method for manufacturing a nonvolatile memory, which is thinner than the second film thickness, is provided.

In the method for manufacturing a nonvolatile memory,
The first and second film thicknesses are preferably 1 to 150 nm.

A method for manufacturing a nonvolatile memory including at least a memory cell array in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, comprising: a first amorphous semiconductor layer on an insulating substrate; Forming a second amorphous semiconductor layer, crystallizing the first amorphous semiconductor layer and the second amorphous semiconductor layer, and forming a region having a first thickness. Forming a crystalline semiconductor layer comprising a region having a second thickness; and forming a memory TFT in the crystalline semiconductor layer, wherein the region having the first thickness is a first semiconductor active layer. Forming a switching TFT using the region having the second film thickness as a second semiconductor active layer, wherein the first film thickness is ,
1 to 100 nm, and the second film thickness is 1 to 150 nm
A method for fabricating a nonvolatile memory is provided.

In the method for manufacturing a nonvolatile memory,
It is preferable that the first film thickness is 1 to 50 nm and the second film thickness is 10 to 100 nm.

In the method for manufacturing a nonvolatile memory,
More preferably, the first film thickness is 10 to 40 nm.

In the method for manufacturing a nonvolatile memory,
It is preferable that the first semiconductor active layer has a thickness more likely to cause impact ionization than the second semiconductor active layer.

In the method of manufacturing a nonvolatile memory,
The first tunnel current flowing between the floating gate electrode of the memory TFT and the first semiconductor active layer is the second tunnel current flowing between the gate electrode of the switching TFT and the second semiconductor active layer. It is preferably at least two times.

In the method for manufacturing a nonvolatile memory,
Preferably, the memory TFT and the switching TFT are p-channel TFTs.

A method for manufacturing a nonvolatile memory is provided, comprising at least a memory cell drive circuit, wherein the memory cell array and the memory cell drive circuit are integrally formed on the insulating substrate. You.

A method for manufacturing a semiconductor device using the method for manufacturing a nonvolatile memory, wherein the semiconductor device is manufactured by a pixel portion, a driving circuit for driving the pixel portion, and the method for manufacturing the nonvolatile memory. Wherein the pixel portion, the driving circuit, and the non-volatile memory are integrally formed over an insulating substrate.

As a method for manufacturing the semiconductor device, a method for manufacturing a liquid crystal display device or an EL display device is provided.

As a method for manufacturing the semiconductor device, a display, a video camera, a head-mounted display,
A method for manufacturing a DVD player, a goggle type display, a personal computer, a mobile phone, a car audio, and the like is provided.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit diagram of a nonvolatile memory according to the present invention and a method for driving the same will be described below for the case of m × n bits. The top structure and the cross-sectional structure of a memory cell included in a nonvolatile memory will also be described with examples.

The method of manufacturing the nonvolatile memory according to the present invention will be briefly described. Note that the manufacturing method will be described in detail in Examples 1 and 2.

The non-volatile memory according to the present embodiment is insulated together with its driving circuit (in this embodiment, an address decoder) and other peripheral circuits, and in some cases, with other components of the semiconductor device. It is integrally formed on a substrate. Further, in the present embodiment, in particular, an EEPROM (Electrically Erasable and
Programmable Read Only Memory) will be described.

FIG. 1 is a circuit diagram of an m × n-bit nonvolatile memory according to the present invention. In the present embodiment, m
The × n-bit nonvolatile memory includes a plurality of electrically erasable memory TFTs (memory elements, storage elements) Tr 1, a plurality of switching TFTs Tr 2, and an X address decoder 10.
1, Y address decoder 102, and other peripheral circuits 1
03 and 104. Other peripheral circuits include
An address buffer circuit, a control logic circuit, and the like are included and provided as needed. Memory TFTTr
Reference numeral 1 denotes a TFT having a floating gate,
Bit data is recorded. Further, in the present invention, the memory TFT Tr1 and the switching TFT Tr2 need to be the same conductivity type TFT. In addition,
The memory TFT Tr1 and the switching TFT Tr2 may be either n-channel or p-channel TFTs, but are preferably p-channel TFTs.

The source electrode of the memory TFT Tr1 and the drain electrode of the switching TFT Tr2 are electrically connected to each other.
A bit memory cell is configured. In the present embodiment,
The memory cells are arranged in a matrix of m × n rows (m and n are each an integer of 1 or more). Since each memory cell can store one bit of information,
The nonvolatile memory according to the present embodiment has a storage capacity of m × n bits.

As shown in FIG. 1, each of the memory cells constituting the m × n-bit nonvolatile memory includes (1, 1),
Symbols (2, 1) to (n, m) are assigned.
The memory cells arranged in each column are A1, B
Both ends are connected to signal lines labeled 1 to An and Bn, and signal lines C1, D1 to Cm, and Dm are connected to memory cells arranged in each row. Specifically, the signal line Ai is connected to the drain electrode of the memory TFT Tr1 included in each of the memory cells (i, 1), (i, 2) to (i, m) arranged in the i-th column, and the switching is performed. The signal line Bi is connected to the source electrode of the TFT (i is an integer of 1 or more and n or less). Also, the memory cells (1, j), (2,
The signal line Cj is connected to the control gate electrode of the memory TFT Tr1 included in j) to (n, j), and the signal line Dj is connected to the gate electrode of the switching TFT Tr2 (j is an integer of 1 to m).

The signal lines A1, B1 to An, Bn and C1, D1 to Cm, Dm are connected to an X address decoder 101 and a Y address decoder 102, respectively. A specific memory cell is designated by the X address decoder 101 and the Y address decoder 102, and data writing, reading, and erasing are performed.

Here, the operation of the nonvolatile memory according to the present embodiment will be described using the memory cell (1, 1) in FIG. 1 as an example.

First, when writing data to the memory TFT Tr1, the switching TFT is connected via the signal line D1.
Turn Tr2 on. Further, an appropriate potential difference is applied between the drain electrode of the memory TFT Tr1 and the source electrode of the switching TFT Tr2 via the signal lines A1 and B1. Then, the memory TFT Tr1 is connected via the signal line C1.
When a high positive voltage (for example, 20 V) is applied to the control gate, carriers (in this case, holes) moving in the channel forming region of the memory TFT Tr1 are accelerated, weak avalanche decay or impact ionization occurs, and a large number of electrons in a high energy state occur. (Hot electrons) are generated. Then, the hot electrons cross the energy barrier of the gate insulating film and are injected into the floating gate electrode. In this manner, charges are accumulated in the floating gate electrode, and writing is performed. Memory T
The threshold voltage of FTTr1 changes depending on the amount of charge stored in the floating gate electrode.

When reading data from a memory cell,
For example, the switching TFT Tr2 is connected via the signal line D1.
Is turned on, and the memory TFT TTT is connected via the signal line C1.
When 0 V is applied to the control gate of r1, the signal line B1
The source of the switching TFT Tr2 may be connected to GND via the switch. As a result, the conduction or non-conduction of the memory TFT Tr1 is determined according to the electric charge accumulated in the floating gate electrode of the memory TFT Tr1, and data stored in the memory cell is read from the signal line A1.

Next, when erasing the data stored in the memory TFT Tr1, the switching TFT Tr2 is turned on via the signal line D1, and the source electrode of the switching TFT TR1 is connected to GND via the signal line B1. Then, a negative high voltage (for example, -20
When V) is applied, electrons trapped in the floating gate electrode are emitted to the drain region by a tunnel current. As a result, the stored data is erased.

Table 1 shows specific examples of the voltages applied to the signal lines A1, B1, C1, and D1 based on the above-described operation. Note that the memory TFT Tr1 and the switching TF
It is assumed that TTr2 is a p-channel TFT.

[0053]

[Table 1]

The voltages applied to the signal lines shown in Table 1 are examples, and are not limited to the values in Table 1. For example, the voltage applied to the memory TFT depends on the thickness of the semiconductor active layer of the memory TFT, the capacitance between the control gate electrode and the floating gate electrode, and the like. And the operating voltage of the memory TFT also changes accordingly.

The memory TFT Tr1 and the switching TFT Tr2 may be n-channel TFTs. In that case, for example, the voltages applied to the signal line D1 are all +
The voltage may be set to 5V. Note that when an n-channel TFT is used as a memory TFT, a larger current flows at the time of writing than in the case where a p-channel TFT is used, and deterioration may be faster. Therefore, in the present embodiment, it is preferable that the memory TFT Tr1 be a p-channel type.

In the present embodiment, the memory TF
When writing / erasing T, a voltage lower than + 20 / -20V may be applied to the control gate electrode of the memory TFT at one time, but a voltage lower than this may be applied by a plurality of pulses. In this case, deterioration of the TFT can be suppressed to some extent.

Next, the top structure and the sectional structure of the memory cell constituting the nonvolatile memory of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

First, an example of a top view of a memory cell constituting the nonvolatile memory of the present invention is shown. FIG. 7 shows four memory cells (1, 1), (1, 2), (2, 1),
A top view of a region including (2, 2) (see FIG. 1) is shown.

In FIG. 7, regions 701 to 704 are semiconductor active layers, and the memory TFT Tr1 and the switching TFT Tr2 are formed on the same semiconductor active layer. Among the first wiring layers 711 to 714, the wiring 713,
Reference numeral 714 is used as the gate electrode of the switching TFT Tr2 and the signal lines C1 and C2.
Reference numeral 12 is used as signal lines D1 and D2. The floating gate electrode 715 of the memory TFT Tr1
718 is formed simultaneously with the first wiring layers 711 to 714. Among the second wiring layers 731 to 738, the wiring 73
Reference numerals 1 and 732 are used as signal lines A1 and A2 connected to the source region of the memory TFT Tr1.
Reference numeral 734 is used as signal lines B1 and B2 connected to the drain region of the switching TFT Tr2. The wires 735 to 738 are used as wires for connecting the control gate electrodes 721 to 724 of the memory TFT Tr1 and the signal lines D1 and D2. Further, in the drawing, a black portion indicates that a contact is made with a wiring or a semiconductor layer therebelow. Note that, in the drawing, all wirings of the same pattern are the same wiring layer.

Next, a sectional view of a memory cell constituting the nonvolatile memory of the present invention is shown. FIG. 2 illustrates a cross-sectional structure of the memory cell illustrated in FIG. 7 (for example, a cross-sectional structure taken along the line AA ′ in the memory cell (1, 2)).

In FIG. 2, the left TFT is the memory TF
TTr1 and the TFT on the right is a switching TFT T
r2. Memory TFT Tr1 and switching T
The semiconductor active layer forming FTTr2 includes source / drain regions 201, 202, 203 and channel formation regions 204, 205. Insulating films 206, 210 and 2
07 is a first gate insulating film of the memory TFT,
A second gate insulating film and a gate insulating film of the switching TFT, and electrodes 208, 211 and 209 are a floating gate electrode, a control gate electrode of the memory TFT and a gate electrode of the switching TFT, respectively. The insulating film 212 is an interlayer insulating film, and
13, 214 and 215 are memory TFTTs, respectively.
The drain wiring of r1, the source wiring of the switching TFT Tr2, and the control gate wiring of the memory TFT Tr1.

As shown in FIG. 2 (and FIG. 7), in the present invention, the semiconductor active layer of the memory TFT Tr1 and the semiconductor active layer of the switching TFT Tr2 are directly connected. In other words, the source region of the memory TFT Tr1 and the drain region of the switching TFT Tr2 are electrically connected by sharing a semiconductor active layer.
With such a structure, the area of the memory cell can be significantly reduced as compared with a case where the memory TFT Tr1 and the switching TFT Tr2 are formed on different semiconductor active layers. A semiconductor device having a nonvolatile memory can be reduced in size.

As shown in FIG. 2, the memory TFT Tr
The semiconductor active layer 1 (thickness d1) is a switching TFT
It is formed thinner than the semiconductor active layer (thickness d2) of Tr2. That is, d1 <d2 holds. With such a structure, impact ionization (impact ionization, impact ionization, or impact ionization) is more likely to occur in the semiconductor active layer of the memory TFT Tr1, and as a result, charges to the floating gate electrode of the memory TFT Tr1 are transferred. The injection is more likely to occur. It should be noted that the X address decoder 101, the Y address decoder 102, and TFTs forming other peripheral circuits
May be the same as the thickness d2 of the switching TFT Tr2.

The source region 2 of the memory TFT Tr1
02 and the floating gate region 208 partially overlap with the gate insulating film 206 interposed therebetween, and a tunnel current at the time of erasure is secured. The tunnel current flowing in the semiconductor active layer of the memory TFT Tr1 is preferably at least twice the tunnel current flowing in the semiconductor active layer of the switching TFT Tr2.

For an example of the cross-sectional structure of the memory cell, Embodiment 2 can be referred to in addition to this embodiment. As described above, in the present invention, the semiconductor active layer of the memory TFT Tr1 is thinner than the semiconductor active layers of the TFTs and the switching TFTs constituting the address decoder and other peripheral circuits, or has a thickness of 1 to 100 nm (preferably 1 to 100 nm). To 50 nm, more preferably 10 to 40 nm).

In a nonvolatile memory, the number of rewritable times and the information holding time are important. In order to improve the number of rewritable times, it is required to reduce the voltage applied to the control gate electrode of the memory TFT.
In the nonvolatile memory of the present invention, as described above, since the semiconductor active layer of the memory TFT is formed thin, impact ionization easily occurs, and writing and erasing of the memory TFT can be performed at a low voltage. This is because in a conventional nonvolatile memory made of bulk silicon, the gate insulating film has been relatively deteriorated because the gate insulating film is relatively thin, or the carriers accumulated in the floating gate electrode have a high temperature. Spilled by rising,
Is an innovative solution to

Next, a brief description will be given of a method of manufacturing the nonvolatile memory of the present invention. Note that Embodiments 1 and 2 can be referred to for a detailed manufacturing method.

First, after forming and patterning a first amorphous semiconductor layer on an insulating substrate, a second amorphous semiconductor layer is formed. Then, the two amorphous semiconductor layers are crystallized to form a crystalline semiconductor layer including a region having a first thickness and a region having a second thickness. In the case where a driver circuit of a memory cell and other peripheral circuits are formed over an insulating substrate, a crystalline semiconductor layer having a second thickness is formed in that region.

In this specification, the term “amorphous semiconductor film” refers to an entire semiconductor film having an amorphous structure, and includes a so-called amorphous semiconductor film and a microcrystalline semiconductor film. Further, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.

In this specification, a crystalline semiconductor layer refers to the entire semiconductor layer including a crystal structure, and includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film. In addition, a polycrystalline semiconductor film having particularly excellent crystallinity is disclosed in
No. 7,735, a semiconductor film having a crystal structure in which rod-shaped crystals are gathered and arranged (Example 1).
Reference).

Thereafter, a memory TFT having a region having a first thickness as a semiconductor active layer and a switching TFT having a region having a second thickness as a semiconductor active layer are formed. Having a memory cell in which the semiconductor active layers are continuously connected,
A non-volatile memory can be manufactured. Further, by simultaneously forming a CMOS circuit using a crystalline semiconductor layer having a second thickness as a semiconductor active layer, a drive circuit of a memory cell and other peripheral circuits can be formed integrally.

Of course, the first film thickness and the second film thickness
It can be set freely within the range of the device,
By forming the first film thickness smaller than the second film thickness or forming the first film thickness to be 1 to 100 nm (preferably 1 to 50 nm, more preferably 10 to 40 nm),
The non-volatile memory of the present invention can be manufactured.

By the above-described method for manufacturing a nonvolatile memory, the nonvolatile memory of the present invention can be formed integrally with any semiconductor device component that can be manufactured using thin film technology.

When the manufacturing method shown in Embodiment 1 is used, a TFT having high characteristics can be manufactured.
As a result, various types of nonvolatile memories and semiconductor devices having nonvolatile memories can be integrated with peripheral circuits and semiconductor device components that require TFTs exhibiting high characteristics in mobility, threshold voltage, and the like. Can be realized.

[0075]

(Embodiment 1) In this embodiment, a method for manufacturing a nonvolatile memory using the present invention will be described with reference to FIGS. FIGS. 3 to 6 show, as TFTs constituting the nonvolatile memory of this embodiment, memory TFTs (p-channel TFTs) and switching TFTs (p-channel TFTs) constituting memory cells, an address decoder, and the like. Two TFTs (p-channel type TFTs) constituting a typical CMOS circuit as circuits constituting other peripheral circuits
FT and n-channel TFT) will be described as an example.

According to the method for manufacturing a nonvolatile memory described below, it is understood that the nonvolatile memory of the present invention can be integrally formed with any semiconductor device component that can be manufactured by using a thin film technique.

In order to realize a non-volatile memory and a semiconductor device having a memory cell, an address decoder and a circuit composed of other TFTs on the same insulating substrate, high characteristics such as mobility and threshold voltage are required. Is required. In particular, a TFT having a semiconductor active layer of amorphous silicon, which is often used in the past, is not enough. According to the following manufacturing method, a TFT having high characteristics can be manufactured, and the nonvolatile memory and the semiconductor device of the present invention can be realized.

Referring to FIG. First, a quartz substrate 301 is prepared as a substrate having an insulating surface. A silicon substrate on which a thermal oxide film is formed can be used instead of the quartz substrate. Also, once an amorphous silicon film is formed on a quartz substrate,
A method of completely thermally oxidizing it to form an insulating film may be used. Further, a quartz substrate or a ceramic substrate on which a silicon nitride film is formed as an insulating film may be used.

Next, an amorphous silicon film 302 having a thickness of 25 nm is formed by a known film forming method (FIG. 3A). Note that the present invention is not limited to an amorphous silicon film, and may be any amorphous semiconductor film (including a compound semiconductor film including an amorphous structure such as a microcrystalline semiconductor film and an amorphous silicon germanium film). .

Next, a mask 311 is formed by forming a resist film and patterning it.
(B)). After that, the amorphous silicon film 302 is etched to form an amorphous silicon film 321 partially formed over the substrate (FIG. 3C). Note that the amorphous silicon film 321 may be etched by either dry etching or wet etching. In the case of dry etching, for example, CF ₄ + O ₂ may be used, and in the case of wet etching, an etching solution such as fluoric acid + nitric acid may be used.

Next, an amorphous silicon film is formed to a thickness of 50 nm again by the method described above, and amorphous silicon films 331 and 332 are formed as shown in FIG. Here, the final film thickness was adjusted so that the amorphous silicon film 331 would be 50 nm and the amorphous silicon film 332 would be 75 nm. Note that, here, it is not necessary to limit to an amorphous silicon film. Any amorphous semiconductor film (including a microcrystalline semiconductor film and a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film) is used. Good.

It is desirable that the surface of the amorphous silicon film 321 and the surface of the quartz substrate 301 be cleaned before the second formation of the amorphous silicon film.

In forming the amorphous silicon films 331 and 332, another method may be used. For example, an amorphous silicon film having a thickness of 75 nm can be entirely formed by the above-described method, a mask can be partially formed, and an amorphous silicon film having a partially reduced thickness can be obtained by the above-described etching. .

The amorphous silicon film 331 will later become a semiconductor active layer of the memory TFT, and the amorphous silicon film 332 will
Later, it becomes a semiconductor active layer such as a switching TFT and a peripheral CMOS circuit.

The final thickness of the semiconductor active layer is 15
In the case of 0 nm or more, particularly 200 nm or more, impact ionization peculiar to SOI is extremely small, and is almost the same as the case of non-volatile memory using bulk silicon. Therefore, the characteristics of the nonvolatile memory based on the SOI technology cannot be brought out. For this reason,
In the present invention, the thickness of the final semiconductor active layer is preferably 1 to 150 nm.

In this embodiment, as described above, the final thickness of the amorphous silicon film 331 of the memory TFT is set to 50n.
m, the final film thickness of the amorphous silicon film 332 of the switching TFT and the peripheral CMOS circuit is set to 75 nm,
The thickness may be in the range of 1 to 100 nm (preferably 1 to 50 nm, more preferably 10 to 40 nm) and 1 to 150 nm (preferably 10 to 100 nm), and is not limited to the film thickness in this embodiment. .

Next, a crystallization step of the amorphous silicon films 331 and 332 is performed. The steps from here to FIG. 4 (B) can completely refer to JP-A-10-247735 by the present applicant. This publication discloses a technique relating to a method for crystallizing a semiconductor film using an element such as Ni as a catalyst.

First, protective films 400 to 402 having openings 404 and 405 are formed. In this embodiment, a silicon oxide film having a thickness of 150 nm is used. Then, the protective films 400 to 402
A layer (Ni-containing layer) 403 containing nickel (Ni) is formed thereon by spin coating. Regarding the formation of the Ni-containing layer, the above publication may be referred to (FIG. 4).
(A)).

In addition to nickel, cobalt (Co), iron (Fe), palladium (P
d), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb), indium (In), or the like can be used.

The step of adding the catalyst element is not limited to the spin coating method, but may be an ion implantation method using a resist mask, a plasma doping method, or a sputtering method. In this case, the reduction of the occupied area of the addition region and the control of the crystal growth distance are facilitated, and this is an effective technique for forming a miniaturized circuit.

Next, as shown in FIG. 4B, heat treatment is performed at 570 ° C. for 14 hours in an inert atmosphere to crystallize the amorphous silicon films 331 and 332. At this time, regions in contact with Ni (hereinafter, referred to as Ni added regions) 411 and 41
Crystallization proceeds in a direction substantially parallel to the substrate starting from 2, and a crystalline silicon film 4 having a crystal structure in which rod-like crystals are gathered and arranged.
13 are formed. The crystalline silicon film 413 has an advantage of excellent overall crystallinity since individual crystals are aggregated in a relatively uniform state. The heat treatment temperature is
Preferably 500 to 700 ° C (typically 550 to 65 ° C)
0 ° C.), and the treatment time is preferably 4 to 24 hours.

Next, as shown in FIG.
Elements belonging to Group 15 (preferably phosphorus) are added to the Ni-added regions 411 and 412 using 00 to 402 as a mask. Thus, regions 421 and 422 to which phosphorus is added at a high concentration (hereinafter, referred to as phosphorus added regions) are formed.

Next, as shown in FIG. 4C, heat treatment is performed at 600 ° C. for 12 hours in an inert atmosphere. As a result of this heat treatment, Ni existing in the crystalline silicon film 423 moves, and finally, almost all of the Ni is captured in the phosphorus-added regions 421 and 422 as indicated by arrows. This is considered to be a phenomenon due to the gettering effect of the metal element (Ni in this embodiment) by phosphorus.

By this step, the concentration of Ni remaining in the crystalline silicon film 423 is reduced to at least 2 × 10 ¹⁷ atoms / cm ³ as measured by SIMS (mass secondary ion analysis). Ni is a lifetime killer for semiconductors, but if it is reduced to this extent, there is no adverse effect on TFT characteristics. In addition, this concentration is almost
Since it is the measurement limit of the IMS analysis, it is considered that the concentration is actually lower (2 × 10 ¹⁷ atoms / cm ³ or less).

Thus, it is crystallized using a catalyst, and
A crystalline silicon film 423 whose catalyst is reduced to a level that does not interfere with the operation of the TFT is obtained. After that, the protective films 400 to 402 are removed, and the phosphorus added regions 421 and 4
The island-shaped semiconductor layers (active layers) 431 to 433 using only the crystalline silicon film 423 that do not include 22 are formed by a patterning process. At this time, the island-shaped semiconductor active layer 431 includes two active regions having different thicknesses obtained by crystallizing the amorphous silicon films 331 and 332 (FIG. 4).
(D)). The thin active region obtained by crystallizing the amorphous silicon film 331 in the island-shaped semiconductor active layer 431 is
The amorphous silicon film 33 becomes the semiconductor active layer of the memory TFT.
The thick active region obtained by crystallizing 2 becomes a semiconductor active layer of the switching TFT.

Next, in the island-shaped semiconductor active layer 431, a region other than the region 503 which will be a source region of the memory TFT later is covered with a resist mask, and an impurity element imparting p-type (also referred to as a p-type impurity element) is added. (FIG. 5A). In this embodiment, boron (B) is used as an impurity element, and the accelerating voltage at the time of adding the impurity is about 10 keV. In the p-type impurity region 503 formed by this step, the p-type impurity element is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically, 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm ^3). The dose is adjusted so as to be included in the concentration of ()). As the p-type impurity element, gallium (Ga), indium (In), or the like may be used in addition to boron (B). Note that the p-type impurity region 503 formed in this step may be formed so as to have a region overlapping with a part of a floating gate electrode of a memory TFT to be formed later via a gate insulating film. Therefore, the region covered with the resist mask is not limited to the present embodiment (FIG. 5A), and at least one of the island-shaped semiconductor active layers 431 and a channel forming region of a memory TFT and a switching TFT later. Region and island-shaped semiconductor active layers 432, 433
Should be included.

As a result, a region 503 to be a source region of the memory TFT later in the island-shaped semiconductor active layer 431 is formed. Since the remaining region of the island-shaped semiconductor active layer 431 and the island-shaped semiconductor active layers 432 and 433 are covered with the resist masks 501 and 502, no impurity is added.

After that, the resist masks 501 and 502 are removed, and a gate insulating film 511 made of an insulating film containing silicon is formed (FIG. 5B). The thickness of the gate insulating film 511 is 10 to 250 nm in consideration of an increase due to a subsequent thermal oxidation step.
It can be adjusted within the range. Note that the thickness of the gate insulating film of the island-shaped semiconductor active layer of the memory TFT is set to 10 to 50 nm,
Another gate insulating film may have a thickness of 50 to 250 nm. Further, a film forming method is a known gas phase method (plasma CVD).
Method, sputtering method, or the like). In this embodiment, 5
A silicon nitride oxide film having a thickness of 0 nm is formed by a plasma CVD method.

Next, a heat treatment is performed in an oxidizing atmosphere at 950 ° C. for one hour to perform a thermal oxidation step. Note that the oxidation atmosphere may be an oxygen atmosphere or an oxygen atmosphere to which a halogen element is added. In this thermal oxidation step, oxidation proceeds at the interface between the active layer and the silicon nitride oxide film, and the thickness of the gate insulating film 511 increases by the amount of the thermal oxide film. When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Further, there is also an effect of preventing formation failure (edge thinning) of a thermal oxide film at an end of the active layer.

Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 521 to 524 (FIG. 5C). The gate electrodes 521 to 524
Determines the channel length of the two TFTs and the switching TFT that constitute the CMOS circuit. At this time, the gate electrode 521 of the memory TFT (to be a floating gate electrode later) is formed so as to partially overlap the p-type impurity region 503 with the gate insulating film 511 interposed therebetween. This overlapping region is a region for sufficiently securing a tunnel current flowing when the memory TFT performs erasing.

Note that the gate electrode may be formed of a single-layer conductive film, but it is preferable to form a two-layer or three-layer laminated film as necessary. A known conductive film can be used as a material for the gate electrode. Specifically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a nitride of the element (Typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film combining the above elements (typically, a Mo—W alloy, a Mo—Ta alloy), or a silicide film of the above element (Typically, a tungsten silicide film or a titanium silicide film) can be used.

In this embodiment, a laminated film composed of a 50 nm thick tungsten nitride (WN) film and a 350 nm thick tungsten (W) film is used. This may be formed by a sputtering method. Further, when an inert gas such as xenon (Xe) or neon (Ne) is added as a sputtering gas, peeling of the film due to stress can be prevented.

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, phosphorus (P) or arsenic (As) for n-type, boron (B) for p-type,
Gallium (Ga) or indium (In) may be used.

First, as shown in FIG. 5D, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate electrodes 521 to 524 as a mask to form a low concentration impurity region (n− ) Is formed. This low concentration impurity region
Phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ³ to 1 × 10 ¹⁹ atoms / c
Adjust to ³ m. The acceleration voltage may be set to about 80 keV.

Next, the gate insulating film 511 is etched by a dry etching method using the gate electrodes 521 to 524 as a mask, and is patterned into 601 to 604 (FIG. 6).
(A)).

Next, as shown in FIG. 6A, resist masks 605 and 606 are formed so as to cover the entire p-channel TFT and a part of the n-channel TFT, and add an n-type impurity element. Region 6 containing phosphorus at a high concentration
07 and 608 are formed. At this time, the concentration of the n-type impurity element is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ²¹ atoms / cm ³ ).
It is adjusted so as to be in the range of × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm ³ ). In this embodiment, phosphorus (P) is used as an impurity element, and the accelerating voltage at the time of adding the impurity is about 10 keV.

In this step, source / drain regions 607 and 608 of the n-channel TFT are formed. In particular, in the n-channel TFT, part of the low-concentration impurity region (n − region) 536 formed in the step of FIG.
This remaining region becomes the LDD region of the n-channel TFT. Accordingly, source / drain regions 607 and 608 of the n-channel TFT, an LDD region 609, and a channel formation region 610 are formed.

Next, as shown in FIG. 6B, the resist masks 605 and 606 are removed, and a new resist mask 617 is formed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 611 to 615 containing boron at a high concentration. Here, diborane (B ₂
1 × 10 ²⁰ to 1 × by ion doping using H ₆ )
10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ a
Add boron to a concentration of toms / cm ³ ).

In this manner, source / drain regions 611 to 616 (including a floating gate electrode and a source region partially overlapping via a gate insulating film) of a p-channel TFT and channel forming regions 618 to 620 are formed (FIG. 10). 6 (B)).

Next, as shown in FIG. 6C, after removing the resist mask 617, an insulating film 621 containing silicon is formed (FIG. 6C). This insulating film 621 becomes a gate insulating film between the floating gate electrode and the control gate electrode in the memory TFT. Insulating film 62
The thickness of 1 may be 10 to 250 nm. In addition, a film forming method is a known gas phase method (plasma CVD method, sputtering method, etc.)
May be used. Note that in this embodiment, a silicon nitride oxide film having a thickness of 50 nm is formed by a plasma CVD method.

Thereafter, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, lamp annealing, and the like may be combined. In this embodiment, heat treatment is performed in an electric furnace at 550 ° C. for 4 hours in a nitrogen atmosphere. At this time, the damage of the active layer in the adding step is also repaired. As an activation means, a furnace annealing method is preferable.

Next, a conductive film of 200 to 400 nm is formed and patterned to form a control gate electrode 622.
Is formed (FIG. 6C). Control gate electrode 6
22 is formed so as to overlap a part or the whole of the floating gate electrode with the insulating film 621 interposed therebetween.

The control gate electrode may be formed of a single-layer conductive film, but is preferably formed as a two-layer or three-layer film as required. A known conductive film can be used as a material for the gate electrode. Specifically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a nitride of the element Film, an alloy film combining the above elements, or a silicide film of the above elements can be used.

In this embodiment, a laminated film composed of a 50 nm thick tungsten nitride (WN) film and a 350 nm thick tungsten (W) film is formed by sputtering. When an inert gas such as xenon (Xe) or neon (Ne) is added as a sputtering gas, the film can be prevented from peeling due to stress.

Next, an interlayer insulating film 631 is formed. As the interlayer insulating film 631, an insulating film containing silicon, an organic resin film, or a stacked film combined therewith may be used.
The film thickness may be 400 nm to 1.5 mm. In this embodiment, a silicon nitride oxide film having a thickness of 500 nm is used.

Next, as shown in FIG. 6D, contact holes are formed in the interlayer insulating film 631 and the insulating film 621, and source / drain wirings 632 to 636 and control gate wirings 637 are formed. In this embodiment, the wiring is a three-layer laminated film in which a Ti film, a Ti-containing aluminum film, a Ti film, and a Ti film are successively formed by a sputtering method. Of course, other conductive films may be used.

Finally, a heat treatment is performed in an atmosphere containing 3 to 100% hydrogen at 300 to 450 ° C. for 1 to 12 hours to perform a hydrogenation treatment. This step is a step of terminating dangling bonds of the semiconductor film with thermally excited hydrogen.
In this embodiment, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 2 hours to perform hydrogenation treatment. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. The hydrogenation treatment may be performed before forming the contact hole.

Through the above steps, a TFT having a structure as shown in FIG. 6D can be manufactured.

(Embodiment 2) In this embodiment, a case where a non-volatile memory is constituted by an inverted stagger type TFT will be described with reference to FIGS. 9 to 11.
The memory TFT (p-channel type TFT) and the switching TFT (p-channel type TF) forming a memory cell are used as TFTs forming the nonvolatile memory of this embodiment.
T) and a typical CMOS circuit as a circuit constituting an address decoder and other peripheral circuits 2
TFTs (p-channel TFT and n-channel TFT)
FT) will be described as an example.

Referring to FIG. First, a glass substrate 901
A base film 902 made of a silicon oxide film is provided thereon, and gate electrodes 903 to 906 are formed thereon. Gate electrode 903
Later becomes the control gate electrode of the memory TFT, and the gate electrode 904 later becomes the gate electrode of the switching TFT. In this embodiment, the gate electrodes 903-9
Although a chromium film having a thickness of 200 to 400 nm is used for 06, an aluminum alloy, tantalum, tungsten, molybdenum, a silicon film having conductivity, or the like may be used.

Next, a gate insulating film 907 having a thickness of 100 to 200 nm is formed on the gate electrodes 903 to 906.
As the gate insulating film 907, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used.

The gate insulating film on the side of the memory TFT defines the capacitance between the floating gate electrode and the control gate electrode to be formed in the next step. Can be adjusted. Therefore, the thickness of the gate insulating film 907 is not limited to the above range, and the thickness may be partially changed.

Next, a floating gate electrode 911 is formed (FIG. 9B). Although a chromium film is used as the floating gate electrode in this embodiment, an aluminum alloy, tantalum, tungsten, molybdenum, a silicon film with conductivity, or the like may be used.

Next, an insulating film 912 is formed to a thickness of 10 to 50 nm. As the insulating film 912, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used.

Next, amorphous silicon films 921 and 922 are formed by the method shown in FIGS. 3A to 3D of the first embodiment (FIG. 9C). In this embodiment, the memory TFT
The final thickness of the amorphous silicon film 921 is 50 nm, and the final thickness of the amorphous silicon film 922 of the switching TFT is 7 nm.
5 nm, each being 1 to 100 nm (preferably 1 to 100 nm)
50 nm, more preferably 10 to 40 nm), 1 to 150 nm
(Preferably 10 to 100 nm), and the film thickness is not limited to the thickness in this embodiment. Also,
The thickness of the amorphous silicon film of the TFT constituting the address decoder and the peripheral circuit is the same as that of the switching TFT.

It is not necessary to limit the invention to an amorphous silicon film, but an amorphous semiconductor film (including a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film and an amorphous silicon germanium film). I just want it.

Next, the amorphous silicon films 921 and 922 are irradiated with laser light or strong light having an intensity equivalent to the laser light to crystallize the amorphous silicon films (FIG. 9).
(D)). Excimer laser light is preferable as the laser light. Excimer lasers include KrF, Ar
A pulse laser using F, XeCl as a light source may be used.

As the intense light having the same intensity as the laser light, intense light from a halogen lamp or a metal halide lamp, or intense light from an infrared light or an ultraviolet light lamp can be used.

In this embodiment, an excimer laser beam processed linearly is scanned from one end to the other end of the substrate to crystallize the entire surface of the amorphous silicon film. At this time, the sweep speed of the laser beam is 1.2 mm / s, the processing temperature is room temperature, the pulse frequency is 30 Hz, and the laser energy is 300 to 315 mJ / cm ² . By this step, a crystalline silicon film is obtained.

Note that the crystallization method used in the first embodiment may be used as the crystallization method for the amorphous semiconductor film in the present embodiment. Conversely, the crystallization method of the present embodiment can be used as the crystallization method of the amorphous semiconductor film of the first embodiment.

Next, reference is made to FIG. First, the crystalline silicon film is patterned to form active layers 1001 to 1003 (FIG. 10A).

Next, an impurity element imparting one conductivity is added. As an impurity element, phosphorus (P) or arsenic (As) may be used for n-type, and boron (B), gallium (Ga), indium (In) or the like may be used for p-type.

First, resist masks 1011 to 1014
Is formed, and an impurity element imparting p-type conductivity (also referred to as a p-type impurity element) is added (FIG. 10B). as a result,
Source region / drain region 101 of p-channel TFT
5 to 1019 and channel forming regions 1020 to 1022
Is formed. In this embodiment, boron is used as the p-type impurity element and the boron concentration is 1 × 10 ²⁰ to 1 × 10 ^20.
21 atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atom
s / cm ³ ).

Next, the resist masks 1011 to 1014
Is removed to form resist masks 1031 and 1032. Then, an n-type impurity element (phosphorus is used in this embodiment) is added to add 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms /.
Low concentration impurity regions 1033 and 1034 of about cm ³
Is formed (FIG. 10C).

Next, the resist masks 1031 and 1031
32 are removed and the resist masks 1041 and 1042 are removed.
To form Then, the n-type impurity element is again introduced into FIG.
Higher concentration than step (C) (1 × 10 ²⁰ to 1 × 10 ²¹ at
oms / cm ³ ) to form source / drain regions 1043 and 1044 of the N-type TFT. The area 10
Reference numeral 45 denotes a low concentration impurity region, and a region 1046 denotes a channel formation region (FIG. 10D).

Next, resist masks 1041 and 10
After removing 42, irradiation with excimer laser light (laser annealing) is performed to recover damage at the time of impurity element implantation and to activate added impurities (FIG. 11).
(A)).

When the laser annealing is completed, an interlayer insulating film 1111 is formed to a thickness of 300 to 500 nm (FIG. 11).
(B)). The interlayer insulating film 1111 is formed of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, an organic resin, or a stacked film thereof.

Next, a contact hole is formed in the interlayer insulating film 1111 and the source / drain electrode 1 made of a metal thin film is formed.
112 to 1116 are formed. As this metal thin film, aluminum, tantalum, titanium, tungsten, molybdenum, or a stacked film thereof may be used (FIG. 11).
(B)).

Finally, 35% of the whole was placed in a hydrogen atmosphere.
Heat treatment is performed at 0 ° C. for about 2 hours to terminate dangling bonds in the film (particularly, a channel formation region) with hydrogen. Through the above steps, a TFT having a structure as illustrated in FIG. 11B can be manufactured.

(Embodiment 3) In the sectional view of the memory cell shown in FIG. 2, the semiconductor active layer (thickness d1) of the memory TFT is shown.
Has a structure thinner than the semiconductor active layer (thickness d2) of the switching TFT, and d1 is 1 to 100 nm (preferably 1 to 50 nm, more preferably 10 to 40 nm),
2 may be formed in the range of 1 to 150 nm (preferably 10 to 100 nm). In particular, the semiconductor active layer of the memory TFT and the semiconductor active layer of the switching TFT may have the same thickness.

The semiconductor active layer of the TFT forming the drive circuit of the memory cell and other peripheral circuits is the memory TF
Even if it is formed to have the same thickness as the semiconductor active layer of T, it may be formed thicker than the semiconductor active layer of the memory TFT as long as the driving frequency of the circuit does not decrease.

In this embodiment, the manufacturing methods of Embodiments 1 and 2 can be used. In that case, it is not necessary to form semiconductor active layers having different thicknesses, and the manufacturing process is simplified.

Embodiment 4 In this embodiment, an example different from the circuit diagram of the memory cell in the nonvolatile memory shown in FIG. 1 will be described with reference to FIG. FIG. 8 is a circuit diagram of adjacent memory cells arranged in the same row in a memory cell array in which memory cells are arranged in a matrix. In FIG. 8, two adjacent memory cells share a signal line (referred to as a signal line B) connected to the source electrode of the switching TFT.

Specifically, the signal lines A and A 'are connected to the drain electrodes of the left and right memory TFTs Tr1 and Tr1', respectively, and the signal line B is connected to the switching TFT T1.
It is connected to the source electrodes of r2 and Tr2 '. The signal line C is connected to the control gate electrodes of the memory TFTs Tr1, Tr1 ', and the signal line D is connected to the gate electrodes of the switching TFTs Tr2, Tr2'. In the two memory cells, a memory TFT and a switching TFT are provided symmetrically with respect to the signal line B.

By adopting such a structure, the number of signal lines B can be reduced as compared with the structure shown in FIG. 1, and memory cells can be arranged at higher density. As a result, the size and capacity of the nonvolatile memory can be reduced.

This embodiment can be combined with any one of Embodiments 1 to 3.

Embodiment 5 In this embodiment, an inexpensive low-grade quartz substrate is first prepared. Next, the quartz substrate is polished to an ideal state (the average value of the difference between the concave and convex portions is 5 nm or less, typically 3 nm or less, preferably 2 nm or less) by a method such as CMP (chemical mechanical polishing).

As described above, even an inexpensive quartz substrate can be used as an insulating substrate having excellent flatness by polishing. When a quartz substrate is used, the underlayer becomes very dense, so that the stability of the underlayer / semiconductor thin film interface is high. In addition, it is very useful because there is almost no influence of contamination from the substrate.

This embodiment can be combined with any of the structures of the first to fourth embodiments.

(Embodiment 6) In Embodiments 1 and 2,
The example in which an element belonging to Group 15 (phosphorus in Examples 1 and 2) is used in the step of gettering a catalyst element that promotes crystallization of silicon has been described. In the present invention, a halogen element can be used in the catalyst element gettering step.

In this embodiment, in the heat treatment after forming the gate insulating film on the semiconductor active layer (see FIG. 5A), the gettering of the catalytic element is performed by using a processing atmosphere containing a halogen element. Perform the process.

In order to sufficiently obtain the gettering effect by the halogen element, it is preferable to perform the above heat treatment at a temperature exceeding 700 ° C. Below this temperature, the decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained. Therefore, the heat treatment temperature is preferably set to 800 to 1000 ° C. (typically 950 ° C.), and the treatment time is set to 0.1 to 6 hours, typically 0.5 to 1 hour.

As a typical example, the temperature is 950 ° C. in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume (3% by volume in this embodiment) with respect to an oxygen atmosphere. For 30 minutes. HCl
If the concentration is higher than the above-mentioned concentration, unevenness having a thickness of about the thickness of the surface of the semiconductor active layer is not preferable.

The compound containing a halogen element may be H
In addition to Cl gas, HF, NF ₃ , HBr, Cl ₂ , ClF
_One or more compounds selected from compounds containing a halogen element such as ₃ , BCl ₃ , F ₂ , and Br ₂ can be used.

In this step, nickel in the semiconductor active layer is gettered by the action of chlorine, becomes volatile nickel chloride, and is released to the atmosphere and removed. By this step, the concentration of nickel in the semiconductor active layer is 5 × 10 ¹⁷ atoms / cm ³ or less (typically 2 × 10 ¹⁷ a
toms / cm ³ or less). According to the experience of the present inventors, if the nickel concentration is 1 × 10 ¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁷ atoms / cm ³ or less), T
There is no adverse effect on the FT characteristics.

The gettering process is also effective for metal elements other than nickel. As metal elements that can be mixed into the silicon film, constituent elements of the film formation chamber (typically, aluminum, iron, chromium, etc.) can be considered, but if the above gettering treatment is performed, the concentration of those metal elements can be considered. 5 × 10 ¹⁷ atoms / cm ³ or less (preferably 2 × 1
0 ¹⁷ atoms / cm ³ or less).

When the gettering process is performed, the halogen element used for the gettering process remains in the semiconductor active layer at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ .

In addition, the thermal treatment causes a thermal oxidation reaction to proceed at the interface between the semiconductor active layer and the gate insulating film, and the thickness of the gate insulating film increases by the amount of the thermal oxide film. When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Further, there is also an effect of preventing formation failure (edge thinning) of a thermal oxide film at an end of the active layer.

As described above, the catalyst element gettering step using the halogen element is performed. Note that the other steps may follow the manufacturing steps described in Embodiment 1 or 2. As a result, a nonvolatile memory having the same characteristics as those of the first or second embodiment can be obtained.

This embodiment can be combined with any of Embodiments 3 to 5.

(Embodiment 7) In this embodiment, in the manufacturing method described in Embodiment 1 or 2, tantalum (Ta) or a Ta alloy is used for the gate electrode, and the floating gate electrode and the control gate electrode of the memory TFT are used. The case where a thermal oxide film of a gate electrode made of Ta or a Ta alloy is used as the insulating film during the period will be described.

In the case of the manufacturing method described in Embodiment 1, Ta or Ta is applied to the floating gate electrode of the memory TFT.
It is preferable to use an alloy and thermally oxidize it. Example 2
In the fabrication method described in, the control gate electrode is
It is preferable to use a or Ta alloy and thermally oxidize it.

When Ta or a Ta alloy is used for the gate electrode, thermal oxidation can be performed at about 450 ° C. to about 600 ° C., and an oxide film of good quality such as Ta ₂ O ₃ is formed on the gate electrode.

The relative dielectric constant of the insulating film thus formed is, for example, about 11.6 in the case of Ta ₂ O ₃ , which is larger than that of the insulating film containing silicon. In addition, a larger capacitance is formed between the floating gate and the control gate. As a result, by using a thermal oxide film of Ta or a Ta alloy, it is possible to manufacture a nonvolatile memory having a structure in which charges are easily injected into the floating gate as compared with an insulating film containing silicon.

This embodiment can be combined with any one of Embodiments 3 to 6.

(Embodiment 8) The nonvolatile memory of the present invention has various uses. In this embodiment, an electro-optical device (typically, a liquid crystal display device and an EL display device) including the nonvolatile memory of the present invention as a memory unit will be described.

First, an example of an electro-optical device including at least the nonvolatile memory of the present invention, a pixel portion, a driving circuit for driving the pixel portion, and a γ (gamma) correction circuit will be described with reference to FIG.

The γ correction circuit is a circuit for performing γ correction. The γ correction is a correction for creating a linear relationship between the voltage applied to the pixel electrode and the transmitted light intensity of the liquid crystal or the EL layer thereon by applying an appropriate voltage to the image signal.

In this embodiment, one source line drive circuit and one gate line drive circuit are provided as drive circuits for driving the pixel portion. However, a plurality of drive circuits may be provided. Further, a known circuit structure may be used for the pixel portion, a driving circuit for driving the pixel portion, and a γ (gamma) correction circuit.

The electro-optical device of this embodiment is constituted by TFTs formed on an insulating substrate, and can be manufactured by using the method of manufacturing a nonvolatile memory according to the present invention. Note that steps after TFT formation, such as formation of a liquid crystal or EL layer, may be formed using a known method.

FIG. 12 is a block diagram of the electro-optical device. A source line drive circuit 76 and a gate line drive circuit 77 are provided around the pixel section 75, and a γ correction circuit 7
8. A nonvolatile memory 79 is provided. Further, an image signal, a clock signal, a synchronization signal, and the like are sent via an FPC (flexible print circuit) 80.

The non-volatile memory 79 stores (stores) correction data for performing γ correction on an image signal sent from the personal computer, a television receiving antenna or the like, and refers to the correction data to obtain γ. The correction circuit 78 performs γ correction on the image signal.

The data for γ correction may be stored once before shipping the electro-optical device, but it is also possible to periodically rewrite the correction data. Further, even in the case of an electro-optical device made in the same manner, the optical response characteristics of the liquid crystal (such as the relationship between the transmitted light intensity and the applied voltage) may be slightly different. Also in this case, in this embodiment, since different γ correction data can be stored for each electro-optical device, the same image quality can always be obtained.

Note that when storing the correction data of the γ correction in the nonvolatile memory 79, the applicant of the present invention disclosed in Japanese Patent Application No.
It is preferred to use the means described in 156696. Further, a description regarding gamma correction is also made in the same application.

Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.

Next, an example of an electro-optical device having at least the nonvolatile memory of the present invention, a pixel portion, a driving circuit for driving the pixel portion, and a memory controller circuit will be described with reference to FIG.
This will be described with reference to FIG.

The memory controller circuit in this embodiment is a control circuit for controlling operations such as storing and reading image data in a nonvolatile memory.

In this embodiment, as the driving circuit for driving the pixel portion, one source wiring driving circuit and one gate wiring driving circuit are provided, but a plurality of driving circuits may be provided. Further, a known circuit structure may be used for the pixel portion, a driver circuit for driving the pixel portion, and a memory controller circuit.

The electro-optical device of this embodiment is constituted by TFTs formed on an insulating substrate, and can be manufactured by using the method of manufacturing a nonvolatile memory according to the present invention. Note that steps after TFT formation, such as formation of a liquid crystal or EL layer, may be formed using a known method.

FIG. 13 is a block diagram of the electro-optical device of this embodiment. A source line driving circuit 8 is provided around the pixel portion 81.
2, a gate line driving circuit 83 is provided, a memory controller circuit 84, and a nonvolatile memory 85 of the present invention are provided.
Is provided. Further, an image signal, a clock signal, a synchronization signal, and the like are transmitted via an FPC (flexible print circuit) 86.

The non-volatile memory 85 stores (stores) an image signal sent from the personal computer, a television receiving antenna, or the like for each frame, and sequentially inputs the image signal to the pixel unit to display the image. Do. The non-volatile memory 85 stores image information for one frame displayed on the pixel unit 81. For example, when a 6-bit digital signal is sent as an image signal, a memory capacity equivalent to the number of pixels × 6 bits is required.

Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.

With the configuration of this embodiment, the image displayed on the pixel portion 81 is always stored in the non-volatile memory 85.
Operations such as temporary stop of an image can be easily performed.
That is, the image signal stored in the non-volatile memory 85 is always sent to the pixel unit 81 by the memory controller circuit 84, so that the television broadcast can be paused freely without recording on a video deck or the like. Become.

In this embodiment, an example in which one frame is stored has been described. However, the memory capacity of the nonvolatile memory 85 may be increased to such an extent that image information such as several hundred frames or several thousand frames can be stored. If so, it is possible to reproduce (replay) an image several seconds or several minutes ago as well as pause.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 7.

(Embodiment 9) The nonvolatile memory of the present invention has various uses. In this embodiment, electronic devices using these nonvolatile memories will be described.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display, a goggle type display, a game machine, a car navigation, a personal computer, and a portable information terminal (mobile computer, A mobile phone or an electronic book), a DVD player, and the like. Examples of these are shown in FIGS.

FIG. 14A shows a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like.
The nonvolatile memory of the present invention may be formed integrally with the display portion 2003 and other signal control circuits.

FIG. 14B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The nonvolatile memory of the present invention may be formed integrally with the display portion 2102 and other signal control circuits.

FIG. 14C shows a part (right side) of the head mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, and a display section 220.
4, including an optical system 2205, a display unit 2206, and the like. The nonvolatile memory of the present invention may be formed integrally with the display portion 2206 and other signal control circuits.

FIG. 14D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, a recording medium 2302, operation switches 2303, display units 2304 and 2305, and the like. This device uses a DVD (Digital Versatile Disc) as a recording medium and a C
Using D or the like, music viewing, movie viewing, games, and the Internet can be performed. The nonvolatile memory of the present invention may be formed integrally with the display portion 2304 and other signal control circuits.

FIG. 14E shows a goggle type display, which comprises a main body 2401, a display section 2402, and an arm section 240.
3 inclusive. The non-volatile memory of the present invention is a display unit 2402
And other signal control circuits.

FIG. 14F shows a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503,
It is composed of a keyboard 2504 and the like. The nonvolatile memory of the present invention may be formed integrally with the display portion 2503 and other signal control circuits.

FIG. 15A shows a portable telephone, and the main body 26 is provided.
01, audio output unit 2602, audio input unit 2603, display unit 2604, operation switch 2605, antenna 2606
including. The nonvolatile memory of the present invention may be formed integrally with the display portion 2604 and other signal control circuits.

FIG. 15B shows a sound reproducing device, specifically, a car audio.
2, including operation switches 2703 and 2704. The nonvolatile memory of the present invention may be formed integrally with the display portion 2702 and other signal control circuits. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to eighth embodiments.

[0197]

According to the present invention, the nonvolatile memory is
The driving circuit and other peripheral circuits are integrally formed on an insulating substrate, so that downsizing can be achieved.

According to the present invention, in each memory cell constituting the nonvolatile memory, the memory TFT and the switching TFT are formed on the same semiconductor active layer, so that the nonvolatile memory can be downsized. .

Further, according to the present invention, since the thickness of the semiconductor active layer of the nonvolatile memory is relatively thin, impact ionization is likely to occur, and a nonvolatile memory driven at low voltage and with little deterioration is realized.

Further, the nonvolatile memory according to the present invention has a T
The semiconductor device including the nonvolatile memory can be reduced in size by being formed integrally with an arbitrary circuit including an FT and an insulating substrate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a nonvolatile memory of the present invention.

FIG. 2 is a cross-sectional view of a memory cell constituting the nonvolatile memory of the present invention.

FIG. 3 is a view showing a manufacturing process of the nonvolatile memory according to the first embodiment;

FIG. 4 is a diagram showing a manufacturing process of the nonvolatile memory according to the first embodiment.

FIG. 5 is a view showing a manufacturing process of the nonvolatile memory according to the first embodiment;

FIG. 6 is a diagram showing a manufacturing process of the nonvolatile memory according to the first embodiment.

FIG. 7 is a top view of a memory cell included in the nonvolatile memory of the present invention.

FIG. 8 is a circuit diagram of a memory cell included in a nonvolatile memory according to a fourth embodiment.

FIG. 9 is a diagram showing a manufacturing process of the nonvolatile memory according to the second embodiment.

FIG. 10 is a view showing a manufacturing process of a nonvolatile memory according to a second embodiment;

FIG. 11 is a view showing a manufacturing process of the nonvolatile memory in Example 2;

FIG. 12 shows an electro-optical device using the nonvolatile memory according to the eighth embodiment.

FIG. 13 shows an electro-optical device using the nonvolatile memory according to the eighth embodiment.

FIG. 14 illustrates an electronic apparatus using the nonvolatile memory according to the ninth embodiment.

FIG. 15 illustrates an electronic apparatus using the nonvolatile memory according to the ninth embodiment.

[Explanation of symbols]

 101 X address decoder 102 Y address decoder 103, 104 Peripheral circuit 201, 202, 203 Source / drain region 204, 205 Channel formation region 206 First gate insulating film 207 Gate insulating film 208 Floating gate electrode 209 Gate electrode 210 Second Gate insulating film 211 Control gate electrode 212 Interlayer insulating film 213, 214 Source / drain wiring 215 Control gate wiring Tr1 Memory TFT Tr2 Switching TFT

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8242 H01L 29/78 612B 29/788 613B 29/792 618D 29/786 627G 21/336

Claims (24)

[Claims] 1. A non-volatile memory including at least a memory cell array in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, wherein the memory TFT is formed on a first insulating substrate. A semiconductor active layer, a first insulating film, a floating gate electrode, a second insulating film, a control gate electrode,
Wherein the switching TFT comprises at least a second semiconductor active layer formed on the insulating substrate, a gate insulating film, and a gate electrode. Is integrally formed on the insulating substrate, the first semiconductor active layer and the second semiconductor active layer are continuously connected, and the thickness of the first semiconductor active layer is 2. A nonvolatile memory characterized in that the thickness is smaller than the thickness of the semiconductor active layer. 2. The nonvolatile memory according to claim 1, wherein said first and second semiconductor active layers have a thickness of 1 to 150 nm. 3. A non-volatile memory in which memory cells each including a memory TFT and a switching TFT are arranged in a matrix, wherein the memory TFT includes a first semiconductor active layer formed on an insulating substrate; A first insulating film, a floating gate electrode, a second insulating film, a control gate electrode,
Wherein the switching TFT comprises at least a second semiconductor active layer formed on the insulating substrate, a gate insulating film, and a gate electrode. Is formed integrally on the insulating substrate, the first semiconductor active layer and the second semiconductor active layer are continuously connected, and the thickness of the first semiconductor active layer is 1 to 100 nm, and the thickness of the second semiconductor active layer is 1 to 150 nm. 4. The semiconductor device according to claim 1, wherein the first semiconductor active layer has a thickness of 1 to 50 nm, and the second semiconductor active layer has a thickness of 10 to 100 nm. A non-volatile memory, characterized in that: 5. The nonvolatile memory according to claim 4, wherein said first semiconductor active layer has a thickness of 10 to 40 nm. 6. The semiconductor device according to claim 1, wherein the first semiconductor active layer has a thickness in which impact ionization is more likely to occur than the second semiconductor active layer. Nonvolatile memory. 7. The switching TFT according to claim 1, wherein a first tunnel current flowing between a floating gate electrode of the memory TFT and a first semiconductor active layer is applied to a gate of the switching TFT. A nonvolatile memory characterized in that the current is at least twice as large as a second tunnel current flowing between an electrode and a second semiconductor active layer. 8. The memory TFT and the switching TFT according to claim 1, wherein:
Is a non-volatile memory, which is a p-channel TFT. 9. The non-volatile memory according to claim 1, further comprising at least a memory cell drive circuit, wherein said memory cell array and said memory cell drive circuit are provided. Is a non-volatile memory formed integrally on the insulating substrate. 10. A semiconductor device comprising, on an insulating substrate, at least a pixel portion, a driving circuit for driving the pixel portion, and the nonvolatile memory according to claim 1. Wherein the pixel unit, the drive circuit, and the non-volatile memory,
A semiconductor device integrally formed on the insulating substrate. 11. The semiconductor device according to claim 10, wherein the semiconductor device is a liquid crystal display device or an EL display device. 12. The semiconductor device according to claim 10, wherein the semiconductor device is a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio. 13. A method for fabricating a nonvolatile memory comprising at least a memory cell array in which memory cells each comprising a memory TFT and a switching TFT are arranged in a matrix, comprising: a first amorphous semiconductor layer on an insulating substrate; Forming a second amorphous semiconductor layer; crystallizing the first amorphous semiconductor layer and the second amorphous semiconductor layer to have a first thickness. Forming a crystalline semiconductor layer including a region and a region having a second thickness; forming a memory TFT using the region having the first thickness as a first semiconductor active layer; Forming a switching TFT using a region having a second film thickness as a second semiconductor active layer, wherein the first film thickness is equal to the second film thickness. It is characterized by being thinner than A method for manufacturing a nonvolatile memory. 14. The first and second film thicknesses are 1 to 150.
14. The method for manufacturing a nonvolatile memory according to claim 13, which is nm. 15. A method for fabricating a nonvolatile memory comprising at least a memory cell array in which memory cells each comprising a memory TFT and a switching TFT are arranged in a matrix, wherein a first amorphous semiconductor layer is formed on an insulating substrate. Forming a second amorphous semiconductor layer; and crystallizing the first amorphous semiconductor layer and the second amorphous semiconductor layer to have a first thickness. Forming a crystalline semiconductor layer including a region and a region having a second thickness; forming a memory TFT using the region having the first thickness as a first semiconductor active layer; Forming a switching TFT using a region having a second thickness as a second semiconductor active layer, comprising: a step of forming a switching TFT using a region having a second thickness as a second semiconductor active layer, wherein the first thickness is 1 to 100 nm. , The second film thickness is 1 to The method for manufacturing a nonvolatile memory, which is a 50nm. 16. The method according to claim 13, wherein:
3. The method for manufacturing a nonvolatile memory according to item 1, wherein the first film thickness is 1 to 50 nm and the second film thickness is 10 to 100 nm. 17. The method according to claim 16, wherein the first film thickness is 10 to 40 nm. 18. The method according to claim 13, wherein:
3. The method for manufacturing a nonvolatile memory according to item 1, wherein the first semiconductor active layer has a thickness more likely to cause impact ionization than the second semiconductor active layer. 19. The method according to claim 13, wherein:
In the above item, a first tunnel current flowing between a floating gate electrode of the memory TFT and a first semiconductor active layer is connected to a gate electrode of the switching TFT and a second tunnel current.
Of the second tunnel current flowing between the semiconductor
A method for manufacturing a nonvolatile memory, which is at least twice as large. 20. Any one of claims 13 to 19
In the paragraph, the memory TFT and the switching T
A method for manufacturing a nonvolatile memory, wherein the FT is a p-channel TFT. 21. Any one of claims 13 to 20
13. The method for fabricating a nonvolatile memory according to item 2, wherein the nonvolatile memory further includes at least a memory cell drive circuit, wherein the memory cell array and the memory cell drive circuit are mounted on the insulating substrate. A method for manufacturing a non-volatile memory, wherein the method is integrated with a non-volatile memory. 22. One of claims 13 to 21.
13. A method for manufacturing a semiconductor device using the method for manufacturing a nonvolatile memory according to item 13. The semiconductor device is manufactured by a method for manufacturing the nonvolatile memory, including a pixel portion, a driving circuit for driving the pixel portion, The pixel unit, the driving circuit, and the non-volatile memory,
A method for manufacturing a semiconductor device, which is formed over an insulating substrate. 23. The method for manufacturing a semiconductor device according to claim 22, wherein the semiconductor device is a liquid crystal display device or an EL display device. 24. The semiconductor device according to claim 22, wherein the semiconductor device is a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio. Production method.