JP4498685B2 - Method for manufacturing semiconductor memory element - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor memory element, and more particularly to a thin film transistor having a charge storage layer. The present invention also relates to a thin film transistor having a charge storage layer and a semiconductor memory device in which the thin film transistor is formed over a substrate having an insulating surface.
[0002]
[Prior art]
EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory are known as representative memories of semiconductor nonvolatile memory. Since these are non-volatile, unlike DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), which represent semiconductor memories, data is not lost even when the power is turned off. Further, when compared with a magnetic disk representing another nonvolatile memory, it has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like.
[0003]
As described above, the semiconductor non-volatile memory has characteristics suitable for portable devices, and application development to portable devices is being promoted. In particular, flash memories with high integration density have been widely applied, and in recent years, multi-value memories that further improve the integration degree have been commercialized. Of course, these are nonvolatile memories on a single crystal silicon substrate (see, for example, Non-Patent Document 1).
[0004]
[Non-Patent Document 1]
Fujio Takaoka, 7 others, "Flash Memory Technology Forum 2000", Science Forum, Inc., July 18, 2000
[0005]
On the other hand, with the spread of portable devices having a display unit such as a mobile phone, there is an increasing demand for a system-on-panel in which a display unit and a logic circuit unit are integrally formed on a substrate having an insulating surface. Along with this, a technique for manufacturing a nonvolatile memory on a substrate having an insulating surface has been required.
[0006]
[Problems to be solved by the invention]
When a nonvolatile memory is manufactured on a substrate having an insulating surface, a memory cell array is formed of semiconductor memory elements, and peripheral circuits such as a decoder circuit for selecting a memory cell and a write / read circuit are thin film transistors (hereinafter referred to as TFTs). The form which comprises is considered.
[0007]
In the present invention, a semiconductor memory element refers to a thin film transistor having a charge storage layer surrounded by an insulating film between a semiconductor active layer and a gate electrode. For example, a structure having a floating gate electrode, an MNOS structure, or a MONOS A thin film transistor having a structure is included in its category.
[0008]
When considering such a nonvolatile memory, improvement of the reliability of the semiconductor memory element accompanied by charge injection and charge discharge into the charge storage layer and improvement of the operation speed of the peripheral circuits are important issues.
[0009]
First, regarding the reliability of the semiconductor memory element, there are the following structural problems. FIG. 2 shows a structure of a typical semiconductor memory element manufactured over a substrate having an insulating surface. (A), (B), and (C) are a plan view, a channel length direction cross-sectional view, And a channel width direction sectional view. In FIG. 2, in the semiconductor memory element, a semiconductor active layer 202, a first gate insulating film 203, a floating gate electrode 204, a second gate insulating film 205, and a control gate electrode 206 are stacked on a substrate 201 having an insulating surface. It has a structure. The semiconductor active layer 202 includes a channel region 207 and a high concentration impurity region 208 to which an impurity of one conductivity type is added.
[0010]
Note that the floating gate electrode 204 is one form of a charge storage layer. Further, one of the high concentration impurity regions 208 may partially overlap the floating gate electrode 204 with the first gate insulating film 203 interposed therebetween.
[0011]
A problem regarding the reliability of the semiconductor memory element is the shape of the semiconductor active layer end 209. In the case of the semiconductor active layer shape as shown in FIG. 2, when a potential difference is applied between the control gate electrode and the active layer, the electric field is concentrated at the corner of the semiconductor active layer end, and the local area at the semiconductor active layer end 209 is localized. Charge injection / release occurs. As a result, the first gate insulating film deteriorates intensively at the semiconductor active layer end portion 209, and the reliability is lowered.
[0012]
In order to prevent local degradation of the first gate insulating film due to electric field concentration, it is effective to realize a structure of a semiconductor memory element that does not have an electric field concentration region such as the semiconductor active layer end 209. is there.
[0013]
Next, with respect to the operation speed of the memory, it is important to manufacture high-performance TFTs and semiconductor memory elements on a substrate having an insulating surface.
[0014]
The technology for forming TFTs on a substrate having an insulating surface has greatly advanced mainly through research and development of semiconductor display devices (typically, liquid crystal display devices and EL display devices). For example, a TFT using a polycrystalline silicon film has higher field effect mobility (also referred to as mobility) than a TFT using an amorphous silicon film, and control of a display portion that has been conventionally performed by a driver circuit outside the substrate. Can be performed by a driving circuit formed on the same substrate as the pixel.
[0015]
In the future, when a system-on-panel is taken into consideration, it is necessary to realize higher-speed operation, and TFTs with higher characteristics are required.
[0016]
In recent years, one of the technologies that attract attention that forms TFTs on a substrate having an insulating surface is a method for manufacturing a crystalline semiconductor film by laser light irradiation. As the laser oscillation device, a gas laser represented by an excimer laser or a solid laser represented by a YAG laser is usually used. In particular, in Japanese Patent Application Laid-Open No. 2001-144027, Nd: YVO _Four Using a solid-state laser oscillation device such as a laser, the amorphous semiconductor film is irradiated with laser light, which is the second harmonic, to form a crystalline semiconductor film having a larger crystal grain size than before, and a TFT is manufactured. Technology is disclosed.
[0017]
However, when an amorphous semiconductor film formed on a flat surface is crystallized by irradiating laser light, the crystal becomes polycrystalline, and the position of the crystal grain boundary including crystal defects cannot be controlled. . In addition, the semiconductor film volume shrinkage caused by crystallization, distortion or cracks due to thermal stress or lattice mismatch with the substrate, etc. occur, but this position could not be controlled.
[0018]
As a result, the crystallinity of the channel region of the TFT cannot be controlled, and eventually the individual device characteristics vary due to crystal grain boundaries and crystal defects included in the channel region.
[0019]
In other words, when a crystalline semiconductor film is formed by laser light irradiation, it is an important issue to control the crystallinity of the TFT channel region by controlling the position of the crystal grain boundary.
[0020]
Further, when realizing high-speed memory operation, it is important to improve not only the TFT characteristics but also the semiconductor memory element characteristics at the same time. That is, the improvement of the TFT characteristics increases the operation speed of the peripheral circuit, and the improvement of the characteristics of the semiconductor memory element increases the driving capability of the semiconductor memory element, thereby improving the reading speed.
[0021]
The present invention has been made in view of the above problems, and realizes a semiconductor memory element having a structure in which electric field concentration does not occur at the end of the active layer in the channel region, and the position of crystal grain boundaries, crystal defects, and cracks. By controlling the above, the channel region does not include crystal grain boundaries other than twins, and the field effect mobility is high and the variation is small. An object of the present invention is to provide a high-speed semiconductor memory device.
[0022]
[Means for Solving the Problems]
In order to solve the above problems, in a semiconductor memory element of the present invention, an insulating film provided with a linear recess is formed on a substrate having an insulating surface, and an amorphous semiconductor film or a polycrystalline film is formed on the insulating film. A semiconductor film is formed, and a crystalline semiconductor film is formed by melting and pouring the semiconductor film into a concave portion of the insulating film to crystallize, and the thickness of the crystalline semiconductor film is not more than the depth of the concave portion at least at a site where a channel region is formed. The surface of the crystalline semiconductor film is removed by etching so that the first gate insulating film, the floating gate electrode, the second gate insulating film, and the control gate electrode are in contact with the upper surface portion of the crystalline semiconductor film. It is what.
[0023]
The semiconductor memory device of the present invention has a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array has a plurality of linear recesses arranged in stripes on a substrate having an insulating surface. Crystallinity formed by forming an insulating film provided with stripe-shaped recesses, forming an amorphous semiconductor film or a polycrystalline semiconductor film on the insulating film, and melting and pouring the semiconductor film into the recesses of the insulating film The surface of the crystalline semiconductor film is removed by etching so that the thickness of the crystalline semiconductor film is equal to or less than the depth of the recess at least in a region where the channel region is formed, and a crystal is formed in accordance with the arrangement of the semiconductor memory element. An unnecessary region of the crystalline semiconductor film is removed by etching, and a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode that are in contact with the upper surface portion of the crystalline semiconductor film are removed. It is characterized in that to form the.
[0024]
According to another aspect of the present invention, a semiconductor memory device includes a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array stripes a plurality of linear recesses on a substrate having an insulating surface. Forming an insulating film provided with stripe-shaped concave portions arranged in a shape and inter-stripe concave portions connecting the stripe-shaped concave portions, and forming an amorphous semiconductor film or a polycrystalline semiconductor film on the insulating film to A crystalline semiconductor film is formed by melting and pouring a semiconductor film into a concave portion of the film and crystallizing the crystalline semiconductor film so that the thickness of the crystalline semiconductor film is equal to or less than the depth of the concave portion at least at a portion where a channel region is formed. The surface of the film is etched away, and unnecessary regions of the crystalline semiconductor film are removed by etching in accordance with the arrangement of the semiconductor memory elements and the connection between the semiconductor memory elements. The first gate insulating film in contact with the upper surface of the conductive film, a floating gate electrode, the second gate insulating film, and is characterized in forming a control gate electrode. In this configuration, the semiconductor film wiring for connecting the semiconductor memory element is formed by a crystalline semiconductor film formed in the recess between stripes.
[0025]
According to another aspect of the present invention, a semiconductor memory device includes a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array stripes a plurality of linear recesses on a substrate having an insulating surface. An insulating film provided with stripe-shaped recesses arranged in a row, an amorphous semiconductor film or a polycrystalline semiconductor film is formed on the insulating film, and the semiconductor film is melted and poured into the recesses of the insulating film for crystallization In the state in which the crystalline semiconductor film is formed, and the region to be the semiconductor film wiring for connecting the semiconductor memory element is masked with a photoresist, the thickness of the crystalline semiconductor film is at least the depth of the recess in the portion where the channel region is formed. The surface of the crystalline semiconductor film is etched away so that the following is achieved in accordance with the arrangement of the semiconductor memory element and the arrangement of the semiconductor film wiring connecting the semiconductor memory element. An unnecessary region of the crystalline semiconductor film is removed by etching to form a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode in contact with the upper surface portion of the crystalline semiconductor film It is. Note that in this configuration, the semiconductor film wiring for connecting the semiconductor memory element is formed of a crystalline semiconductor film that is not etched on the surface of the crystalline semiconductor film but is connected across the stripe-shaped recesses.
[0026]
Note that the semiconductor memory device refers to a nonvolatile memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a flash memory, and a general semiconductor device having such a nonvolatile memory as a semiconductor memory unit. For example, the category includes a microprocessor having a nonvolatile memory as a semiconductor storage unit, a semiconductor display device (typically, a liquid crystal display device and an EL display device), and a device in which these are mounted.
[0027]
Note that the amorphous semiconductor film referred to in the present invention is not limited to a film having a completely amorphous structure in a narrow sense, but includes a state in which fine crystal particles are included, or a so-called microcrystalline semiconductor film, a local Includes a semiconductor film including a crystal structure. Typically, an amorphous silicon film is applied, and in addition, an amorphous silicon germanium film, an amorphous silicon carbide film, or the like can also be applied. The polycrystalline semiconductor film is obtained by crystallizing these amorphous semiconductor films by a known method.
[0028]
FIG. 1 shows a typical structure of a semiconductor memory element constituting the semiconductor memory device of the present invention described above. (1), (2), and (3) are a plan view and a channel length direction sectional view, respectively. FIG. 5 is a cross-sectional view in the channel width direction. In FIG. 1, a semiconductor memory element includes a crystalline semiconductor active layer 102, a first gate insulating film 103, a floating gate formed in a linear recess provided by insulating films 109 and 110 on a substrate 101 having an insulating surface. The electrode 104, the second gate insulating film 105, and the control gate electrode 106 are stacked. The crystalline semiconductor active layer 102 includes a channel region 107 and a high concentration impurity region 108 to which an impurity of one conductivity type is added.
[0029]
Note that one of the high-concentration impurity regions 108 may partially overlap with the floating gate electrode 104 with the first gate insulating film 103 interposed therebetween.
[0030]
In the semiconductor memory element of the present invention, the channel region is formed by a step of etching and removing the surface of the crystalline semiconductor film so that the thickness of the crystalline semiconductor film is equal to or less than the depth of the recess at least in a region where the channel region is formed. The side surface of the crystalline semiconductor film is completely covered with the side wall of the recess.
[0031]
As shown in FIG. 1, the thickness of the crystalline semiconductor active layer may be smaller than the thickness of the insulating films 109 and 110, and the thickness of the crystalline semiconductor active layer is the same as the thickness of the insulating films 109 and 110. It may be the same.
[0032]
Since the cross-sectional structure of the semiconductor memory element is a flat surface with no corners at the interface between the semiconductor active layer and the first gate insulating film, the electric field is concentrated at the edge of the semiconductor active layer, and charge injection / discharge is locally performed. Nothing happens. As a result, local degradation of the first gate insulating film can be prevented, and high reliability can be realized.
[0033]
Note that the above-described semiconductor memory device may include a peripheral circuit such as a decoder circuit, a write / read circuit, and other semiconductor integrated circuits on a substrate on which the memory cell is formed, and the like. In that case, in order to realize high-speed operation of the memory, it is preferable to manufacture a TFT constituting a peripheral circuit or another semiconductor integrated circuit using the crystalline semiconductor film formed by the above-described method.
[0034]
A method for forming a crystalline semiconductor film will be further described.
[0035]
The linear recesses or stripe-like recesses described above are provided so as to extend in the channel length direction. The width of the recess (channel width in the case of forming a channel formation region) is 0.01 μm or more and 2 μm or less, preferably 0.1 to 1 μm, and the depth is 0.01 μm or more and 3 μm or less, preferably 0.1 μm. The thickness is 2 μm or less.
[0036]
As a means for melting and crystallizing the crystalline semiconductor film, pulsed oscillation or continuous oscillation laser light using a gas laser oscillation device or a solid laser oscillation device as a light source is applied. The laser light to be irradiated is focused in a linear shape by an optical system, and the intensity distribution may have a uniform region in the longitudinal direction and may be distributed in the lateral direction. As the oscillation device, a rectangular beam solid laser oscillation device is applied, and a slab laser oscillation device is particularly preferably applied.
[0037]
Irradiate an amorphous semiconductor film or a polycrystalline semiconductor film with laser light or strong light condensed in a linear shape and extended in the longitudinal direction, and the irradiation position of the laser light and the substrate on which the semiconductor film is formed are relative to each other. Then, the semiconductor film is melted by scanning a part or the whole surface of the laser beam, and crystallization or recrystallization is performed through this state. The scanning direction of the laser light is performed in a direction parallel to the linear recess formed in the insulating film or in the channel length direction of the transistor. As a result, the crystal grows along the scanning direction of the laser beam, and the crystal grain boundary can be prevented from crossing the channel length direction.
[0038]
By setting the depth of the recesses to be equal to or greater than the thickness of the semiconductor film, the semiconductor melted by the irradiation with laser light or strong light aggregates and solidifies in the recesses due to surface tension. At this time, by causing the crystal to grow from the bottom end portion of the concave portion, the distortion generated along with the crystallization is concentrated in a region other than the concave portion. On the other hand, the crystalline semiconductor film formed so as to fill the recesses can be free from strain. Then, the crystalline semiconductor film remaining around the recess including crystal grain boundaries and crystal defects is removed by etching.
[0039]
The semiconductor memory element manufactured as described above includes a crystalline semiconductor film that does not include a crystal grain boundary other than twins in a linear recess provided on an insulating surface.
[0040]
According to the present invention, in the semiconductor memory element and the TFT, it is possible to designate the location of the channel formation region and form a crystalline semiconductor film that does not include crystal grain boundaries other than twins. That is, by controlling the crystallinity of the channel region of the TFT and increasing the crystallinity of the channel region, it is possible to manufacture a semiconductor memory element and a TFT with high field effect mobility and small characteristic variation. As a result, it is possible to realize a semiconductor memory device that realizes high-speed operation by increasing the peripheral circuit speed by improving the TFT characteristics and increasing the read speed by improving the semiconductor memory element characteristics.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
As an embodiment of the semiconductor memory device of the present invention, a circuit configuration and an operation method of a nonvolatile memory will be described.
[0042]
The present invention is characterized by the structure of the semiconductor memory element, the semiconductor active layer, and the structure of the TFT constituting the peripheral circuit and the semiconductor active layer, and a known technology may be used for the circuit configuration and operation method of the memory cell. In this embodiment, a circuit configuration and an operation method of a NOR flash memory as a typical nonvolatile memory will be briefly described.
[0043]
FIG. 7 shows a block circuit diagram of a NOR type flash memory having a storage capacity of m × n bits. The NOR flash memory shown in FIG. 7 includes a memory cell array 701 in which a plurality of memory cells (1, 1) to (n, m) are arranged in a matrix of m vertical × n horizontal, and an X address decoder 703. , A Y address decoder 702, a Y selector 704, and a write / read circuit 705. As other peripheral circuits, a booster circuit, an address buffer circuit, or the like may be provided.
[0044]
Each memory cell (typically, a memory cell (i, j) is considered. Here, i is an integer of 1 to n and j is an integer of 1 to m) is constituted by an n-channel semiconductor memory element. The The drain electrode and the control gate electrode of the semiconductor memory element are connected to the bit line BL (i) and the word line WL (j), respectively. The bit lines BL (1) to BL (n) are connected to the Y address decoder 702, and the word lines WL (1) to WL (m) are connected to the X address decoder 703, respectively. Further, the source electrodes of all the semiconductor memory elements are connected to a common source line, and are supplied with a source line potential Vs.
[0045]
Data writing and reading are performed in the memory cell selected by the X address decoder 703 and the Y address decoder 702. Taking a memory cell (1, 1) as an example, a write operation and a read operation using hot electrons will be described.
[0046]
First, when data is written in the semiconductor memory element, the source line is dropped to GND, and a positive high voltage (for example, 16 V) is applied to the bit line BL (1) and the word line WL (1), respectively. Under such conditions, impact ionization occurs due to a high electric field in the vicinity of the drain of the semiconductor memory element. Further, since a high electric field is generated also in the gate direction, the generated hot electrons are injected into the floating gate electrode and writing is performed. The threshold voltage of the semiconductor memory element changes according to the amount of charge accumulated in the floating gate electrode.
[0047]
When reading data stored in the semiconductor memory element, the source line is dropped to GND and a predetermined voltage is applied to the word line WL (1). The predetermined voltage may be set between a threshold voltage in a state where charges are accumulated in the floating gate electrode of the semiconductor memory element and a threshold voltage in a state where charges are not accumulated. As a result, the semiconductor memory element in which the charge is accumulated in the floating gate electrode is turned off, and the semiconductor memory element that is not accumulated is turned on, so that it is stored in the memory cell (1, 1). Data is read from the bit line BL (1).
[0048]
For example, when the two-state threshold voltages of the semiconductor memory element are 2 V or less and 4 V or more, 3 V can be used as the predetermined voltage.
[0049]
Data is erased simultaneously for a plurality of selected memory cells. For example, when erasing the memory cells (1, 1) to (m, 1) in the first column, the source line and the word line WL (1) are dropped to GND, and a positive high voltage is applied to the bit line BL (1). (For example, 20V) is applied. At this time, since a high potential difference is generated between the gate and the drain of the semiconductor memory element, electrons accumulated in the floating gate electrode are emitted to the drain region by a tunnel current, and erasing is performed. As described above, when the charge is extracted from the drain region of the semiconductor memory element, it is preferable that the high-concentration impurity region on the drain side and the floating gate electrode partially overlap with each other through the first gate insulating film.
[0050]
Note that the potentials of the signal lines BL (2) to BL (n) and WL (2) to WL (m) that are not selected at the time of writing, reading, and erasing may be 0V. Moreover, the value of the operating voltage described above is an example, and the value is not limited to that value.
[0051]
In this embodiment, the case where binary (1 bit) information is stored in one semiconductor memory element has been described. However, a multi-value nonvolatile memory that stores information of three values or more in one semiconductor memory element. It does not matter. Further, the present invention is not limited to the NOR type flash memory, but can be similarly applied to a NAND type flash memory and an AND type flash memory. In addition, it may be a non-volatile memory of a type that constitutes a memory cell with one semiconductor memory element and one selection TFT, or a split gate having the role of the selection TFT and the semiconductor memory element. A non-volatile memory of a type that constitutes a memory cell with a semiconductor memory element having a structure may be used.
[0052]
(Embodiment 2)
A method for forming a crystalline semiconductor film in the present invention will be described. 3 to 6 are used for the description. The perspective view shown in FIG. 3 shows a form in which a first insulating film 302 and second insulating films 303 to 306 are formed on a substrate 301, and a stripe-shaped recess is provided by the insulating film. In FIG. 3, three linear recesses are shown, but the number is not limited to that.
[0053]
As the substrate, a commercially available non-alkali glass substrate, a quartz substrate, a sapphire substrate, a substrate obtained by coating the surface of a single crystal or polycrystalline semiconductor substrate with an insulating film, or a substrate obtained by coating the surface of a metal substrate with an insulating film can be applied.
[0054]
In order to form a stripe-shaped recess with a sub-micron design rule, it is necessary to keep the unevenness of the substrate surface, the undulation or twist of the substrate below the depth of focus of the exposure apparatus (especially a stepper). It is desirable that the unevenness of the substrate surface in the exposure region, the waviness or twist of the substrate is 1 μm or less, preferably 0.5 μm or less.
[0055]
The width W2 of the second insulating films 303 to 306 is 0.1 to 10 μm (preferably 0.5 to 1 μm), and the interval W1 between adjacent second insulating films is 0.01 to 2 μm (preferably 0.1 to 1 μm). The thickness d1 of the second insulating film is 0.01 to 3 μm (preferably 0.1 to 2 μm). The stripe pattern does not need to have a regular cycle, and may be arranged at a predetermined interval in accordance with the width of the island-shaped semiconductor film. The length of the linear concave portion is not limited, and may be any length that can form the channel region of the TFT, for example.
[0056]
The first insulating film is made of silicon nitride, a material selected from silicon oxynitride, aluminum nitride, or aluminum oxynitride having a nitrogen content larger than the oxygen content, and is formed to a thickness of 30 to 300 nm. Further, the second insulating film in which the concave portion is formed in a predetermined shape is formed of silicon oxide or silicon oxynitride so that the thickness d1 is 10 to 3000 nm, preferably 100 to 2000 nm. Silicon oxide is composed of tetraethyl orthosilicate (TEOS) and O ₂ And can be formed by a plasma CVD (Chemical Vapor Deposition) method. Silicon nitride oxide film is SiH _Four , NH _Three , N ₂ O or SiH _Four , N ₂ It can be formed by plasma CVD using O as a raw material.
[0057]
As shown in FIG. 3, when a linear stripe pattern is formed by two layers of insulating films, it is necessary to provide a selection ratio between the first insulating film and the second insulating film in the etching process. Actually, it is desirable to appropriately adjust the material and the film forming conditions so that the etching rate of the second insulating film is relatively faster than that of the first insulating film. Etching using buffered hydrofluoric acid or CHF _Three Performed by dry etching using At this time, the angle of the side surface portion of the recess formed by the second insulating film may be appropriately set in the range of 5 to 120 degrees, preferably 80 to 100 degrees.
[0058]
Note that, here, an example in which the uneven shape of the base on which the crystalline semiconductor film is formed is formed using the first insulating film and the second insulating film, but is not limited to the form shown here and has a similar shape. It can be replaced if there is one. For example, the concave surface may be formed directly by etching the surface of the quartz substrate to provide an uneven shape.
[0059]
As shown in FIG. 4, the semiconductor film 401 has a thickness of 0.01 to 3 μm (preferably 0.1 to 1 μm) using silicon, a compound or alloy of silicon and germanium, or a compound or alloy of silicon and carbon. Form. That is, it is desirable that the thickness d2 of the semiconductor film 401 is approximately equal to or greater than the depth of the recess formed by the second insulating film. As the semiconductor film 401, an amorphous semiconductor film or a polycrystalline semiconductor film formed by a plasma CVD method, a sputtering method, or a low pressure CVD method, a polycrystalline semiconductor film formed by solid phase growth, or the like is applied. As shown in the drawing, the semiconductor film 401 is formed so as to cover the concavo-convex structure formed by the underlying first insulating film and second insulating film. Further, an amorphous semiconductor film is removed so as to eliminate the influence of chemical contamination such as boron adhering to the surfaces of the first insulating film and the second insulating film, and so that the insulating surface and the amorphous semiconductor film are not in direct contact with each other. A silicon oxynitride film may be continuously formed as a third insulating film on the lower layer side of the substrate without being exposed to the atmosphere in the same film formation apparatus.
[0060]
Then, the semiconductor film 401 is instantaneously melted and crystallized. In this crystallization, laser light or radiated light from a lamp light source is condensed and irradiated with an optical system to an energy density that melts the semiconductor film. In this step, it is particularly preferable to apply laser light using a continuous wave laser oscillation device as a light source. The applied laser light is linearly condensed by the optical system and expanded in the longitudinal direction, and its intensity distribution has a uniform region in the longitudinal direction and has a distribution in the lateral direction. It is desirable.
[0061]
As the laser oscillation device, a rectangular beam solid-state laser oscillation device is applied, and a slab laser oscillation device is particularly preferably applied. Crystals such as Nd: YAG, Nd: GGG (gadolinium / gallium / garnet), Nd: GsGG (gadolinium / scandium / gallium / garnet) are used as the slab material. A slab laser travels in a zigzag optical path through this plate-like laser medium while repeating total reflection. Alternatively, it is a solid state laser oscillation device using a rod doped with Nd, Tm, and Ho, especially YAG, YVO. _Four , YLF, YAlO _Three A slab structure amplifier may be combined with a solid-state laser oscillation device using a crystal doped with Nd, Tm, or Ho.
[0062]
The wavelength of the continuous wave laser beam is preferably 400 to 700 nm in consideration of the light absorption coefficient of the semiconductor film. Light in such a wavelength band is obtained by taking out the second harmonic and the third harmonic of the fundamental wave using a wavelength conversion element. As wavelength conversion element, ADP (ammonium dihydrogen phosphate), Ba ₂ NaNb _Five O ₁₅ (Sodium barium niobate), CdSe (selenium cadmium), KDP (potassium dihydrogen phosphate), LiNbO _Three (Lithium niobate), Se, Te, LBO, BBO, KB _Five Etc. apply. It is particularly desirable to use LBO. A typical example is Nd: YVO _Four The second harmonic (532 nm) of the laser oscillation device (fundamental wave 1064 nm) is used. Further, a single mode which is a TEM00 mode is applied as the laser oscillation mode.
[0063]
Moreover, you may irradiate the strong light according to a laser beam. For example, light having a high energy density obtained by condensing light emitted from a halogen lamp, xenon lamp, high-pressure mercury lamp, metal halide lamp, or excimer lamp by a reflecting mirror or a lens may be used.
[0064]
In the case of silicon selected as the most suitable material, the absorption coefficient is 10 ^Three -10 ^Four cm ^-1 The region which is is almost in the visible light region. When crystallizing a substrate having a high visible light transmittance such as glass and an amorphous semiconductor film formed with a thickness of 30 to 200 nm using silicon, by irradiating light in the visible light region with a wavelength of 400 to 700 nm, Crystallization can be performed without selectively damaging the base insulating film by selectively heating the semiconductor film. Specifically, the penetration depth of light with a wavelength of 532 nm is approximately 100 nm to 1000 nm with respect to the amorphous silicon film, and can sufficiently reach the inside of the amorphous semiconductor film formed with a film thickness of 30 nm to 200 nm. . That is, it is possible to heat from the inside of the semiconductor film, and almost the entire semiconductor film in the laser light irradiation region can be heated uniformly.
[0065]
The laser beam scans in a direction parallel to the linear recess direction, and the molten semiconductor flows into the recess due to surface tension and solidifies. In the solidified state, the surface becomes almost flat as shown in FIG. As a result, a crystalline semiconductor film 501 having a thickness d3 larger than the thickness d4 on the second insulating film is formed on the recess. The crystalline semiconductor film 501 thus formed is characterized in that crystal growth ends and crystal grain boundaries are formed on the second insulating film, and the crystal grain boundaries other than twins are not included in the recessed region. .
[0066]
After that, heat treatment is preferably performed at 500 to 600 ° C. to remove distortion accumulated in the crystalline semiconductor film. This distortion occurs due to semiconductor volume shrinkage caused by crystallization, thermal stress with the base, or lattice mismatch. This heat treatment may be performed using a normal heat treatment apparatus. For example, a gas heating rapid thermal annealing (RTA) method may be used for 1 to 10 minutes. Note that this step is not an essential requirement in the present invention, and may be selected as appropriate.
[0067]
Thereafter, as shown in FIG. 6, the surface of the crystalline semiconductor film 501 is etched to selectively extract the crystalline semiconductor films 601, 602, and 603 embedded in the recesses. Only a high-quality semiconductor region can be left by etching and removing the region including the crystal growth edge and the crystal grain boundary formed on the second insulating film. At this time, the side surfaces of the crystalline semiconductor films 601, 602, and 603 are completely covered with the side walls of the recesses. That is, the thickness d5 of the crystalline semiconductor films 601, 602, and 603 is set to be equal to or less than the thickness d1 of the second insulating film.
[0068]
In order to obtain such a crystalline semiconductor film, a configuration in which the thickness (recess depth) d1 of the second insulating film is approximately equal to or larger than the thickness d2 of the semiconductor film 401 is most suitable. . When the thickness (depth of the recess) d1 of the second insulating film is smaller than the thickness d2 of the semiconductor film 401, the surface of the crystalline semiconductor film 501 is not sufficiently planarized because the recess is shallow. Note that in the case where the thickness (depth of the recess) d1 of the second insulating film is sufficiently larger than the thickness d2 of the semiconductor film 401, the crystalline semiconductor film 501 flows into the recess and is formed on the second insulating film 203. It is also possible to make it hardly remain. Further, when the width W2 of the recess is larger than 1 μm, not only a crystal grain boundary is formed on the second insulating film, but also a tendency that a crystal grain boundary tends to be generated near the center of the recess. . This is presumed to be because the effect of stress relaxation is reduced by increasing the interval.
[0069]
The scanning electron microscope (SEM) photograph shown in FIG. 25 shows an example. A 150 nm amorphous silicon film is formed on a base insulating film provided with a step of 170 nm and a width and interval of a recess of 0.5 μm. The results of crystallization are shown. The surface of the crystalline semiconductor film is a seco liquid (HF: H) in order to reveal the grain boundary. ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ Etched with a chemical solution prepared using
[0070]
FIG. 28 shows a sketch of the SEM photograph shown in FIG. 28, a hatched portion 2802 is a region where the second insulating film shown in FIG. 3 is present, and a region 2803 sandwiched between the hatched portions 2802 is a recessed region. A thick line 2801 represents a crack or a crystal grain boundary. As is clear from FIGS. 28 and 25, the crystal grain boundaries are concentrated on the second insulating film, and it can be seen that no remarkable grain boundaries are observed in the recessed region.
[0071]
In FIGS. 28 and 25, the scanning direction of the laser light is from the bottom to the top. Further, the second insulating film is exposed at the lower end of the hatched portion 2802. This is presumably because the melted silicon film moved in the scanning direction of the laser beam and solidified in the crystallization process by laser beam irradiation.
[0072]
FIG. 26 shows the result of obtaining the orientation of the crystalline semiconductor film formed in the concave portion by a reflected electron diffraction pattern (EBSP). EBSP provides a scanning electron microscope (SEM) with a dedicated detector, which irradiates the crystal plane with an electron beam and causes the computer to recognize the crystal orientation from the Kikuchi line. The crystallinity is measured not only on the surface orientation but also in all directions of the crystal (hereinafter, this method is referred to as EBSP method for convenience).
[0073]
The data in FIG. 26 indicates that the crystal grows in the direction parallel to the scanning direction of the laser beam condensed linearly in the concave portion. It is confirmed that the growth plane orientation is almost uniform in the same linear recess.
[0074]
Further, FIG. 27 shows a cross-sectional transmission electron microscope as a result of crystallization by forming a 150 nm amorphous silicon film on a base insulating film having a step of 170 nm and a width and interval of a recess of 0.5 μm. (Transmission Electron Microscope: TEM) A photograph is shown.
[0075]
In the photograph shown in FIG. 27, a stripe pattern cross section exists in the longitudinal direction of the photograph center. In the cross section of the stripe pattern, the dark gray region is the second insulating film, and the crystalline silicon film is formed in the recess formed between the second insulating films and the thin region on the second insulating film. It can be seen that a black region is seen in the crystalline silicon film on the second insulating film, and crystal grain boundaries are concentrated on the second insulating film. It can be seen that the linear boundaries seen in the crystalline silicon film formed in the recess are twins, and the crystal semiconductor film in the recess does not contain crystal grain boundaries other than twins.
[0076]
According to the above-described method, a crystalline semiconductor film having substantially uniform crystal orientations that does not include crystal grain boundaries other than twins in the recesses can be left. Then, in accordance with the arrangement of the semiconductor memory element, the active layer is cut out so that the high-quality crystalline semiconductor film in the recess becomes the channel region, and the first gate insulating film and the floating gate electrode are formed. By forming the semiconductor memory element of the present invention through each of these steps, it is possible to realize a semiconductor memory element with small characteristic variation and high current driving capability.
[0077]
At the same time, by completely covering the side surfaces of the crystalline semiconductor film with the sidewalls of the recesses, it is possible to obtain a structure without electric field concentration at the active layer edge during charge injection and emission to the floating gate electrode, A highly reliable semiconductor memory element can be realized.
[0078]
Further, by the above-described method, the active layer is cut out so that the high-quality crystalline semiconductor film of the recess becomes a channel region in accordance with the arrangement of the TFT, and the gate insulating film and the gate electrode are formed. Thus, it is possible to realize a TFT having a high current driving capability. By forming the memory cell and the peripheral circuit at the same time using the semiconductor memory element and the TFT described above, a semiconductor memory device with high reliability and capable of operating at high speed can be realized.
[0079]
(Embodiment 3)
Next, a semiconductor memory element and a TFT in which a crystalline silicon film is formed over a base insulating film having a recess and a channel formation region is provided in the filling region filled in the recess are used with reference to the drawings. I will explain. In each drawing according to the present embodiment, (1) is a top view, and (2) to (5) are longitudinal sectional views of corresponding parts.
[0080]
In this embodiment mode, a memory cell array and a peripheral circuit are manufactured at the same time. A part of a NOR type memory cell array in which semiconductor memory elements are arranged in a matrix is shown on the right side of the drawing, and a peripheral circuit is shown on the left side. As an example, a mode of manufacturing an inverter including an n-channel TFT and a p-channel TFT will be described.
[0081]
FIG. 8 shows a form in which a first insulating film 802 and a second insulating film 803 are formed on a glass substrate 801, and a stripe-shaped recess is formed on the insulating surface. The form shown in FIG. 8 can be manufactured by the method described in Embodiment 2. In this embodiment, the first insulating film 802 is formed of aluminum oxynitride having a thickness of 30 to 300 nm. The second insulating film 803 is formed by plasma CVD with TEOS and O ₂ And a reaction pressure of 40 Pa, a substrate temperature of 400 ° C., and a high frequency (13.56 MHz) power density of 0.6 W / cm. ² A silicon oxide film is deposited to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm, and then a recess is formed by etching. The width of the recess is 0.01 to 2 [mu] m, preferably 0.1 to 1 [mu] m, particularly in the place where the channel forming region is arranged.
[0082]
After that, as shown in FIG. 9, a third insulating film 901 made of an oxide film or a silicon oxynitride film and an amorphous silicon film are formed on the first insulating film 802 and the second insulating film 803 using the same plasma CVD apparatus. The film is continuously formed without being touched. The amorphous silicon film is formed of a semiconductor film containing silicon as a main component, and SiH is formed by plasma CVD. _Four Is used as a raw material gas. The amorphous silicon film has a non-flat surface shape reflecting the step shape of the base.
[0083]
Crystallization is performed by irradiating a continuous wave laser beam. FIG. 9 shows the state after the crystallization. The crystallization conditions are YVO in continuous oscillation mode. _Four Using a laser oscillator, the output of 5 to 10 W of the second harmonic (wavelength 532 nm) is condensed into linear laser light having a ratio of the longitudinal direction to the transverse direction of 10 or more in the optical system, and the longitudinal direction. Are condensed so as to have a uniform energy density distribution, and are crystallized by scanning at a speed of 10 to 200 cm / sec. A uniform energy density distribution does not exclude anything that is completely constant, but the allowable range in the energy density distribution is ± 10%.
[0084]
The relationship between the scanning direction of the laser beam condensed linearly and the arrangement of the recesses is shown in FIG. It is desirable that the intensity distribution of the laser beam 2160 condensed in a linear shape has a region where the intensity distribution is uniform in the longitudinal direction. This is because the temperature of the semiconductor to be heated makes the temperature of the irradiated region constant. This is because if the temperature distribution is generated in the longitudinal direction of the laser beam condensed linearly (direction intersecting the scanning direction), the crystal growth direction cannot be limited to the scanning direction of the laser beam. As shown in the figure, the linear stripe pattern is aligned with the scanning direction of the linearly focused laser beam 2160 so that the crystal growth direction matches the channel length direction of all transistors. Can do. Thereby, the characteristic variation between the elements of the transistor can be reduced.
[0085]
Further, the crystallization by the laser beam condensed linearly may be completed by only one scan (that is, one direction), or may be reciprocated to improve the crystallinity. Furthermore, after crystallizing with laser light, the surface of the silicon film is treated with an alkali solution such as oxide removal with hydrofluoric acid or ammonia hydrogen peroxide solution treatment, and the poor quality part with high etching rate is selectively used. It may be removed and the same crystallization treatment may be performed again. In this way, crystallinity can be increased.
[0086]
By irradiating laser light under these conditions, the amorphous silicon film is instantaneously melted and crystallized. In practice, crystallization proceeds while the melting zone moves. The molten silicon is agglomerated and solidified in the recesses due to surface tension. As a result, as shown in FIG. 9, a crystalline silicon film 902 having a flat surface is formed in a form filling the recess.
[0087]
Thereafter, as shown in FIG. 10, the surface of the crystalline silicon film 902 is removed by etching in a state where the region to be the source / drain region and the region to be the wiring using the crystalline silicon film are masked with a photoresist. At this time, an etching process is performed so that only the crystalline silicon film embedded in the recess remains in the region not masked with the photoresist. As a result, at least in the portion that becomes the channel region, the side surface of the crystalline silicon film is completely covered with an insulating film that forms a recess. By this etching process, a crystalline silicon film 1001 in which a non-masking region is buried in a recess and the masked region is connected between the recesses is obtained. The crystalline silicon film can be etched selectively with the underlying oxide film by using a fluorine-based gas and oxygen as etching gases. For example, as an etching gas, CF _Four And O ₂ The mixed gas is applied.
[0088]
Further, island-shaped silicon films 1101 to 1103 shown in FIG. 11 are formed from the crystalline silicon film 1001 shown in FIG. This island-shaped silicon film has a feature that no crystal grain boundaries other than twins are included as shown in the second embodiment. Note that FIG. 11 does not limit the shape of the island-shaped silicon films 1101 to 1103, and the island-shaped silicon films 1101 to 1103 may be designed freely within a range in accordance with a predetermined design rule.
[0089]
In this embodiment, the semiconductor memory element is formed using a crystalline silicon film formed in one linear recess so as to minimize the element area, and the source line connected to the semiconductor memory element is crystalline. An island-shaped silicon film 1103 as shown in FIG. 11 is formed by using a silicon film. On the other hand, it is necessary to design the channel width of the TFT constituting the peripheral circuit according to the required current driving capability. By using a crystalline silicon film formed in a plurality of linearly recessed portions as a channel region, A TFT structure in which channel regions are arranged in parallel (referred to as a multi-channel TFT) is used, and island-shaped silicon films 1101 and 1102 as shown in FIG. 11 are used.
[0090]
Thereafter, as shown in FIG. 12, the upper surface of the island-like silicon films 1101 to 1103 is covered, the fourth insulating film 1201 used as the gate insulating film of the TFT and the first gate insulating film of the semiconductor memory element, and the gate electrode of the TFT And conductive films 1202 and 1203 used as floating gate electrodes of the semiconductor memory element, a fifth insulating film 1204 used as the second gate insulating film of the semiconductor memory element, and a conductive film 1205 used as the control gate electrode of the semiconductor memory element. To do. As the fourth insulating film 1201 and the fifth insulating film 1204, a silicon oxide film or a silicon oxynitride film with a thickness of 30 to 200 nm is formed using a known vapor phase method (plasma CVD method, sputtering method, or the like). As the fifth insulating film 1204, SiO ₂ / SiN / SiO ₂ A laminated film (referred to as ONO film) may be formed. In addition, the conductive films 1202, 1203, and 1205 are formed using tungsten, an alloy containing tungsten, aluminum, an aluminum alloy, polycrystalline silicon, or the like.
[0091]
Note that in the case where a quartz substrate is used as the substrate having an insulating surface, the fourth insulating film 1201 used as the first gate insulating film of the semiconductor memory element may be formed by a thermal oxidation process. For example, a heat treatment at 950 ° C. is performed in an oxidizing atmosphere to form a thermal oxide film having a thickness of 10 to 200 nm. As a result, a good quality oxide film and a semiconductor / insulating film interface with few interface states can be obtained, and high reliability of the first gate insulating film can be obtained. The first gate insulating film may have a stacked structure of a deposited film and a thermal oxide film by performing a thermal oxidation process after forming a silicon oxide film or a silicon oxynitride film. Also in this case, a semiconductor / insulating film interface with a low interface state is obtained, and high reliability is obtained.
[0092]
In the conventional semiconductor memory element, if thermal oxidation is performed at the time of forming the first gate insulating film, thermal oxidation proceeds on the bottom of the active layer near the edge of the active layer, and the shape of the short portion of the active layer is distorted. There was a problem of lowering reliability due to concentration of electric field. In the semiconductor memory element of the present invention, since the side surface of the semiconductor active layer is covered with the side wall of the recess, thermal oxidation proceeds only on the upper surface of the active layer even near the edge of the active layer. There is no problem of thermal oxidation.
[0093]
FIG. 13 shows a step of forming one conductivity type impurity regions 1301 to 1303 in the island-shaped semiconductor films 1101 to 1103. Here, n-type impurity regions 1302 and 1303 and a p-type impurity region 1301 are provided. These impurity regions may be formed in a self-aligned manner using the conductive film 1202 used as the gate electrode of the TFT and the conductive film 1205 used as the control gate electrode of the semiconductor memory element as a mask, or may be formed using a photoresist as a mask. good. The impurity regions 1301 to 1303 form source / drain regions, and a low-concentration drain region can be appropriately provided as necessary.
[0094]
For the impurity regions 1301 to 1303, an ion implantation method or an ion doping method in which impurity ions are accelerated by an electric field and implanted into a semiconductor film is applied.
[0095]
Then, as shown in FIG. 14, a sixth insulating film 1401 made of a silicon nitride film or a silicon oxynitride film is formed, and a wiring 1402 in contact with an impurity region forming a source / drain region is formed. After that, by performing heat treatment at 400 to 450 ° C., hydrogen contained in the silicon nitride film or the silicon oxynitride film is released, and the island-shaped semiconductor film can be hydrogenated.
[0096]
Thus, as shown in FIG. 14, a NOR type memory cell array composed of semiconductor memory elements 1405 and an inverter circuit composed of n-channel type multi-channel TFTs 1403 and p-channel type multi-channel TFTs 1404 are formed on behalf of peripheral circuits. can do. Of course, the present invention is not limited to this configuration, and even other known memory cell arrays, other CMOS circuits, or circuits composed of unipolar TFTs can be manufactured in the same manner as in this embodiment. Further, the number of channel formation regions arranged in parallel is not limited, and an arbitrary number may be provided as necessary.
[0097]
As described above, in accordance with the arrangement of the semiconductor memory element and the TFT, at least in the channel region of the semiconductor memory element, the side surface of the crystalline semiconductor film is covered by the side wall of the recess and does not include a crystal grain boundary other than twins. An active layer is cut out so that a crystalline semiconductor film becomes a channel region. In a semiconductor memory element, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are formed. By forming the film and the gate electrode respectively, it is possible to simultaneously manufacture a semiconductor memory element with high reliability, small characteristic variation, and high current drive capability, and a TFT with low characteristic variation and high current drive capability. It becomes.
[0098]
As a result, it is possible to realize a highly reliable and high-speed semiconductor memory device in which a memory cell array in which semiconductor memory elements are arranged in a matrix and a peripheral circuit including TFTs are formed on the same substrate. It becomes possible.
[0099]
【Example】
Example 1
The present invention can be applied to various semiconductor memory elements having a charge storage layer between a semiconductor active layer and a control gate electrode. In particular, the present invention can also be applied to a semiconductor memory element provided with a semiconductor cluster layer, a metal cluster layer, or a nitride film as a charge storage layer. These semiconductor memory elements are characterized in that charge accumulation regions are spatially discretely provided.
[0100]
FIG. 19A shows an example of a cross-sectional view in the channel length direction of a semiconductor memory element using a semiconductor or metal cluster layer as a region for accumulating charges. 19A includes a semiconductor active layer including a channel region 1901 and impurity regions 1902 and 1903 to which an impurity of one conductivity type is added, a first gate insulating film 1904, a substrate 1900, A cluster layer 1906, a second gate insulating film 1907, and a control gate electrode 1908 are sequentially stacked. The cluster layer 1906 is a layer formed of discrete block semiconductors or metals (called clusters), and the discrete clusters 1905 serve as charge trapping centers.
[0101]
Known semiconductor memory elements using a nitride film or the like as a region for accumulating charges include MNOS (Metal Nitride Oxide Semiconductor), MONOS (Metal Oxide Nitride Oxide Semiconductor), and the like. Examples of cross-sectional views in the channel length direction of MNOS and MONOS type semiconductor memory elements are shown in FIGS. 19B and 19C, respectively. In the semiconductor memory element shown in FIG. 19B, a semiconductor active layer including a channel region 1911 and impurity regions 1912 and 1913 to which an impurity of one conductivity type is added, a first gate insulating film 1914, a nitride, and a substrate 1910. A film 1915 and a control gate electrode 1916 are sequentially stacked. In the semiconductor memory element shown in FIG. 19C, a semiconductor active layer including a channel region 1921 and impurity regions 1922 and 1923 doped with one conductivity type impurity on a substrate 1920, a first gate insulating film 1924. The nitride film 1925, the second gate insulating film 1926, and the control gate electrode 1927 are sequentially stacked. In any case, spatially discrete impurity levels in the nitride film serve as charge trapping centers.
[0102]
When the present invention is applied to the semiconductor memory element described above, it is formed as a linear recess having an insulating surface as a channel region, the side surface is completely covered by the recess side wall, and includes crystal grain boundaries other than twins. A crystalline semiconductor film having a substantially uniform crystal orientation may be used.
[0103]
When a charge storage layer in which charge storage regions are discretely provided is used as a semiconductor memory element, there is an effect that the charge retention characteristics are not easily affected by defects in the first gate insulating film or pinholes. In the case where a region for accumulating charges is continuously provided as in a semiconductor memory element having a floating gate electrode, if there is even a pinhole in the first gate insulating film, it is accumulated in the floating gate electrode. All the charges leaked from the pinholes greatly affect the charge retention characteristics of the semiconductor memory element. However, when a semiconductor memory element in which charge accumulation regions are provided discretely is used, the region affected by the pinhole is limited, and many charge accumulation regions are not affected by the pinhole. Therefore, the influence on the charge retention characteristics of the semiconductor memory element is small.
[0104]
(Example 2)
In the formation of the crystalline semiconductor film in the present invention, in addition to the method of crystallizing an amorphous semiconductor film by irradiating the amorphous semiconductor film with laser as shown in Embodiment Mode 2, laser light is further emitted after crystallization by solid phase growth. It may be melted and recrystallized by irradiation.
[0105]
For example, after forming the amorphous semiconductor film 401 in FIG. 4, a catalyst that promotes crystallization, such as lowering the crystallization temperature of the amorphous semiconductor film (for example, amorphous silicon film) to improve the orientation. Ni is added as an active metal element. There is no limitation on the method of adding Ni, and a spin coating method, a vapor deposition method, a sputtering method, or the like can be applied. In the case of the spin coating method, an aqueous solution containing 5 ppm of nickel acetate is applied to form a metal element-containing layer. Of course, the catalyst element is not limited to Ni, and other known materials may be used.
[0106]
Thereafter, the amorphous semiconductor film 401 is crystallized by heat treatment at 580 ° C. for 4 hours. This crystallized semiconductor film is melted and recrystallized by irradiating it with laser light or strong light equivalent thereto. Thus, a crystalline semiconductor film 501 having a substantially flat surface can be obtained as in FIG. Similarly, the crystalline semiconductor film 501 has a growth edge and a crystal grain boundary formed on the second insulating film 304.
[0107]
The advantage of using a crystallized semiconductor film as an object to be irradiated with laser light is the variation rate of the light absorption coefficient of the semiconductor film. Even if the crystallized semiconductor film is irradiated with laser light and melted, the light absorption coefficient is almost Does not fluctuate. Therefore, a wide margin of laser irradiation conditions can be taken.
[0108]
A metal element remains in the crystalline semiconductor film thus formed, but can be removed by gettering treatment. For details of this technique, refer to Japanese Patent Application No. 2001-019367 (or Japanese Patent Application No. 2002-020801). Further, the heat treatment accompanying the gettering treatment has an effect of alleviating distortion of the crystalline semiconductor film.
[0109]
Thereafter, the recessed crystalline semiconductor film is extracted as in the second embodiment. The extracted crystalline semiconductor film has the characteristics that it does not include crystal grain boundaries other than twins and the crystal orientation is almost uniform, and the side surface is at least a portion that becomes a channel region of a semiconductor memory element. It is covered by the side wall of the recess. Then, a semiconductor memory element and a TFT can be manufactured using this crystalline semiconductor.
[0110]
Note that this embodiment can also be applied to the semiconductor memory element described in Embodiment 1.
[0111]
(Example 3)
In this embodiment, an example of a configuration of a laser processing apparatus that can be applied in crystallization is shown.
[0112]
FIG. 20 shows laser oscillation devices 2001a and 2001b, shutters 2002, high conversion mirrors 2003 to 2006, cylindrical lenses 2008 and 2009, slit 2007, mounting table 2011, and driving means 2012 and 2013 for displacing the mounting table 2011 in the X and Y directions. A front view and a side view of the configuration of a laser processing apparatus including a control means 2014 for controlling the driving means, an information processing means 2015 for sending a signal to the laser oscillation apparatus 2001 and a control means 2014 based on a program stored in advance, and the like. It is shown by the figure.
[0113]
As the laser oscillation device, a rectangular beam solid-state laser oscillation device is applied, and a slab laser oscillation device is particularly preferably applied. Or YAG, YVO _Four , YLF, YAlO _Three A slab structure amplifier may be combined with a solid-state laser oscillation device using a crystal doped with Nd, Tm, or Ho. Crystals such as Nd: YAG, Nd: GGG (gadolinium / gallium / garnet), Nd: GsGG (gadolinium / scandium / gallium / garnet) are used as the slab material. In addition, a gas laser oscillation device and a solid laser oscillation device capable of continuous oscillation can also be applied. As continuous wave solid state laser oscillators, YAG, YVO _Four , YLF, YAlO _Three A laser oscillation device using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is applied. The fundamental wave of the oscillation wavelength varies depending on the material to be doped, but oscillates at a wavelength of 1 μm to 2 μm. In order to obtain a higher output of 5 W or more, diode-pumped solid state laser oscillation devices may be cascaded.
[0114]
Circular or rectangular laser light output from such a laser oscillation device is condensed linearly in the cross-sectional shape of the irradiated surface by the cylindrical lenses 2008 and 2009. Further, in order to prevent interference on the irradiation surface, the high conversion mirror is appropriately adjusted so that the incident light is incident from an oblique direction with an angle of 10 to 80 degrees. If the cylindrical lenses 2008 and 2009 are made of synthetic quartz, a high transmittance can be obtained, and the coating applied to the surface of the lens is applied in order to realize a transmittance of 99% or more with respect to the wavelength of the laser beam. Of course, the cross-sectional shape of the irradiation surface is not limited to a linear shape, and may be an arbitrary shape such as a rectangular shape, an elliptical shape, or an oval shape. In any case, the ratio between the short axis and the long axis is within the range of 1 to 10 to 1 to 100. Further, the wavelength conversion element 2010 is provided to obtain harmonics with respect to the fundamental wave.
[0115]
In addition, the substrate 2020 can be subjected to laser processing by moving the mounting table 2011 in the biaxial direction by the driving units 2012 and 2013. The movement in one direction can be continuously performed at a constant speed of 1 to 200 cm / sec, preferably 5 to 50 cm / sec, over a distance longer than the length of one side of the substrate 2020, and the other is a line. It is possible to discontinuously step the distance as much as the longitudinal direction of the beam. The oscillation of the laser oscillation devices 2001a and 2001b and the mounting table 2011 are operated in synchronization by the information processing means 2015 equipped with a microprocessor.
[0116]
The mounting table 2011 linearly moves in the X direction shown in the drawing, so that the entire surface of the substrate can be processed with laser light emitted from a fixed optical system. The position detection unit 2016 detects that the substrate 2020 is at the irradiation position of the laser beam, transmits the signal to the information processing unit 2015, and the information processing unit 2015 determines the timing of the oscillation operations of the laser oscillation devices 2001a and 2001b. Synchronized. In other words, when the substrate 2020 is not at the laser light irradiation position, the laser oscillation is stopped and the lifetime is extended.
[0117]
The laser light irradiated to the substrate 2020 by the laser irradiation apparatus having such a structure can process a desired region or the entire surface of the semiconductor film by relatively moving in the X direction or the Y direction shown in the drawing.
[0118]
This embodiment can be freely combined with any of the configurations of the first and second embodiments.
[0119]
Example 4
In Embodiments 2 to 3, the case where the crystalline semiconductor film is formed over the base insulating film having the stripe-shaped recesses has been described. The present invention does not have to be a complete stripe pattern, but is characterized in that at least a crystalline semiconductor film constituting a semiconductor memory element and a channel region of a TFT is formed by a linear recess. For example, a wiring region using a source / drain region or a semiconductor film may use a crystalline semiconductor film formed by recesses between stripes connecting linear recesses. Such a crystalline semiconductor film may contain crystal grain boundaries and crystal defects, but this is not a problem when used as a source / drain region or a semiconductor film wiring.
[0120]
In this embodiment, a process for manufacturing a semiconductor memory element and a TFT using a base insulating film provided with an inter-stripe recess that connects between stripe-shaped recesses in accordance with a source / drain region or a wiring region using a semiconductor film. explain. Only the differences from the third embodiment will be described in detail with reference to FIGS. 15 and 16.
[0121]
FIG. 15 shows a state in which the first insulating film 1501 and the second insulating film 1502 for forming the stripe-shaped recesses and the recesses between the stripes are formed. A region 1503 surrounded by a dotted line in the drawing is a part to be a source wiring in the memory cell array, and a recess is provided in accordance with the region to be the source wiring. In addition, regions 1504 to 1507 surrounded by dotted lines in the figure are portions that become source / drain regions of the TFT.
[0122]
Next, an amorphous semiconductor film is deposited thereon, and a crystalline semiconductor film is formed by irradiating it with a linearly focused laser beam, and then the crystalline semiconductor film over the second insulating film 1502 is formed. The crystalline semiconductor film is extracted so as to be removed by etching and filling the recess. In FIG. 16, the crystalline semiconductor film is further etched to form island-shaped semiconductor films 1601, 1602, and 1603 in accordance with the arrangement of the semiconductor film and the semiconductor film wiring constituting the semiconductor memory element and TFT. Shows the state.
[0123]
Then, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are formed in accordance with the arrangement of the semiconductor memory elements, and a gate insulating film and a gate electrode are formed in accordance with the arrangement of the TFTs. Thereafter, an n-type or p-type impurity region is formed, and various wirings are formed through an interlayer insulating film, whereby a memory cell array and a peripheral circuit can be manufactured simultaneously as in the third embodiment.
[0124]
As described above, by providing the base insulating film with recesses corresponding to the wiring regions using the source / drain regions and the semiconductor film, the wiring regions using the source / drain regions and the semiconductor film described in the third embodiment are formed. A mask to be covered becomes unnecessary, and the number of masks necessary for manufacturing a semiconductor memory device can be reduced by one.
[0125]
In addition, a present Example can be freely combined with any structure of Examples 1-3.
[0126]
(Example 5)
In this embodiment, another method for simultaneously manufacturing a memory cell array and a peripheral circuit will be described. The semiconductor memory element of the present invention is characterized in that the side surface of the crystalline semiconductor film constituting the channel region is covered with the side wall of the recess, but the peripheral circuit such as a decoder circuit or a write / read circuit for selecting a memory cell The TFTs on the same substrate constituting other semiconductor integrated circuits do not have to have such a structure.
[0127]
In particular, not only the top surface of the crystalline semiconductor film but also the side surface portion is channeled by removing the recess side walls covering the side surfaces of the crystalline semiconductor film constituting the channel region of the TFT constituting the peripheral circuit and other semiconductor integrated circuits. A structure having a region and a TFT with high current driving capability can be realized.
[0128]
Only the differences from the third embodiment will be described in detail with reference to FIGS. 17 and 18.
[0129]
FIG. 17 shows a state in which the second insulating film is removed by an etching process in a state where the region where the semiconductor memory element is arranged (right half in the drawing) is masked with a photoresist after being manufactured up to FIG. 11 according to the third embodiment. Is shown. This etching process is a chemical process using buffered hydrofluoric acid, or CHF. _Three It can be performed by dry etching using
[0130]
By this step, as shown in FIG. 17, the side surface portions and the upper surface portions of the island-shaped semiconductor films 1701 and 1702 that become the channel regions of the TFTs are exposed. By forming a gate in this portion, the side surface portion and the upper surface portion of the island-shaped semiconductor films 1701 and 1702 can be channel formation regions.
[0131]
In this embodiment, the etching is performed up to the first insulating film, but the etching may be stopped in the middle of the second insulating film. By adjusting the etching depth, the depth of the channel formation region of the island-shaped semiconductor films 1701 and 1702 can be adjusted. That is, a crystallization region can be selected.
[0132]
Then, as shown in FIG. 18, the first gate insulating film, the floating gate electrode, the second gate insulating film, and the control gate electrode are superimposed on the upper surface portion of the crystalline semiconductor film in accordance with the arrangement of the semiconductor memory elements. A gate insulating film and a gate electrode are formed so as to overlap with the side surface portion and the upper surface portion of the crystalline semiconductor film in accordance with the arrangement of the TFT.
[0133]
Thereafter, an n-type or p-type impurity region is formed, and various wirings are formed through an interlayer insulating film, whereby a memory cell array and a peripheral circuit can be manufactured simultaneously as in the third embodiment.
[0134]
With such a configuration, in the semiconductor memory element, the side surface of the crystalline semiconductor film constituting the channel region is covered with the side wall of the recess, and the charge is injected into and released from the floating gate electrode at the end of the active layer. High reliability can be realized by adopting a structure that does not concentrate the electric field. In the TFT constituting the peripheral circuit, a channel is formed on the side surface and the top surface of the crystalline semiconductor film, effectively increasing the channel width. By doing so, the current drive capability can be improved.
[0135]
In addition, a present Example can be freely combined with any structure of Examples 1-4.
[0136]
(Example 6)
As an example of the semiconductor memory device of the present invention, a case where a nonvolatile memory is applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip will be described.
[0137]
FIG. 22 shows an example of a microprocessor. The microprocessor typically includes a CPU core 2201, a flash memory 2204, a clock controller 2203, a cache memory 2202, a cache controller 2205, an interrupt controller 2206, an I / O port 2207, and the like. Needless to say, the microprocessor illustrated in FIG. 22 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on the application.
[0138]
The microprocessor illustrated in FIG. 22 is manufactured by the manufacturing method described in the embodiment or the example, and a crystalline silicon film is formed over a base insulating film having a recess, and a channel formation region is formed in the filling region filled in the recess. The semiconductor memory element and the TFT are provided. The flash memory 2204 uses the semiconductor memory element of the present invention. For example, an SRAM is used as the cache memory.
[0139]
Thus, by applying the present invention to a microprocessor, a semiconductor memory device having a highly reliable nonvolatile memory and capable of operating at high speed can be realized. Although the operation speed depends on the design rule and the like, a read cycle of the flash memory of 500 nsec or less and a CPU operation frequency of 5 MHz or more are realized.
[0140]
Note that this example can be combined with any of the configurations of the embodiment and Examples 1 to 5.
[0141]
(Example 7)
In this embodiment, an image display unit (typically a liquid crystal display unit or an EL display unit), a nonvolatile memory, and another semiconductor integrated circuit are integrally formed on a substrate having an insulating surface. An example of a semiconductor memory device taking the above will be described with reference to FIG.
[0142]
23, the semiconductor memory device includes a pixel region 2300, a scanning line driver circuit 2301, a signal line driver circuit 2302, a VRAM 2303, a flash memory 2304, a CPU 2305, an image processing circuit 2306, a work memory 2307, and an interface circuit 2308 having an insulating surface. The substrate 2310 is integrally formed.
[0143]
The semiconductor memory device shown in FIG. 23 is a device that captures or creates image data, processes the image data, converts the format, and displays an image. As the semiconductor memory device, for example, a video camera, a car navigation system, a personal computer, a game machine, etc. can be considered.
[0144]
The semiconductor memory device receives data serving as a basis of image data from an input terminal in accordance with each form. For example, it is input data from an antenna in a broadcast receiver, and input data from a CCD in a video camera. It may be input data from a DV tape or a memory card. In addition to this, an input signal from the keyboard or another control signal may be input from the input terminal. The data that is the basis of the input image is stored in the flash memory 2304, temporarily stored in the work memory 2307 via the interface circuit 2308 and the system bus, or is converted into an image signal by the image processing circuit 2306. Converted and stored in VRAM. The image processing circuit 2306 performs image signal processing such as decoding processing of image data compression-encoded according to the MPEG standard, tape format, etc., image interpolation and resizing. The input control signal is used for communication with the CPU and the image processing circuit, and is also input to the signal line driving circuit and the running line driving circuit.
[0145]
The CPU 2305 controls the flash memory 2304, the work memory 2307, the interface circuit 2308, and other circuits. In addition, data that is the basis of image data is created or processed. The flash memory 2304 is used as a memory area for storing color data and character data necessary for creating or processing image data, or a memory area for storing program data. The work memory 2307 is used as a memory area for storing image data and its base data, a work memory area for control by the CPU, and a DRAM or SRAM is used.
[0146]
An image display portion including the signal line driver circuit 2302, the scanning line driver circuit 2301, and the pixel area 2300 is an area for displaying an image. A control signal is input to the signal line driver circuit 2302 and the scanning line driver circuit 2301 from the outside via an interface circuit. The signal line driver circuit 2302 outputs an image output from the image processing circuit 2306 and stored in the VRAM in accordance with the control signal. Data is captured and an image is displayed in the pixel area.
[0147]
As described above, a semiconductor memory device having a nonvolatile memory that captures or produces image data and displays an image is configured. The semiconductor memory device illustrated in FIG. 23 is manufactured by the manufacturing method described in the embodiment or the example, and a crystalline silicon film is formed over a base insulating film having a recess, and a channel is formed in a filling region filled in the recess. The semiconductor memory element and the TFT in which the region is disposed are configured. The flash memory 2304 uses the semiconductor memory element of the present invention.
[0148]
Thus, by applying the present invention to a semiconductor memory device, a semiconductor memory device having a highly reliable nonvolatile memory and capable of operating at high speed can be realized. In addition, by integrally forming, there are effects such as downsizing and reduction of power consumption.
[0149]
Note that the image display portion including the signal line driver circuit 2302, the scanning line driver circuit 2301, and the pixel region 2300 and the image processing portion including other circuits may be manufactured over different substrates. As the semiconductor memory device, a form such as a broadcast receiver or a game machine having no display unit can be configured with a substrate constituting the image processing unit. Of course, the above-described semiconductor memory device may be realized by mounting a plurality of substrates.
[0150]
This embodiment can be used in combination with the first to fifth embodiments.
[0151]
(Example 8)
Various devices can be completed using the present invention. Examples thereof include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, television receivers, projection display devices, and the like. An example of them is shown in FIG.
[0152]
FIG. 24A illustrates an example in which a television receiver is completed by applying the present invention, which includes a housing 2401, a support base 2402, a display portion 2403, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a television receiver having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0153]
FIG. 24B shows an example in which the present invention is applied to complete a video camera, which includes a main body 2411, a display portion 2412, an audio input portion 2413, operation switches 2414, a battery 2415, an image receiving portion 2416, and the like. . By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a video camera having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0154]
FIG. 24C illustrates an example in which a laptop personal computer is completed by applying the present invention, which includes a main body 2421, a housing 2422, a display portion 2423, a keyboard 2424, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a personal computer having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0155]
FIG. 24D is an example in which a PDA (Personal Digital Assistant) is completed by applying the present invention, and includes a main body 2431, a stylus 2432, a display portion 2433, operation buttons 2434, an external interface 2435, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a PDA having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0156]
FIG. 24E is an example in which a sound reproducing device is completed by applying the present invention, specifically, an in-vehicle audio device, which includes a main body 2441, a display portion 2442, operation switches 2443, 2444, and the like. Has been. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, an audio device having a highly reliable non-volatile memory and a high operation speed can be completed.
[0157]
FIG. 24F illustrates an example in which the present invention is applied to complete a digital camera. A main body 2451, a display portion (A) 2452, an eyepiece portion 2453, an operation switch 2454, a display portion (B) 2455, a battery 2456, and the like. Etc. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a digital camera having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0158]
FIG. 24G illustrates an example of a cellular phone completed by applying the present invention, which includes a main body 2461, an audio output portion 2462, an audio input portion 2463, a display portion 2464, operation switches 2465, an antenna 2466, and the like. Yes. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a mobile phone having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0159]
In addition, the apparatus shown here is only an example and is not limited to these uses.
[0160]
This embodiment can be used in combination with the first to fifth embodiments.
[0161]
【The invention's effect】
According to the present invention, it is possible to manufacture a crystalline semiconductor film in which a side surface is covered with a recess side wall at a portion where a channel region of a semiconductor memory element is formed.
[0162]
As a result, local deterioration of the first gate insulating film due to electric field concentration at the edge of the semiconductor active layer can be suppressed, and a highly reliable semiconductor memory element can be realized.
[0163]
According to the present invention, it is possible to simultaneously concentrate strain or stress associated with crystallization in a region other than a recess, and to manufacture a high-quality crystalline semiconductor film that does not include a crystal grain boundary other than twins in the recess. Become.
[0164]
In this manner, by controlling the crystallinity of the channel region and increasing the crystallinity of the channel region, it is possible to manufacture a semiconductor memory element and a TFT with high field effect mobility and small characteristic variation.
[0165]
By forming the memory cell and the peripheral circuit at the same time using the semiconductor memory element and the TFT described above, a semiconductor memory device with high reliability and capable of operating at high speed can be realized.
[Brief description of the drawings]
1A and 1B are a top view and a cross-sectional view of a semiconductor memory element of the present invention.
2A and 2B are a top view and a cross-sectional view of a conventional semiconductor memory element.
FIG. 3 is a perspective view illustrating a crystallization method of the present invention.
FIG. 4 is a perspective view illustrating a crystallization method of the present invention.
FIG. 5 is a perspective view illustrating a crystallization method according to the present invention.
FIG. 6 is a perspective view illustrating a crystallization method of the present invention.
FIG. 7 is a block circuit diagram of a NOR type nonvolatile memory.
8A to 8C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
9A to 9C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
10A to 10C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
11A to 11C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
12A to 12C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
13A to 13C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
14A to 14C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
15A to 15C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
16A to 16C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
17A to 17C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
18A to 18C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
FIG. 19 is a cross-sectional view of a semiconductor memory element to which the present invention is applied.
FIG. 20 is a layout view illustrating one embodiment of a laser irradiation apparatus applied to the present invention.
FIG. 21 is a diagram for explaining a linearly focused laser beam and its scanning direction in the present invention.
FIG 22 illustrates an example of a microprocessor.
FIG. 23 illustrates an example of a semiconductor memory device.
FIG 24 illustrates an example of a semiconductor memory device.
FIG. 25 is a scanning electron microscope (SEM) photograph (after seco etching) showing a surface state when an amorphous silicon film having a thickness of 150 nm is formed and crystallized on a base insulating film provided with stripe-shaped recesses.
FIG. 26 is EBSP mapping data showing the orientation of crystals formed in the recesses.
FIG. 27 is a cross-sectional transmission electron microscope (TEM) photograph of a crystal formed in a recess.
FIG. 28 is a sketch of the scanning electron microscope (SEM) photograph shown in FIG. 25.

Claims (8)

Forming an insulating film so that a linear recess is formed on a substrate having an insulating surface;
Forming a semiconductor film in a region including the linear recess,
Melting and crystallizing the semiconductor film to form a crystalline semiconductor film;
The surface of the crystalline semiconductor film is etched away so that the side surface of the crystalline semiconductor film is covered on the side wall of the linear concave portion,
Forming a first gate insulating film in contact with an upper surface portion of the etched crystalline semiconductor film;
Charge storage layer is laminated on the first gate insulating film, forming a second gate insulating film, and a control gate electrode,
The method for manufacturing a semiconductor memory element, wherein the crystalline semiconductor film after the etching does not include crystal grain boundaries other than twins . Forming an insulating film so that a linear recess is formed on a substrate having an insulating surface;
Forming a semiconductor film in a region including the linear recess,
By irradiating the semiconductor film with a laser beam and scanning the laser beam in the linear direction of the recess, the semiconductor film is melted and crystallized to form a crystalline semiconductor film,
The surface of the crystalline semiconductor film is etched away so that the side surface of the crystalline semiconductor film is covered on the side wall of the linear concave portion,
Forming a first gate insulating film in contact with an upper surface portion of the etched crystalline semiconductor film;
Charge storage layer is laminated on the first gate insulating film, forming a second gate insulating film, and a control gate electrode,
The method for manufacturing a semiconductor memory element, wherein the crystalline semiconductor film after the etching does not include crystal grain boundaries other than twins . Forming a first insulating film over a substrate having an insulating surface;
Forming a plurality of second insulating films on the first insulating film such that a linear recess is provided between two adjacent second insulating films;
Forming a semiconductor film in a region including the linear recess,
Melting and crystallizing the semiconductor film to form a crystalline semiconductor film;
The surface of the crystalline semiconductor film is etched away so that the side surface of the crystalline semiconductor film is covered on the side wall of the linear concave portion,
Forming a first gate insulating film in contact with an upper surface portion of the etched crystalline semiconductor film;
Charge storage layer is laminated on the first gate insulating film, forming a second gate insulating film, and a control gate electrode,
The method for manufacturing a semiconductor memory element, wherein the crystalline semiconductor film after the etching does not include crystal grain boundaries other than twins . Forming a first insulating film over a substrate having an insulating surface;
Forming a plurality of second insulating films on the first insulating film such that a linear recess is provided between two adjacent second insulating films;
Forming a semiconductor film in a region including the linear recess,
By irradiating the semiconductor film with a laser beam and scanning the laser beam in the linear direction of the recess, the semiconductor film is melted and crystallized to form a crystalline semiconductor film,
The surface of the crystalline semiconductor film is etched away so that the side surface of the crystalline semiconductor film is covered on the side wall of the linear concave portion,
Forming a first gate insulating film in contact with an upper surface portion of the etched crystalline semiconductor film;
Charge storage layer is laminated on the first gate insulating film, forming a second gate insulating film, and a control gate electrode,
The method for manufacturing a semiconductor memory element, wherein the crystalline semiconductor film after the etching does not include crystal grain boundaries other than twins . The method for manufacturing a semiconductor memory element according to claim 2, wherein the laser beam is a continuous wave laser beam. 6. The etching according to claim 1, wherein the etching is performed such that a thickness of the crystalline semiconductor film in the linear recess is equal to or less than a depth of the linear recess. The manufacturing method of the semiconductor memory element of description. 7. The semiconductor film according to claim 1, wherein the semiconductor film is formed of any one of silicon, a compound or alloy of silicon and germanium, or a compound or alloy of silicon and carbon. The manufacturing method of the semiconductor memory element of description. The method for manufacturing a semiconductor memory element according to claim 1, wherein the charge storage layer is a floating gate electrode.

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