JP4141292B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element formed using a semiconductor film having a crystal structure, a manufacturing method thereof, a semiconductor device including a circuit in which the semiconductor element is integrated, and a manufacturing method thereof. In particular, the present invention relates to a field effect transistor (typically a thin film transistor) in which a channel formation region is formed using a crystalline semiconductor film formed over an insulating surface as a semiconductor element, a thin film diode using the crystalline semiconductor film, and the like.
[0002]
[Prior art]
A technique for forming an amorphous silicon film on an insulating substrate made of glass or the like and crystallizing the film to form a semiconductor element such as a transistor has been developed. In particular, a technique for crystallizing an amorphous silicon film by irradiating a laser beam is applied to a manufacturing technique of a thin film transistor (TFT). A transistor manufactured using a semiconductor film having a crystal structure (crystalline semiconductor film) is applied to a flat display device (flat panel display) typified by a liquid crystal display device.
[0003]
Applications of laser light in semiconductor manufacturing processes include technologies for recrystallizing damaged layers and amorphous layers formed on semiconductor substrates or semiconductor films, and technologies for crystallizing amorphous semiconductor films formed on insulating surfaces. Has been deployed. As a laser oscillation device to be applied, a gas laser typified by an excimer laser or a solid-state laser typified by a YAG laser is usually used.
[0004]
As an example of crystallization of an amorphous semiconductor film by laser light irradiation, the scanning speed of the laser light is set to a beam spot diameter × 5000 / second or more, and the amorphous semiconductor film is brought into a completely molten state by high-speed scanning. Without being polycrystallized (for example, refer to Patent Document 1), a technique for substantially forming a single crystal region by irradiating a semiconductor film formed in an island shape with an extended laser beam (for example, Patent Document 2) is disclosed. Or the method of processing and irradiating a beam linearly with an optical system like a laser processing apparatus is known (for example, refer patent document 3).
[0005]
[Patent Document 1]
JP 62-104117 A
[Patent Document 2]
U.S. Pat. No. 4,330,363
[Patent Document 3]
JP-A-8-195357
[0006]
Furthermore, Nd: YVO _Four Using a solid-state laser oscillation device such as a laser, the amorphous semiconductor film is irradiated with laser light, which is the second harmonic, to form a crystalline semiconductor film having a larger crystal grain size than before, and a transistor is manufactured. A technique is disclosed (for example, see Patent Document 4).
[0007]
[Patent Document 4]
JP 2001-144027 A
[0008]
[Problems to be solved by the invention]
However, when an amorphous semiconductor film formed on a flat surface is crystallized by irradiating it with laser light, the crystal becomes polycrystals, and defects such as crystal grain boundaries are arbitrarily formed to align crystals with uniform orientation. Couldn't get.
[0009]
The crystal grain boundary contains crystal defects, which become carrier traps and cause the mobility of electrons or holes to decrease. In addition, a semiconductor film free from strain or crystal defects could not be formed due to volume shrinkage of the semiconductor film accompanying crystallization, thermal stress with the base, or lattice mismatch. Therefore, without a special method such as bonding SOI (Silicon on Insulator), it is equivalent to a MOS transistor formed on a single crystal substrate with a crystalline semiconductor film formed on an insulating surface and crystallized or recrystallized. Could not get the quality.
[0010]
The above-described flat display device or the like forms a transistor by forming a semiconductor film on a glass substrate, but it is almost impossible to arrange the transistor so as to avoid an arbitrarily formed crystal grain boundary. . In other words, the crystallinity of the channel formation region of the transistor is strictly controlled, and the grain boundaries and crystal defects that are included unintentionally cannot be excluded. As a result, not only the electrical characteristics of the transistors are inferior, but also the characteristics of individual elements vary.
[0011]
In particular, when a crystalline semiconductor film is formed using laser light on an alkali-free glass substrate that is widely used in industry, the focus of the laser light varies due to the influence of the undulation of the alkali-free glass substrate itself. However, there is a problem that the crystallinity varies. Furthermore, in order to avoid contamination with alkali metals, an alkali-free glass substrate needs to be provided with a protective film such as an insulating film as a base film, and a crystalline semiconductor film from which crystal grain boundaries and crystal defects have been eliminated is large. It was almost impossible to form with a particle size.
[0012]
The present invention has been made in view of the above problems, and a crystalline semiconductor film having no crystal grain boundary at least in a channel formation region is formed on an insulating surface, particularly on an insulating surface using a glass substrate as a supporting base, An object of the present invention is to provide a semiconductor device including a semiconductor element or a group of semiconductor elements that can operate at high speed, has high current driving capability, and has little variation among a plurality of elements.
[0013]
Furthermore, the present invention provides a semiconductor device in which a capacitor element (capacitor) capable of holding charges at a high density is formed on the same substrate with a small occupation area simultaneously with the fabrication of the semiconductor element, and the semiconductor element and the capacitor element are combined. The purpose is to provide.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention forms an insulating film provided with concave and convex portions extending in a linear stripe pattern on a substrate having an insulating surface, and the amorphous film is formed on the insulating film. A semiconductor film is formed, a crystalline semiconductor film is formed by melting and pouring the semiconductor film into a portion corresponding to a concave portion of the insulating film (hereinafter simply referred to as a concave portion), and crystallizing an unnecessary region. A crystalline semiconductor film in which a crystalline semiconductor film divided into islands from a crystalline semiconductor film (which will later become a part of a semiconductor element) is formed, and at least a portion for forming a channel formation region is formed in the above-described recess. A gate insulating film and a gate electrode are provided over the crystalline semiconductor film so as to be (hereinafter referred to as a first crystalline semiconductor region).
[0015]
Of the insulating film provided with a portion corresponding to the concave portion or the convex portion (hereinafter simply referred to as a convex portion), a crystalline semiconductor film (hereinafter referred to as a second crystalline semiconductor region) formed on the convex portion. .) Is inferior to the crystalline semiconductor film formed in the concave portion. However, in the present invention, the crystalline semiconductor film formed on the convex portion is positively formed in a conductive region (if it is a thin film transistor). It corresponds to a source region or a drain region.) Or a wiring. When used as a wiring, since the degree of freedom in designing the occupied area is high, the wiring length can be adjusted to be used as a resistor, or a bent shape can be provided as a protective circuit function.
[0016]
The aforementioned recess may be formed by directly etching the surface of the insulating substrate, or a recess may be formed by etching a silicon oxide, silicon nitride, or silicon oxynitride film. The recess is preferably formed in accordance with the arrangement of the semiconductor element, particularly the island-shaped semiconductor film including the channel formation region of the transistor, and is preferably formed so as to match at least the channel formation region. The recess is provided so as to extend in the channel length direction. The width of the concave portion (channel width direction in the case of forming a channel formation region) is 0.01 μm or more and 2 μm or less, preferably 0.1 to 1 μm, and the depth is 0.01 μm or more and 3 μm or less, preferably 0. It is formed at 1 μm or more and 2 μm or less.
[0017]
Of course, it is also possible to form an island-shaped insulating film on the insulating surface and positively form a convex portion. In that case, the convex portion extending in a plurality of linear stripe patterns forms a portion that is relatively a concave portion between adjacent ones, so that the concave portion includes an island-shaped semiconductor including a channel formation region of a semiconductor element. What is necessary is just to form according to arrangement | positioning of a film | membrane, and it should just be also settled in the above-mentioned range also about a width | variety.
[0018]
In the first stage, the semiconductor film formed over the insulating film and over the recess is an amorphous semiconductor film or a polycrystalline semiconductor film formed by plasma CVD, sputtering, or low pressure CVD, or a multi-layer formed by solid phase growth. A crystalline semiconductor film or the like is applied. Note that the amorphous semiconductor film referred to in the present invention is not limited to a film having a completely amorphous structure in a narrow sense, but includes a state in which fine crystal particles are included, or a so-called microcrystalline semiconductor film, local Includes a semiconductor film including a crystal structure. Typically, an amorphous silicon film is applied, and in addition, an amorphous silicon germanium film, an amorphous silicon carbide film, or the like can also be applied. The polycrystalline semiconductor film is obtained by crystallizing these amorphous semiconductor films by a known method.
[0019]
As a means for melting and crystallizing the crystalline semiconductor film, pulsed oscillation or continuous oscillation laser light using a gas laser oscillation device or a solid laser oscillation device as a light source is applied. The laser light to be irradiated is focused in a linear shape by an optical system, and the intensity distribution may have a uniform region in the longitudinal direction and may be distributed in the lateral direction. As the oscillation device, a rectangular beam solid laser oscillation device is applied, and a slab laser oscillation device is particularly preferably applied. Alternatively, it is a solid state laser oscillation device using a rod doped with Nd, Tm, and Ho, especially YAG, YVO. _Four , YLF, YAlO _Three A slab structure amplifier may be combined with a solid-state laser oscillation device using a crystal doped with Nd, Tm, or Ho. As the slab material, crystals such as Nd: YAG, Nd: GGG (gadolinium / gallium / garnet), Nd: GsGG (gadolinium / scandium / gallium / garnet) are used. A slab laser travels in a zigzag optical path through this plate-like laser medium while repeating total reflection.
[0020]
Moreover, you may irradiate the strong light according to it. For example, light having a high energy density obtained by condensing light emitted from a halogen lamp, xenon lamp, high-pressure mercury lamp, metal halide lamp, or excimer lamp by a reflecting mirror or a lens may be used.
[0021]
Laser light or strong light condensed in a linear shape and extended in the longitudinal direction irradiates the crystalline semiconductor film, and relatively moves the irradiation position of the laser light and the substrate on which the crystalline semiconductor film is formed, The crystalline semiconductor film is melted by scanning a part or the entire surface of the laser beam, and crystallization or recrystallization is performed through this state. The scanning direction of the laser light is performed along the longitudinal direction of the recess formed in the insulating film and extending in a linear stripe pattern or the channel length direction of the transistor. As a result, the crystal grows along the scanning direction of the laser beam, and the crystal grain boundary can be prevented from crossing the channel length direction.
[0022]
Laser light irradiation is typically from the upper surface side of the semiconductor film, but irradiation from the lower surface side (substrate side), irradiation from the upper surface side oblique direction or lower surface side oblique direction, or upper surface side and lower surface. The irradiation may be performed by any irradiation method (including irradiation from an oblique direction) from both sides.
[0023]
As another configuration, the crystalline semiconductor film is provided over a glass or quartz substrate on a metal layer including one or more kinds selected from W, Mo, Ti, Ta, and Cr, and the crystalline property of the metal layer An insulating layer may be interposed between the semiconductor film and the semiconductor film. Alternatively, a metal layer containing one or more selected from W, Mo, Ti, Ta, and Cr is provided on a glass or quartz substrate, and an insulating layer made of aluminum nitride or aluminum oxynitride is provided on the metal layer. Further, a structure in which a crystalline semiconductor film is provided thereover may be employed. The metal layer formed here can function as a light-shielding film that blocks light incident on the channel formation region, or a specific potential can be applied to control the spread of the fixed charge or the depletion layer. Moreover, the function as a heat sink which dissipates Joule heat can also be provided.
[0024]
By setting the depth of the recesses to be equal to or greater than the thickness of the semiconductor film, the semiconductor film melted by irradiation with laser light or strong light aggregates and solidifies in the recesses due to surface tension. As a result, the thickness of the semiconductor film on the convex portion of the insulating film is reduced, and stress strain can be concentrated there. The side surface of the recess has the effect of defining the crystal orientation to some extent.
[0025]
When the semiconductor film is melted, it is agglomerated in the recesses formed on the insulating surface by surface tension, and the crystal growth from the approximate intersection of the bottom and side surfaces of the recesses concentrates the strain generated by crystallization in the region other than the recesses. Can be made. That is, the crystalline semiconductor region (first crystalline semiconductor region) formed so as to be filled in the concave portion can be released from strain. The crystalline semiconductor region (second crystalline semiconductor region) remaining on the insulating film and containing crystal grain boundaries and crystal defects is a portion other than the channel formation region of the semiconductor element, typically a source region or a drain. Used as a region.
[0026]
Then, after forming a crystalline semiconductor film having no crystal grain boundary in the recess, an active layer (semiconductor layer functioning as a carrier movement path) of the semiconductor element is formed by patterning, and a gate insulating film in contact with the active layer is formed Further, a gate electrode is formed. Thereafter, a field effect transistor can be formed by a known method.
[0027]
According to the present invention, it is possible to designate a semiconductor element such as a transistor, particularly a region where a channel formation region thereof is formed, and form a crystalline semiconductor region where no crystal grain boundary exists in the region. As a result, it is possible to eliminate the factor that the characteristics vary due to inadvertently interposed crystal grain boundaries and crystal defects. In other words, it is possible to form a semiconductor device including a semiconductor element or a group of semiconductor elements that can operate at high speed, have high current driving capability, and have little variation among a plurality of elements.
[0028]
Further, the width of the recess is 0.01 μm or more and 2 μm or less and the depth is 0.01 μm or more and 3 μm or less, which means that a semiconductor region having a high aspect ratio can be formed with a linear stripe pattern. is there. In the present invention, by taking advantage of the characteristics and utilizing a semiconductor region having a high aspect ratio as one electrode of the capacitor element, it becomes possible to increase the effective surface area per unit area of the electrode, and a small occupied area Thus, a capacitor element capable of holding a high density charge can be obtained. That is, the capacitor element included in the semiconductor device of the present invention includes a plurality of first crystalline semiconductor regions provided in parallel, an insulating film covering the plurality of first crystalline semiconductor regions, and the insulating film interposed therebetween. The wiring includes a plurality of wirings facing the first crystalline semiconductor regions.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
Hereinafter, embodiments of manufacturing a thin film transistor using the present invention will be described with reference to the drawings. The perspective view shown in FIG. 1A shows a form in which the first insulating film 102 and the second insulating films 103 to 105 having a linear stripe pattern are formed on the substrate 101. In FIG. 1A, three linear stripe patterns by the second insulating film are shown, but of course the number is not limited.
[0030]
As the substrate, a commercially available non-alkali glass substrate, a quartz substrate, a sapphire substrate, a substrate obtained by coating the surface of a single crystal or polycrystalline semiconductor substrate with an insulating film, or a substrate obtained by coating the surface of a metal substrate with an insulating film can be applied. In order to form a linear stripe pattern with a sub-micron design rule, it is desirable that the unevenness of the substrate surface, the waviness or twist of the substrate be less than the depth of focus of the exposure apparatus (particularly the stepper). Specifically, the waviness or twist of the substrate is 1 μm or less, preferably 0.5 μm or less in one exposure light irradiation region. In this regard, care must be taken particularly when an alkali-free glass is used as the support substrate.
[0031]
The width W1 of the second insulating film formed in the linear stripe pattern is 0.1 to 10 μm (preferably 0.5 to 1 μm), and the distance W2 between the adjacent second insulating films is 0.01 to 2 μm ( Preferably, the thickness d of the second insulating film is 0.01 to 3 μm (preferably 0.1 to 2 μm). Furthermore, the relationship with the film thickness t02 in the concave portion of the amorphous semiconductor film provided so as to cover the second insulating film may be d ≧ t02, but if d is too thick compared to t02, Care must be taken because the crystalline semiconductor film does not remain.
[0032]
The step shape need not be a regular periodic pattern, and may be arranged at different intervals in accordance with the width of the island-shaped semiconductor film. The length L is not particularly limited numerically, and can be formed so as to extend from one end to the other end of the substrate. For example, the length L can be formed so that a channel formation region of a transistor can be formed. It is also possible.
[0033]
The first insulating film 102 may be any material that can ensure a selection ratio with respect to the second insulating film to be formed later. Typically, silicon nitride, silicon oxide, and an acid whose oxygen content is larger than the nitrogen content are used. Silicon nitride (shown as SiOxNy), silicon oxynitride (shown as SiNxOy) whose nitrogen content is larger than oxygen content, aluminum nitride (shown as AlxNy), oxynitride whose oxygen content is larger than nitrogen content A material selected from aluminum (shown as AlOxNy), aluminum oxynitride (shown as AlNxOy) having a nitrogen content larger than the oxygen content, or aluminum oxide is formed to a thickness of 30 to 300 nm. In particular, since an aluminum oxide film can be expected to have a blocking effect on sodium (Na), it is effective as a countermeasure against contamination from a glass substrate.
[0034]
As the silicon oxynitride (SiOxNy) film, a film containing Si at 25 to 35 atomic%, oxygen at 55 to 65 atomic%, nitrogen at 1 to 20 atomic%, and hydrogen at 0.1 to 10 atomic%. Use it. Further, as a silicon oxynitride (SiNxOy) film, a film containing Si of 25 to 35 atomic%, oxygen of 15 to 30 atomic%, nitrogen of 20 to 35 atomic%, and hydrogen of 15 to 25 atomic% may be used. good. As the aluminum oxynitride (AlOxNy) film, a film containing Al at 30 to 40 atomic%, oxygen at 50 to 70 atomic%, and nitrogen at 1 to 20 atomic% may be used. Further, as the aluminum oxynitride (AlNxOy) film, a film containing Al in an amount of 30 to 50 atomic%, oxygen in an amount of 30 to 40 atomic%, and nitrogen in an amount of 10 to 30 atomic% may be used.
[0035]
The second insulating films 103 to 105 may be formed using silicon oxide or silicon oxynitride having a thickness of 10 to 3000 nm, preferably 100 to 2000 nm. Silicon oxide is composed of tetraethyl orthosilicate (TEOS) and O ₂ And can be formed by a plasma CVD method. Silicon nitride oxide film is SiH _Four , NH _Three , N ₂ O or SiH _Four , N ₂ It can be formed by plasma CVD using O as a raw material.
[0036]
As shown in FIG. 1A, in the case of forming a linear stripe pattern with two layers of insulating films, the selectivity between the first insulating film 102 and the second insulating films 103 to 105 in the etching process. It is necessary to have. Actually, it is desirable to appropriately adjust the material and film formation conditions so that the etching rate of the second insulating films 103 to 105 is relatively faster than that of the first insulating film 102. Etching using buffered hydrofluoric acid or CHF _Three Performed by dry etching using And the angle of the side part of the recessed part formed with the 2nd insulating films 103-105 should just be set suitably in the range of 5-120 degree | times, Preferably it is 80-100 degree | times.
[0037]
Note that as the second insulating films 103 to 105, an insulating film formed by a CVD method (typically, a plasma CVD method or a thermal CVD method) or a PVD method (typically, a sputtering method or an evaporation method) is used. It is preferable to use it. This is because, when crystallizing an amorphous semiconductor film, the softness that can relieve the stress associated with crystallization is considered to play an important role in obtaining good crystallinity. is there. The reason will be described later.
[0038]
Next, as shown in FIG. 1B, an amorphous semiconductor film 106 covering the concave portion on the surface composed of the first insulating film 102 and the second insulating films 103 to 105 and 0.01 to 3 μm (preferably 0.1 to 1 μm) in thickness. At this time, it is desirable that the thickness of the amorphous semiconductor film 106 be equal to or greater than the depth of the recess formed by the second insulating films 103 to 105. The amorphous semiconductor film is made of silicon, a compound of silicon and germanium (Si _X Ge _1-X : However, Ge is preferably 0.01 to 2 atomic%. Or an alloy, a compound of silicon and carbon, or an alloy can be applied.
[0039]
As shown in the figure, the amorphous semiconductor film 106 is formed so as to cover the concavo-convex structure formed by the underlying first insulating film 102 and second insulating films 103 to 105. Further, the influence of chemical contamination such as boron adhering to the surfaces of the first insulating film 102 and the second insulating films 103 to 105 is eliminated, and the insulating surface and the amorphous semiconductor film are not in direct contact with each other. Immediately before the crystalline semiconductor film 106 is formed, a silicon oxynitride film may be continuously formed as a third insulating film (not shown) without being exposed to the atmosphere in the same film forming apparatus. The film thickness of the third insulating film is intended to eliminate the influence of the above-mentioned chemical contamination and improve adhesion, and even a thin film is sufficiently effective. Typically, the thickness may be 5 to 50 nm (20 nm or more is preferable for enhancing the chemical contamination blocking effect).
[0040]
Then, the amorphous semiconductor film 106 is instantaneously melted and crystallized. In this crystallization, laser light or radiated light from a lamp light source is condensed and irradiated with an optical system to an energy density that melts the semiconductor film. In this step, it is particularly preferable to apply laser light using a continuous wave laser oscillation device as a light source. The applied laser beam is linearly collected by the optical system and expanded in the long direction, and its intensity distribution has a uniform region in the long direction, It is desirable to have a certain distribution in the short direction.
[0041]
Note that, at the time of crystallization, it is preferable that a position where a marker used for patterning mask alignment is formed after the end of the substrate is not crystallized. This is because a crystalline semiconductor film (especially a crystalline silicon film) has a higher visible light transmittance when crystallized, so that it is difficult to identify it as a marker. However, there is no problem when performing the type of alignment control for optically identifying the difference in contrast due to the level difference of the marker.
[0042]
As the laser oscillation device, a rectangular beam solid-state laser oscillation device is applied, and a slab laser oscillation device is particularly preferably applied. As the slab material, crystals such as Nd: YAG, Nd: GGG (gadolinium / gallium / garnet), Nd: GsGG (gadolinium / scandium / gallium / garnet) are used. A slab laser travels in a zigzag optical path through this plate-like laser medium while repeating total reflection. Alternatively, it is a solid state laser oscillation device using a rod doped with Nd, Tm, and Ho, especially YAG, YVO. _Four , YLF, YAlO _Three A slab structure amplifier may be combined with a solid-state laser oscillation device using a crystal doped with Nd, Tm, or Ho.
[0043]
Then, as indicated by an arrow in FIG. 2A, the second insulating film 103 in which the long direction of the linear laser light irradiation region 100 (X-axis direction in the drawing) is a linear stripe pattern. A linear laser beam or strong light is scanned so as to cross each of .about.105. Here, the term “linear” means that the ratio of the length in the long direction (X-axis direction) to the length in the short direction (Y-axis direction in the figure) is 1 to 10 or more. Say with things. In addition, although only a part is illustrated in FIG. 2A, the end portion of the irradiation region 100 of the linear laser light may be a rectangular shape or a curved shape.
[0044]
The wavelength of the continuous wave laser beam is preferably 400 to 700 nm in consideration of the light absorption coefficient of the amorphous semiconductor film. Light in such a wavelength band is obtained by taking out the second harmonic and the third harmonic of the fundamental wave using a wavelength conversion element. As wavelength conversion element, ADP (ammonium dihydrogen phosphate), Ba ₂ NaNb _Five O ₁₅ (Sodium barium niobate), CdSe (selenium cadmium), KDP (potassium dihydrogen phosphate), LiNbO _Three (Lithium niobate), Se, Te, LBO, BBO, KB5 and the like are applied. It is particularly desirable to use LBO. A typical example is Nd: YVO _Four The second harmonic (532 nm) of the laser oscillation device (fundamental wave 1064 nm) is used. The laser oscillation mode is TEM ₀₀ Apply single mode.
[0045]
In the case of silicon selected as the most suitable material, the absorption coefficient is 10 ^Three -10 ^Four cm ^-1 The region which is is almost in the visible light region. When crystallizing a substrate having a high visible light transmittance such as glass and an amorphous semiconductor film formed with a thickness of 30 to 200 nm using silicon, by irradiating light in the visible light region with a wavelength of 400 to 700 nm, Crystallization can be performed without selectively damaging the base insulating film by selectively heating the semiconductor film. Specifically, the penetration length of light having a wavelength of 532 nm is approximately 100 nm to 1000 nm with respect to the amorphous silicon film, and can sufficiently reach the inside of the amorphous semiconductor film 106 formed with a film thickness of 30 nm to 200 nm. it can. That is, it is possible to heat from the inside of the semiconductor film, and it is possible to uniformly heat almost the entire semiconductor film in the laser light irradiation region.
[0046]
The laser beam is scanned in a direction parallel to the direction in which the linear stripe pattern extends, and the melted semiconductor flows into the concave portion due to surface tension and solidifies. In the solidified state, the surface becomes almost flat as shown in FIG. This is because once the semiconductor is melted, the interface between the melted semiconductor and the gas phase reaches an equilibrium state, whether on the convex portion or the concave portion, and a flat interface is formed. Further, the crystal growth edge and the crystal grain boundary are formed on the second insulating film (on the convex portion) (region 110 indicated by hatching in the drawing). Thus, the crystalline semiconductor film 107 is formed.
[0047]
After that, heat treatment is preferably performed at 500 to 600 ° C. to remove distortion accumulated in the crystalline semiconductor film. This distortion occurs due to semiconductor volume shrinkage caused by crystallization, thermal stress with the base, or lattice mismatch. This heat treatment may be performed using a normal heat treatment apparatus. For example, a gas heating rapid thermal annealing (RTA) method may be used for 1 to 10 minutes. Note that this step is not an essential requirement in the present invention, and may be appropriately selected.
[0048]
After that, as shown in FIG. 2B, the crystalline semiconductor film 107 is etched to form an active layer 108 of the thin film transistor. At this time, the region 110 where the growth edges and crystal grain boundaries are concentrated may remain in part. A feature of the present invention is that the second crystalline semiconductor region including the region 110 is actively used as an electrode such as a source region or a drain region of a thin film transistor, whereby electrodes connected to the source region or the drain region and each region ( The purpose is to secure a design margin of a contact portion (regions indicated by 111 and 112 in FIG. 2B) with a source electrode or a drain electrode. Needless to say, the highly crystalline semiconductor regions (first crystalline semiconductor regions) 109a and 109b formed in the recesses are used as channel formation regions of the thin film transistor. The semiconductor regions 109a and 109b having high crystallinity have a feature that they have a plurality of crystal orientations and no crystal grain boundaries are formed.
[0049]
Next, as shown in FIG. 3A, resist masks 113a and 113b are formed so as to hide subsequent source and drain regions in the active layer 108, and then the active layer is formed by dry etching or wet etching. 108 is etched to expose the second insulating films 103 to 105. Note that the etching step may use not only a chemical method but also a mechanical polishing method such as CMP (Chemical Mechanical Polishing). Moreover, you may use a chemical method and a mechanical method together.
[0050]
In this step, the first crystalline semiconductor region and the second crystalline semiconductor region remain in the original thickness in the portions hidden by the resist masks 113a and 113b, and the second insulating films 103 to 105 remain in the recesses. The first crystalline semiconductor regions 114a and 114b having substantially the same thickness can be left.
[0051]
Thus, an active layer 115 as shown in FIG. 3B is formed. In the active layer 115, the conductive region (the later source region 116 or the later drain region 117) remains thicker than the first crystalline semiconductor regions (the later channel formation regions) 114a and 114b. According to this embodiment, since the first crystalline semiconductor regions 114a and 114b can be formed in a self-aligned manner by the second insulating films 103 to 105, the convex portions of the second insulating film are erroneously formed due to the pattern shift. Thus, the formation of a channel formation region can be prevented, and the occurrence of a crystal grain boundary in the channel formation region can be reduced.
[0052]
Next, as shown in FIG. 4, the second insulating films 103 to 105 are etched using the active layer 115 as a mask. The etching may be a wet etching method or a dry etching method, and the practitioner may appropriately select the conditions for the selection ratio between the active layer 115 and the second insulating films 103 to 105. For example, when a crystalline silicon film is used as the material of the active layer 115 and a silicon oxide film is used as the material of the second insulating films 103 to 105, wet etching using a hydrofluoric acid aqueous solution or CHF _Three Dry etching using gas may be used. However, since wet etching becomes isotropic etching, it is desirable to perform anisotropic etching by dry etching.
[0053]
Note that the second insulating films 103 a, 104 a, and 105 a formed in a self-aligned manner by the active layer 115 remain under the later source region 116 (the same applies to the later drain region 117). Since these remain, the flatness of the later source region 116 and the later drain region 117 can be ensured.
[0054]
When the state of FIG. 4 is obtained in this way, a gate insulating film and a gate electrode are formed so that the first crystalline semiconductor regions 114a and 114b become channel formation regions. Through these steps, a transistor can be completed.
[0055]
FIG. 5 is a conceptual diagram showing the knowledge of crystallization obtained from the experimental results by the present inventors. 5A to 5E schematically illustrate the relationship between crystal growth and the depth and interval of the recesses formed by the first insulating film and the second insulating film.
[0056]
5, t01: thickness of the amorphous semiconductor film on the second insulating film (convex portion), t02: thickness of the amorphous semiconductor film in the concave portion, t11: second Thickness of crystalline semiconductor film on insulating film (convex portion), t12: Thickness of crystalline semiconductor film in concave portion, d: Thickness of second insulating film (depth of concave portion), W1: Second insulating film , W2: the width of the recess.
[0057]
FIG. 5A shows a case where d <t02, W1, W2 is about 1 μm or less, and when the depth of the recess is smaller than that of the amorphous semiconductor film 204, melt crystallization is performed. Even through this process, since the recess is shallow, the surface of the crystalline semiconductor film 205 is not sufficiently planarized. That is, the surface state of the crystalline semiconductor film 205 is a state in which the uneven shape of the base is reflected.
[0058]
FIG. 5B shows a case where d ≧ t02 and W1 and W2 are approximately equal to or less than 1 μm. In the case where the depth of the recess is substantially equal to or greater than that of the amorphous semiconductor film 204, FIG. The surface tension works and collects in the recess. In the solidified state, the surface becomes almost flat as shown in FIG. In this case, t11 <t12, stress concentrates on the thin portion 220 on the second insulating film 202, strain is accumulated therein, and a crystal grain boundary is formed.
[0059]
The scanning electron microscope (SEM) photograph shown in FIG. 22 (A) shows an example of the state of FIG. 5 (B). On the base insulating film provided with a step of 170 nm and a width and interval of a convex part of 0.5 μm. The result of crystallization by forming an amorphous silicon film of 150 nm is shown. Further, the surface of the crystalline semiconductor film is a seco liquid (HF: H) which is generally known to make the crystal grain boundary manifest. ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ Etching (also called Seco-etching) with chemicals prepared using
[0060]
The results shown in FIG. 22 indicate that potassium dichromate (K ₂ Cr ₂ O ₇ ) 2.2 g was dissolved in 50 cc of water to prepare a 0.15 mol / l solution, and 100 cc of hydrofluoric acid solution was added to the solution, which was further diluted 5-fold with water, and used as the secco solution. Further, the conditions for the secco etching were 75 seconds at room temperature (10 to 30 ° C.). In this specification, the term “seco liquid” or “seco etching” refers to the solution and conditions described here.
[0061]
FIG. 22B is a schematic diagram of the photograph in FIG. In the figure, reference numeral 31 denotes an insulating film (second insulating film) extending in a linear stripe pattern, and crystal grain boundaries 33 clarified by Secco etching are intensively generated on the convex portions 32. I can see how they are. Note that the region 34 described as the disappearing portion is a region corresponding to the starting point of the stripe pattern, and the scanning of the laser beam is started from this starting point. Although the detailed reason is unknown, the silicon film on the starting point is a region where the second insulating film located at the starting point has been exposed by being pushed in the scanning direction when melted. Since the Seco solution etches the silicon oxide film, the region located at the starting point has disappeared by Seco etching.
[0062]
By the way, when compared with the photograph shown in FIG. 22A, the crystalline semiconductor film formed in the concave portion 35 does not reveal crystal grain boundaries or defects that are clarified by secco etching. If it does, it turns out that it does not exist substantially. Although the grain boundaries that are clarified by Secco etching have not been identified at present, it is a well-known fact that stacking faults and grain boundaries are preferentially etched by Seco etching, and the present invention is It can be said that the crystalline semiconductor film obtained by the implementation has a great feature in that there is substantially no crystal grain boundary or defect which becomes apparent by Secco etching.
[0063]
Of course, since it is not a single crystal, there may naturally be grain boundaries and defects that do not appear by Secco etching. However, such grain boundaries and defects do not affect the electrical characteristics when semiconductor devices are manufactured. It is considered electrically inactive. In general, such an electrically inactive grain boundary is called a planar grain boundary (low-order or higher-order twin or corresponding grain boundary), and is not manifested by Secco etching. Is presumed to be a planar grain boundary. From this point of view, it can be said that substantially no crystal grain boundaries or defects exist, it can be said that there are no crystal grain boundaries other than planar grain boundaries.
[0064]
FIG. 24 shows the result of obtaining the orientation of the crystalline semiconductor film formed in the recess 35 shown in FIG. 22B by a reflected electron diffraction pattern (EBSP). EBSP provides a scanning electron microscope (SEM) with a dedicated detector, which irradiates the crystal plane with an electron beam and causes the computer to recognize the crystal orientation from the Kikuchi line. The crystallinity is measured not only on the surface orientation but also in all directions of the crystal (hereinafter, this method is referred to as EBSP method for convenience).
[0065]
The data in FIG. 24 indicates that the crystal grows in the concave portion 35 in a direction parallel to the scanning direction of the laser beam condensed linearly. As for the crystal orientation of growth, the <110> orientation is dominant (that is, the main orientation plane is the {110} plane), but growth of the <100> orientation also exists.
[0066]
FIG. 5C shows a case where d ≧ t02 and W1 and W2 are approximately the same as or slightly larger than 1 μm. When the width of the concave portion is widened, the crystalline semiconductor film 205 fills the concave portion, and there is an effect of planarization. A crystal grain boundary is generated near the center of the recess. Similarly, stress is concentrated on the second insulating film, strain is accumulated therein, and a crystal grain boundary is formed. This is presumed to be because the effect of stress relaxation is reduced by increasing the interval. Under these conditions, a crystal grain boundary may also occur in the semiconductor region serving as a channel formation region, which is not preferable.
[0067]
FIG. 5D shows a case where d ≧ t02 and W1 and W2 are larger than 1.0 μm, and the state of FIG. This condition is not preferable because a crystal grain boundary is generated in the semiconductor region serving as the channel formation region with a considerable probability.
[0068]
The scanning electron microscope (SEM) photograph shown in FIG. 23 (A) shows an example of the state shown in FIG. 5 (D). On the base insulating film provided with a step of 170 nm and a width and interval of a projection of 1.8 μm. The result of crystallization by forming an amorphous silicon film of 150 nm is shown. The surface of the crystalline semiconductor film is etched with the aforementioned Seco solution in order to reveal the crystal grain boundaries.
[0069]
FIG. 23B is a schematic diagram of the photograph in FIG. In the figure, reference numeral 41 denotes an insulating film (second insulating film) extending in a linear stripe pattern, and crystal grain boundaries 43 clarified by secco etching are concentrated on the convex portions 42 and the end portions thereof. I can see how it is occurring. Note that the region 44 described as the disappearing portion is a region corresponding to the start point of the stripe pattern, and has disappeared by the secco etching for the reason described above. In contrast to the photograph shown in FIG. 23A, the crystal grain boundary is generated not only in the convex part 42 of the stripe pattern but also in the concave part 45.
[0070]
FIG. 5E shows a reference example in the present invention, where d >> t02 and W1 and W2 are 1 μm or less. That is, when the thickness d of the second insulating film is too thick compared with the thickness t02 of the amorphous semiconductor film in the concave portion, the crystalline semiconductor film 205 is formed so as to fill the concave portion. Hardly remains. Therefore, unlike the present invention, the crystalline semiconductor film on the second insulating film cannot be used as a contact portion between the source region and the source electrode (or the drain region and the drain electrode).
[0071]
As described above with reference to FIGS. 5A to 5D, when a semiconductor element is formed, particularly when a channel formation region in a thin film transistor is formed, the configuration in FIG. 5B is most suitable. It is thought that there is. That is, a crystalline semiconductor film in which almost no crystal grain boundaries or defects become apparent when performing the seco-etching with the above-mentioned secco solution, in other words, a crystalline semiconductor film in which crystal grain boundaries and defects do not substantially exist. It is desirable to use it for the channel formation region.
[0072]
In addition, although the example in which the uneven shape of the base for forming the crystalline semiconductor film is formed using the first insulating film and the second insulating film is shown here, it is not limited to the form shown here and has a similar shape. It can be replaced if there is one. For example, a recess having a desired depth may be formed by etching an insulating film having a thickness of about 200 nm to 2 μm.
[0073]
In the crystallization step, if the second insulating film is a soft insulating film (insulating film having a low density) as described above, an effect of relaxing stress due to shrinkage of the semiconductor film during crystallization is expected. it can. On the other hand, if a hard insulating film (insulating film with high density) is used, stress is generated against the semiconductor film that is about to shrink or expand, so that it is easy to leave stress strain or the like in the semiconductor film after crystallization. It may also cause For example, in the known graphoepitaxy technology (“MWGeis, DCFlanders, HISmith: Appl. Phys. Lett. 35 (1979) pp71”), the irregularities on the substrate are directly formed of hard quartz glass. It has been found that the orientation axis of Si is the [100] axis, that is, the main orientation plane is the {100} plane.
[0074]
However, when the present invention is carried out, as shown in FIG. 24, the main orientation plane (the orientation plane with the highest existence frequency) is {110}, and semiconductor films having clearly different crystal forms are formed. I know that. The present applicant speculates that the difference is due to the soft insulating film in which the unevenness on the substrate is formed by the above-described CVD method or PVD method. That is, by making the second insulating film as a base material softer than quartz glass, the generation of stress during crystallization could be more relaxed, or the stress can be concentrated on the crystalline semiconductor film on the convex portion. I guess I was able to.
[0075]
The meaning of an insulating film softer than quartz glass means, for example, an insulating film having a faster etching rate or a lower hardness than general quartz glass (quartz glass that is industrially used as a substrate). . Since these etching rates and hardness can be determined by relative comparison with quartz glass, they do not depend on the etching rate measurement conditions and the hardness measurement conditions.
[0076]
For example, if a silicon oxynitride film is used as the second insulating film, SiH _Four Gas, N ₂ A silicon oxynitride film formed by a plasma CVD method using O gas as a raw material is preferable. The silicon oxynitride film is made of ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four The etching rate at 20 ° C. of the mixed aqueous solution containing 15.4% of F) is 110 to 130 nm / min (500 ° C., 1 hour + 550 ° C., after 4 hours of heat treatment, 90 to 100 nm / min).
[0077]
If a silicon oxynitride film is used as the second insulating film, SiH _Four Gas, NH _Three Gas, N ₂ A silicon oxynitride film formed by a plasma CVD method using O gas as a raw material is preferable. The silicon nitride oxide film is made of ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four The etching rate at 20 ° C. of the mixed aqueous solution containing 15.4% of F) is 60 to 70 nm / min (40 to 50 nm / min after heat treatment at 500 ° C., 1 hour + 550 ° C. for 4 hours).
[0078]
As described above, a linear stripe pattern having recesses and projections is formed by an insulating film, an amorphous semiconductor film is deposited thereon, and crystallized through a molten state by irradiation with laser light, thereby forming recesses. The semiconductor is poured and solidified, so that strain or stress accompanying crystallization can be concentrated in a region other than the concave portion, and a region having poor crystallinity such as a crystal grain boundary can be selectively formed. A feature of the present invention is that a semiconductor region with good crystallinity is used as a region where carrier movement is performed, such as a channel formation region of a thin film transistor, and a semiconductor region with poor crystallinity is used as a contact portion with an electrode.
[0079]
That is, a crystalline semiconductor film in which a plurality of crystal grains extending in a direction parallel to a direction in which a linear stripe pattern extends is formed without a crystal grain boundary having a plurality of crystal orientations in a recess Can be formed. By forming a transistor so that a channel formation region is formed using such a crystalline semiconductor film, a transistor or a transistor group that can operate at high speed, has high current driving capability, and has little variation among a plurality of elements. The semiconductor device comprised by this can be formed.
[0080]
[Embodiment 2]
In the formation of the crystalline semiconductor film of the present invention, in addition to the method of crystallizing the amorphous semiconductor film by irradiating the amorphous semiconductor film as shown in Embodiment Mode 1, the laser light is further crystallized after crystallization by solid phase growth. May be melted and recrystallized.
[0081]
For example, after the amorphous semiconductor film 106 is formed in FIG. 1B, the crystallization temperature of the amorphous semiconductor film (eg, an amorphous silicon film) is lowered to improve the orientation. Ni is added as a catalytic metal element that promotes the above.
[0082]
This technique is detailed in Japanese Patent Application Laid-Open No. 11-354442 by the present applicant. A crystalline semiconductor film formed by adding Ni has a feature that a main orientation plane is a {110} plane. When such a crystalline semiconductor film is used for a channel formation region of a thin film transistor, electron mobility and Both the hole mobility is greatly improved, and the field effect mobility of the N-channel transistor and the P-channel transistor is greatly improved. In particular, the improvement of the field effect mobility of the P-channel transistor accompanying the improvement of the hole mobility is notable and is one of the advantages of setting the main orientation plane to {110}.
[0083]
Further, there is no limitation on the addition method of Ni, and a spin coating method, a vapor deposition method, a sputtering method, or the like can be applied. In the case of the spin coating method, an aqueous solution containing 5 ppm of nickel acetate is applied to form a metal element-containing layer. Of course, the catalyst element is not limited to Ni, and other known materials may be used.
[0084]
Thereafter, the amorphous semiconductor film 106 is crystallized by heat treatment at 580 ° C. for 4 hours. This crystallized semiconductor film is melted and recrystallized by irradiating it with laser light or strong light equivalent thereto. In this manner, a crystalline semiconductor film having a substantially flat surface can be obtained as in FIG. Similarly, this crystalline semiconductor film is also formed with a region where a growth edge or a crystal grain boundary 110 is formed.
[0085]
The advantage of using a crystallized semiconductor film as an object to be irradiated with laser light is the fluctuation rate of the light absorption coefficient of the semiconductor film. Even if the crystallized semiconductor film is melted by irradiation with laser light, the light absorption coefficient is Almost no change. Therefore, a wide margin of laser irradiation conditions can be taken.
[0086]
A metal element remains in the crystalline semiconductor film thus formed, but can be removed by gettering treatment. For details of this technique, refer to Japanese Patent Application No. 2001-019367 (or Japanese Patent Application No. 2002-020801). Further, the heat treatment accompanying the gettering treatment has an effect of alleviating distortion of the crystalline semiconductor film.
[0087]
After that, as in Embodiment Mode 1, a thin film transistor is formed using the recessed crystalline semiconductor film as a channel formation region and the protruding crystalline semiconductor film as a source region or a drain region. The crystalline semiconductor film in the recess has a feature that it has a plurality of crystal orientations and no grain boundary is formed, so that it can operate at high speed, has high current driving capability, and varies among a plurality of elements. A semiconductor device including a small transistor or a transistor group thereof can be formed.
[0088]
[Embodiment 3]
Next, one embodiment of a transistor in which a crystalline silicon film is formed over a base insulating film having a recess and a channel formation region is provided in a semiconductor region formed in the recess in this embodiment is illustrated in the drawings. It explains using. Note that, in each drawing according to the present embodiment, (A) is a top view, and (B) and subsequent drawings are longitudinal sectional views of corresponding parts.
[0089]
In FIG. 6, a first insulating film 302 made of silicon nitride having a thickness of 30 to 300 nm and silicon oxynitride, aluminum nitride, or aluminum oxynitride having a nitrogen content larger than the oxygen content is formed on a glass substrate 301. A linear stripe pattern having concave and convex portions thereon is formed by a second insulating film 303 made of silicon oxide or silicon oxynitride. The silicon oxide film is formed by TEOS and O by plasma CVD. ₂ And a reaction pressure of 40 Pa, a substrate temperature of 400 ° C., and a high frequency (13.56 MHz) power density of 0.6 W / cm. ² And is deposited to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm, and then a recess 304 is formed by etching. The width of the recess is 0.01 to 1 [mu] m, preferably 0.05 to 0.2 [mu] m, particularly in the place where the channel forming region is arranged.
[0090]
Next, the third insulating film 305 and the amorphous silicon film 306 made of an oxide film or a silicon oxynitride film are exposed to the atmosphere on the first insulating film 302 and the second insulating film 303 using the same plasma CVD apparatus. Without film formation. The amorphous silicon film 305 is formed of a semiconductor film containing silicon as a main component, and SiH is formed by plasma CVD. _Four Is used as a raw material gas. At this stage, as shown in FIG. 6B, a non-flat surface shape is formed covering the bottom and side surfaces of the recess 304.
[0091]
Crystallization is performed by irradiating a continuous wave laser beam. FIG. 7 shows the state after the crystallization. The crystallization conditions are YVO in continuous oscillation mode. _Four Using a laser oscillator, the output of 5 to 10 W of the second harmonic (wavelength 532 nm) is condensed into linear laser light having a ratio of the longitudinal direction to the transverse direction of 10 or more in the optical system, and the longitudinal direction. Are condensed so as to have a uniform energy density distribution, and are crystallized by scanning at a speed of 5 to 200 cm / sec. A uniform energy density distribution does not exclude anything that is completely constant, but the allowable range in the energy density distribution is ± 10%.
[0092]
It is desirable that the intensity distribution of the laser beam condensed linearly is uniform in the direction in which the intensity distribution is long (the X-axis direction in FIG. 2A). The purpose of this is to make the temperature of the semiconductor to be heated uniform throughout the laser light irradiation region. This is because if the temperature distribution is generated in the X-axis direction of the laser light that is condensed linearly, the crystal growth direction of the semiconductor film cannot be defined as the scanning direction of the laser light. By aligning the linear stripe pattern with the scanning direction of the irradiation region of the laser beam focused in a linear manner, the crystal growth direction can be matched with the channel length direction of all transistors. . Thereby, the characteristic variation between the elements of the transistor can be reduced.
[0093]
Further, the crystallization by the laser beam condensed linearly may be completed by only one scan (that is, one direction), or may be reciprocated to improve the crystallinity. Furthermore, after crystallizing with laser light, the surface of the silicon film is treated with an alkali solution such as oxide removal with hydrofluoric acid or ammonia hydrogen peroxide solution treatment, and the poor quality part with high etching rate is selectively used. It may be removed and the same crystallization treatment may be performed again. In this way, crystallinity can be increased.
[0094]
By irradiating with laser light under these conditions, the amorphous semiconductor film is instantaneously melted and crystallized. In practice, crystallization proceeds while the melting zone moves. The molten silicon is agglomerated and solidified in the recesses due to surface tension. As a result, as shown in FIG. 7, a crystalline semiconductor film 307 having a flat surface is formed in a form in which the recess 304 is filled.
[0095]
Thereafter, as shown in FIG. 8, the crystalline semiconductor film 307 is etched to form semiconductor regions 308 to 310 to be active layers of the thin film transistor. Note that FIG. 8 does not limit the shape of the semiconductor regions 308 to 310, and is not particularly limited as long as a predetermined design rule is satisfied as described in the first embodiment.
[0096]
The crystalline semiconductor film 307 can be selectively etched with the third insulating film 305 by using a fluorine-based gas and oxygen as etching gases. Of course, even if the third insulating film 305 is etched, there is no problem as long as the selectivity with respect to the first insulating film 302 and the second insulating film 303 therebelow can be ensured.
[0097]
As an etching gas, CF _Four And O ₂ Mixed gas and NF _Three It may be performed by a plasma etching method using a gas, or ClF. _Three Plasmaless gas etching using a gas such as a halogen fluoride gas without being excited may be performed. Plasmaless gas etching is an effective technique for suppressing crystal defects because it does not cause plasma damage to the crystalline semiconductor film.
[0098]
Next, as described with reference to FIG. 3 in Embodiment Mode 1, a resist mask (not shown) is provided, and a portion to be a channel formation region of the semiconductor regions 308 to 309 is thinned. This thinning process is performed in CF _Four Gas and O ₂ A mixed gas with gas may be used. When the thinning is completed, the resist mask is removed, and the third insulating film 305 and the second insulating film 303 are etched in a self-aligning manner using the semiconductor region as a mask as described with reference to FIG. The state shown in 9 is obtained. In FIG. 9, reference numerals 308a to 310a denote semiconductor regions obtained by thinning portions that become channel formation regions. Of course, as shown in FIG. 9C, the second insulating film 303 remains in the cross section taken along CC ′ of FIG. 9A, and the semiconductor region has a thickness before the thinning. Remaining.
[0099]
Next, as illustrated in FIG. 10, a fourth insulating film (functioning as a gate insulating film) 311 and conductive films 312 and 313 used as gate electrodes are formed so as to cover the semiconductor regions 308 a to 310 a. The fourth insulating film 311 is formed using the silicon oxide film, the silicon nitride film, the silicon oxynitride film, the silicon nitride oxide film, the aluminum nitride film, the aluminum nitride oxide film, the aluminum oxynitride film, or the aluminum oxide film described in Embodiment 1. Any of them may be used, or a laminated film appropriately combining them may be used.
[0100]
In order to improve the coverage of the gate insulating film, a silicon oxide film using TEOS is preferable for a silicon oxide film, and an aluminum nitride oxide film formed by an RF sputtering method is used for an aluminum nitride oxide film, or the nitrogen nitride film is used. A stacked film of an aluminum oxide film and a silicon oxide film (a silicon oxide film may be obtained by oxidizing a semiconductor film serving as an active layer with hydrogen peroxide) may be used.
[0101]
The conductive films 312 and 313 used as gate electrodes are formed using tungsten, an alloy containing tungsten, aluminum, an aluminum alloy, or the like.
[0102]
Next, as shown in FIG. 11, impurity regions 314 to 319 having one conductivity type are formed in the semiconductor regions 308a to 310a. Here, for convenience, n-type impurity regions 314, 315, 318, and 319 and p-type impurity regions 316 and 317 are provided. These impurity regions may be formed in a self-aligning manner using the conductive films 312 and 313 used as gate electrodes as a mask, or may be formed by masking with a photoresist or the like. The impurity regions 314 to 319 form source and drain regions, and a low-concentration drain region (generally called an LDD region) can be provided as necessary.
[0103]
For the impurity regions 314 to 319, an ion implantation method or an ion doping method in which impurity ions are accelerated by an electric field and implanted into the semiconductor region is applied. In this case, the presence or absence of mass separation of the ion species to be implanted does not constitute an essential problem in applying the present invention.
[0104]
At this time, of the semiconductor regions 308a to 310a, the semiconductor region 320 below the gate electrodes 312 and 313 and formed in the recess 304 is a channel formation region of the thin film transistor of the present invention.
[0105]
Then, as shown in FIG. 12, a fifth insulating film (functioning as a passivation film) 321 made of a silicon nitride film or silicon oxynitride film containing hydrogen of about 50 to 100 nm is formed. By performing heat treatment at 400 to 450 ° C. in this state, hydrogen contained in the silicon nitride film or the silicon oxynitride film is released, and the island-shaped semiconductor film can be hydrogenated.
[0106]
Next, a sixth insulating film (functioning as an interlayer insulating film) 322 formed of a silicon oxide film or the like is formed, and wirings 323 to 327 connected to the impurity regions 314 to 319 are formed. In this manner, n-channel transistors 328 and 330 and a p-channel transistor 329 can be formed.
[0107]
In the n-channel transistor 328 and the p-channel transistor 329 shown in FIG. 12, a plurality of channel formation regions 320 are arranged in parallel, and between a pair of impurity regions 314 and 315 (or 316 and 317). A multi-channel transistor provided in a connected manner is shown. Specifically, an example in which an n-channel multichannel transistor 328 and a p-channel multichannel transistor 329 form an inverter circuit that is a basic circuit of a CMOS structure is shown. In this configuration, the number of channel formation regions provided in parallel is not limited, and a plurality of channel formation regions may be provided as necessary. For example, a single channel may be used like the n-channel transistor 330.
[0108]
[Embodiment 4]
In this embodiment, an example in which a thin film transistor functioning as a switching element and a storage capacitor for storing charge to be stored in each pixel are formed in a pixel portion of a semiconductor device. Specifically, a crystalline silicon film is formed over a base insulating film having a recess, a thin film transistor in which a channel formation region is provided in a semiconductor region formed in the recess, and the recess is formed in the recess An example is shown in which a storage capacitor including another semiconductor region as one electrode is formed. Note that, in each drawing according to the present embodiment, (A) is a top view, and (B) and subsequent drawings are longitudinal sectional views of corresponding parts.
[0109]
In FIG. 6, a first insulating film 302 made of silicon nitride having a thickness of 30 to 300 nm and silicon oxynitride, aluminum nitride, or aluminum oxynitride having a nitrogen content larger than the oxygen content is formed on a glass substrate 301. A linear stripe pattern having concave and convex portions thereon is formed by a second insulating film 303 made of silicon oxide or silicon oxynitride. The silicon oxide film is formed by TEOS and O by plasma CVD. ₂ And a reaction pressure of 40 Pa, a substrate temperature of 400 ° C., and a high frequency (13.56 MHz) power density of 0.6 W / cm. ² And is deposited to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm, and then a recess 304 is formed by etching. The width of the recess is 0.01 to 1 [mu] m, preferably 0.05 to 0.2 [mu] m, particularly in the place where the channel forming region is arranged.
[0110]
Next, the third insulating film 305 and the amorphous silicon film 306 made of an oxide film or a silicon oxynitride film are exposed to the atmosphere on the first insulating film 302 and the second insulating film 303 using the same plasma CVD apparatus. Without film formation. The amorphous silicon film 305 is formed of a semiconductor film containing silicon as a main component, and SiH is formed by plasma CVD. _Four Is used as a raw material gas. At this stage, as shown in FIG. 6B, a non-flat surface shape is formed covering the bottom and side surfaces of the recess 304.
[0111]
Crystallization is performed by irradiating a continuous wave laser beam. FIG. 7 shows the state after the crystallization. The crystallization conditions are YVO in continuous oscillation mode. _Four Using a laser oscillator, the output of 5 to 10 W of the second harmonic (wavelength 532 nm) is condensed into linear laser light having a ratio of the longitudinal direction to the transverse direction of 10 or more in the optical system, and the longitudinal direction. Are condensed so as to have a uniform energy density distribution, and are crystallized by scanning at a speed of 5 to 200 cm / sec. A uniform energy density distribution does not exclude anything that is completely constant, but the allowable range in the energy density distribution is ± 10%.
[0112]
It is desirable that the intensity distribution of the laser beam condensed linearly is uniform in the direction in which the intensity distribution is long (the X-axis direction in FIG. 2A). The purpose of this is to make the temperature of the semiconductor to be heated uniform throughout the laser light irradiation region. This is because if the temperature distribution is generated in the X-axis direction of the laser light that is condensed linearly, the crystal growth direction of the semiconductor film cannot be defined as the scanning direction of the laser light. By aligning the linear stripe pattern with the scanning direction of the irradiation region of the laser beam focused in a linear manner, the crystal growth direction can be matched with the channel length direction of all transistors. . Thereby, the characteristic variation between the elements of the transistor can be reduced.
[0113]
Further, the crystallization by the laser beam condensed linearly may be completed by only one scan (that is, one direction), or may be reciprocated to improve the crystallinity. Furthermore, after crystallizing with laser light, the surface of the silicon film is treated with an alkali solution such as oxide removal with hydrofluoric acid or ammonia hydrogen peroxide solution treatment, and the poor quality part with high etching rate is selectively used. It may be removed and the same crystallization treatment may be performed again. In this way, crystallinity can be increased.
[0114]
By irradiating with laser light under these conditions, the amorphous semiconductor film is instantaneously melted and crystallized. In practice, crystallization proceeds while the melting zone moves. The molten silicon is agglomerated and solidified in the recesses due to surface tension. As a result, as shown in FIG. 7, a crystalline semiconductor film 307 having a flat surface is formed in a form in which the recess 304 is filled.
[0115]
After that, as shown in FIG. 28, the crystalline semiconductor film 307 is etched to form a semiconductor region 358 serving as an active layer of the thin film transistor and a semiconductor region 359 serving as one electrode (lower electrode) of the storage capacitor. Note that FIG. 28 does not limit the shape of the semiconductor regions 358 and 359 and is not particularly limited as long as it conforms to a predetermined design rule as described in the first embodiment.
[0116]
The crystalline semiconductor film 307 can be selectively etched with the third insulating film 305 by using a fluorine-based gas and oxygen as etching gases. Of course, even if the third insulating film 305 is etched, there is no problem as long as the selectivity with respect to the first insulating film 302 and the second insulating film 303 therebelow can be ensured. As an etching gas, CF _Four And O ₂ Mixed gas and NF _Three It may be performed by a plasma etching method using a gas, or ClF. _Three Plasmaless gas etching using a gas such as a halogen fluoride gas without being excited may be performed. Plasmaless gas etching is an effective technique for suppressing crystal defects because it does not cause plasma damage to the crystalline semiconductor film.
[0117]
Next, as described with reference to FIG. 3 in Embodiment Mode 1, a resist mask (not shown) is provided, and a portion that is a channel formation region of the semiconductor region 358 and a portion that is a stripe pattern of the semiconductor region 359 are formed. Thin film. This thinning process is performed in CF _Four Gas and O ₂ A mixed gas with gas may be used. When the thinning is completed, the resist mask is removed, and the third insulating film 305 and the second insulating film 303 are etched in a self-aligning manner using the semiconductor region as a mask as described with reference to FIG. The state shown in 29 is obtained. In FIG. 29, reference numerals 358a and 359a denote semiconductor regions obtained by thinning a portion to be a channel formation region and a portion having a stripe pattern, respectively. Of course, as shown in FIG. 29C, the second insulating film 303 remains in the cross section taken along CC ′ of FIG. 29A, and the semiconductor region has a thickness before thinning. Remaining.
[0118]
Next, as illustrated in FIG. 30, a gate insulating film 360, a gate wiring (also functioning as a gate electrode) 361, and a capacitor wiring 362 are formed so as to cover the semiconductor regions 358a and 359a. The gate insulating film 360 is any of the silicon oxide film, the silicon nitride film, the silicon oxynitride film, the silicon nitride oxide film, the aluminum nitride film, the aluminum nitride oxide film, the aluminum oxynitride film, and the aluminum oxide film described in Embodiment 1. May be used, or a laminated film in which these are appropriately combined may be used. In order to improve the coverage of the gate insulating film, a silicon oxide film using TEOS is preferable for a silicon oxide film, and an aluminum nitride oxide film formed by an RF sputtering method is used for an aluminum nitride oxide film, or the nitrogen nitride film is used. A stacked film of an aluminum oxide film and a silicon oxide film (a silicon oxide film may be obtained by oxidizing a semiconductor film serving as an active layer with hydrogen peroxide) may be used. The gate electrode 361 and the capacitor wiring 362 are formed using tungsten, an alloy containing tungsten, aluminum, an aluminum alloy, or the like.
[0119]
In this state, a storage capacitor is formed by the semiconductor region 359 a including the first crystalline semiconductor region, the gate insulating film 360, and the capacitor wiring 362. That is, the semiconductor region 359a functions as one electrode, the gate insulating film 360 functions as a dielectric, and the capacitor wiring 362 functions as a storage capacitor as the other electrode.
[0120]
Next, as shown in FIG. 31, impurity regions 363 and 364 of one conductivity type are formed in the semiconductor regions 358a and 359a. Here, n-type impurity regions 363 and 364 are provided for convenience. These impurity regions may be formed in a self-aligning manner using the gate electrode 361 and the capacitor wiring 362 as a mask, or may be formed by masking with a photoresist or the like. The impurity regions 363 and 364 are regions that serve as a source region or a drain region of a thin film transistor that functions as a switching element, and a low-concentration drain region (generally called an LDD region) can be provided as needed.
[0121]
At this time, of the semiconductor regions 358a and 359a, the semiconductor region 365 below the gate electrode 361 and formed in the recess 354 is a channel formation region of the thin film transistor, and the semiconductor region 366 below the capacitor wiring 362 is held. It becomes the lower electrode of the capacitor.
[0122]
Then, as shown in FIG. 32, a passivation film 367 made of a silicon nitride film or silicon oxynitride film containing hydrogen of about 50 to 100 nm is formed. By performing heat treatment at 400 to 450 ° C. in this state, hydrogen contained in the silicon nitride film or the silicon oxynitride film is released, and the island-shaped semiconductor film can be hydrogenated. Next, an interlayer insulating film 368 formed using a silicon oxide film or the like is formed, and a data wiring 369 connected to the impurity region 364 and a drain wiring 370 connected to the impurity region 363 are formed. Note that 371 is a contact portion between the impurity region 364 and the data wiring 369, and 372 is a contact portion between the impurity region 363 and the drain wiring 370.
[0123]
Through the process so far, an n-channel thin film transistor is completed. The n-channel thin film transistor shown in FIG. 32 has a multi-channel structure in which a plurality of channel formation regions 365 are arranged in parallel and are connected to each other between a pair of impurity regions 363 and 364. ing. In this configuration, the number of channel formation regions provided in parallel is not limited, and a plurality of channel formation regions may be provided as necessary.
[0124]
When the n-channel thin film transistor is completed, an interlayer insulating film 373 is further formed. Any material may be used for the interlayer insulating film 373 as long as it is a known insulating film, and an organic resin film that can be flattened is particularly preferable. Further, a nitride insulating film may be stacked in combination with an organic resin film as necessary. Then, a pixel electrode 374 made of an oxide conductive film (typically ITO) is formed over the interlayer insulating film 373. Thus, an active matrix substrate having a thin film transistor 380 functioning as a switching element and a storage capacitor 381 functioning as charge holding means is completed. Note that an active matrix substrate refers to a substrate on which various circuits and pixel portions are formed in a semiconductor device such as a liquid crystal display device.
[0125]
FIG. 33A shows an enlarged cross-sectional view of the portion of the storage capacitor 381 in FIG. 32B in the active matrix substrate completed by the process as described above. In FIG. 33A, a capacitor (also referred to as a storage capacitor) is formed in a portion described as Cs, and three capacitors are formed on each of the three sides of the side surface and the upper surface of the semiconductor region 366. Is done. In the present embodiment, since three semiconductor regions 366 are provided in parallel, a total of nine capacitors described as Cs are formed.
[0126]
FIG. 33B is an equivalent schematic diagram of the storage capacitor shown in FIG. When the height of the semiconductor region 366 is d and the width is W, an equivalent length L of the semiconductor region 366 in the schematic diagram is represented by L = 6d + 3W1. That is, in the semiconductor device obtained by carrying out the present invention, by forming the storage capacitors individually on the side surface and the upper surface of the semiconductor region 316, the area occupied by the storage capacitors can be reduced as a whole, and a high density charge can be obtained. Can be stored. Therefore, there is an advantage that the aperture ratio (or effective display area) of the pixel can be increased along with the reduction of the occupied area in the pixel.
[0127]
[Embodiment 5]
In Embodiments 3 and 4, the transistor has a single drain structure, but a lightly doped drain (LDD) may be provided. FIG. 13 shows an example of an n-channel multichannel transistor having an LDD structure.
[0128]
The structure of the transistor illustrated in FIG. 13A is an example in which a gate electrode is formed using a nitride metal 340a such as titanium nitride or tantalum nitride and a refractory metal 340b such as tungsten or a tungsten alloy. A spacer 341 is provided on a side surface of the gate electrode 340b. Provided. The spacer 341 may be formed of an insulator such as silicon oxide, may be formed of n-type polycrystalline silicon in order to have conductivity, and is formed by anisotropic dry etching. The LDD regions 342a and 342b can be formed in a self-aligned manner with respect to the gate electrode 340b by forming them before forming the spacers. In the case where the spacer is formed using a conductive material, a gate-overlapped LDD (LDD) structure in which the LDD regions 342a and 342b substantially overlap with the gate electrode can be formed.
[0129]
On the other hand, FIG. 13B shows a structure in which the gate electrode 340a is not provided. In this case, an LDD structure is formed.
[0130]
In FIG. 13C, an n-type impurity region 344 for forming an LDD region is formed adjacent to the n-type impurity region 315 (363 in Embodiment 4). The gate electrode 343 has a two-layer structure of a lower layer side gate electrode 343a and an upper layer side gate electrode 343b, and the n-type impurity regions 314 and 315 (364 and 363 in the fourth embodiment) and the LDD regions 344a and 344b are self-aligned. Can be formed. Refer to Japanese Patent Application No. 2000-128526 or Japanese Patent Application No. 2001-011085 for details of such a gate electrode and impurity region and a manufacturing method thereof.
[0131]
In any case, the structure in which the LDD region is formed in a self-aligned manner by such a gate structure is particularly effective when the design rule is miniaturized. Although a unipolar transistor structure is shown here, a CMOS structure can be formed as in the third or fourth embodiment.
[0132]
In this embodiment, the configuration other than the configuration of the gate electrode and the LDD region is the same as that in Embodiment 3 or 4, and detailed description thereof is omitted.
[0133]
[Embodiment 6]
This embodiment is an embodiment different from the structure described in Embodiment 1, and relates to an invention characterized in that an impurity region of one conductivity type that functions as an electrode is used as it is as a wiring. In this embodiment, the number of contact portions is reduced to improve the degree of integration by reducing the design margin and to improve the yield.
[0134]
FIG. 14 is used for the description. FIG. 14A is a top view, and FIGS. 14B to 14F are cross-sectional views of corresponding portions. In addition, it is a figure corresponding to the state of FIG. 11 in Embodiment 1. FIG. For the process of reaching this state and the subsequent transistor formation process, Embodiment Mode 3 may be referred to.
[0135]
In FIG. 14A, 401 to 405 are impurity regions of one conductivity type, 401 and 402 are a source region and a drain region of a P-channel transistor, and 403 and 404 are source regions of an N-channel transistor, respectively. , 405 function as drain regions of the N-channel transistor. At this time, the drain region 405 functions as a wiring for electrically connecting two transistors.
[0136]
As a feature of the present invention, since a semiconductor region having poor crystallinity can also be used as an electrode, the number of contact portions can be reduced by using as a wiring as in this embodiment, and contact formation can be performed. Therefore, the design margin can be expanded. Therefore, it is very effective particularly when forming a logic circuit that has been miniaturized.
[0137]
Note that this embodiment is merely an example, and in the present invention, a technical idea that an impurity region of one conductivity type can be used as a wiring as well as an electrode is disclosed. Therefore, the effects described in the present embodiment can be obtained even in combination with any technique disclosed in the first to fifth embodiments.
[0138]
[Embodiment 7]
This embodiment is an embodiment different from the structure described in Embodiment 1, and a transistor having a structure in which a plurality of transistors are connected in series is formed by using an impurity region of one conductivity type as a wiring. The present invention relates to an invention characterized by This embodiment discloses that a transistor having a plurality of channel formation regions between a source region and a drain region can be obtained, and shows a further embodiment of the present invention.
[0139]
FIG. 15 is used for the description. FIG. 15A is a top view, and FIGS. 15B to 15F are cross-sectional views of corresponding portions. In addition, it is a figure corresponding to the state of FIG. 11 in Embodiment 3. For the process to reach this state and the subsequent transistor formation process, Embodiment Mode 1 may be referred to.
[0140]
In FIG. 15A, 411 to 418 are impurity regions of one conductivity type, 411 and 414 are source and drain regions of a P-channel transistor, and 412 and 413 are impurity regions used as wirings. Note that the area occupied by the impurity regions 412 and 413 can be increased as a feature of the present invention, so that the portion can be used simply as a wiring, or the area can be expanded and used as an electrode. Further, it can be processed into a bent shape to have a function as a protection circuit.
[0141]
Reference numeral 415 denotes a source region of a single channel N-channel transistor, and reference numeral 416 denotes a drain region thereof. Further, a transistor having the drain region 416 as a source region and the impurity region 418 as a drain region is formed. In this case, the impurity region 417 functions as a wiring. The transistor has three channel formation regions, two of which are provided in parallel and connected in series with the remaining one. Needless to say, this embodiment mode is not limited to the structure of the transistor.
[0142]
Note that this embodiment is merely an example, and in the present invention, a technical idea that an impurity region of one conductivity type can be used as a wiring as well as an electrode is disclosed. Therefore, it may be combined with any technique disclosed in the first to sixth embodiments.
[0143]
[Embodiment 8]
This embodiment is an embodiment different from the structure described in Embodiment 1, and a transistor having a structure in which a plurality of transistors are connected in series is formed by using an impurity region of one conductivity type as a wiring. The present invention relates to an invention characterized by This embodiment discloses that a transistor having a plurality of channel formation regions between a source region and a drain region can be obtained, and shows a further embodiment of the present invention.
[0144]
FIG. 34 is used for the description. FIG. 34A is a top view, and FIGS. 34B and 34C are cross-sectional views of corresponding portions. In addition, it is a figure corresponding to the state of FIG. 31 in Embodiment 4. For the process to reach this state and the subsequent transistor formation process, Embodiment Mode 1 may be referred to.
[0145]
In FIG. 34A, reference numerals 451 and 452 denote a source region and a drain region of an n-channel thin film transistor, respectively, and reference numeral 453 denotes a channel formation region. Reference numeral 454 denotes a semiconductor region that functions as one electrode of a storage capacitor. In this case, three channel formation regions 453 are provided between the impurity regions 451 and 452, and the redundant design reduces the off current (also referred to as leakage current) when the thin film transistor is in the off state. It has become. Needless to say, this embodiment mode is not limited to the structure of the transistor.
[0146]
Note that this embodiment is merely an example, and in the present invention, a technical idea that an impurity region of one conductivity type can be used as a wiring as well as an electrode is disclosed. Therefore, it may be combined with any technique disclosed in the first to sixth embodiments.
[0147]
[Embodiment 9]
In the transistor of the present invention, by providing a conductive layer on the lower layer side, a so-called substrate bias can be applied. The method for manufacturing the transistor is in accordance with Embodiment Mode 3 or 4, and the difference will be described with reference to FIGS.
[0148]
In FIG. 16A, a silicon nitride film is formed as a first insulating film 802 over a substrate, and a tungsten film 803 is formed thereon by a sputtering method. In particular, when a silicon nitride film is formed by a high frequency sputtering method, a dense film can be formed. The second insulating film 804 is formed using a silicon oxide film. The silicon oxide film forms a recess as shown in the figure by etching, but it can be easily processed because the selectivity with the underlying tungsten film is about 30.
[0149]
Over this, a silicon oxynitride film and an amorphous silicon film 806 are successively formed as a third insulating film 805, and the amorphous semiconductor film 806 is melted and crystallized, as shown in FIG. A silicon film 807 is formed. After that, as shown in FIG. 16C, a channel formation region 808 of the transistor is formed by etching, and a gate insulating film 809 and a gate electrode 810 are formed. Since the gate insulating film 809 is formed over the tungsten film 803, there is no short circuit with the gate electrode 810.
[0150]
In such a mode, when the tungsten film 803 is fixed to the ground potential, variation in threshold voltage of the transistor can be reduced. Further, when the same potential as that of the gate electrode 810 is applied to drive, the on-current can be increased.
[0151]
In order to enhance the heat dissipation effect, an aluminum oxynitride film (or aluminum nitride film) 811 is preferably formed over the tungsten film 803 as shown in FIG. The purpose of providing these films is to ensure the etching selectivity. That is, CHF _Three In order to remove the silicon oxide that is the second insulating film 804 with a fluorine-based etching gas and the like, and to prevent the underlying tungsten film 803 from being exposed, the silicon nitride film has a low selectivity, and the aluminum nitride film or the aluminum oxynitride Is suitable.
[0152]
The present embodiment discloses a configuration in which a conductive film is provided under the second insulating film that forms the convex portion and the concave portion to achieve a heat dissipation effect and threshold control during actual operation. Combinations with the configurations disclosed in Embodiments 1 to 6 are possible, and the effects described in this embodiment can be imparted by combining them.
[0153]
[Embodiment 10]
In this embodiment, an example in which part of the crystalline semiconductor film 307 (a portion that becomes a channel formation region later) is etched to reduce the thickness before the step of forming the active layer 308 of the thin film transistor in Embodiment 3 is described. Show.
[0154]
First, according to the manufacturing method shown in Embodiment Mode 3, the state shown in FIG. 8 is obtained. Next, a resist mask is formed over the semiconductor region which later becomes the source region or the drain region in the crystalline semiconductor film 307.
[0155]
Then, the crystalline semiconductor film 307 is etched by a dry etching method or a wet etching method using the resist mask as a mask, so that the third insulating film 305 serving as a base is exposed. By this step, the crystalline semiconductor film can be selectively left only in the recess. Further, the crystalline semiconductor film remains with the original thickness under the resist mask. This embodiment mode is characterized in that a crystalline semiconductor film is used as a channel formation region of a thin film transistor, and the crystalline semiconductor film is used as a source region or a drain region of the thin film transistor.
[0156]
Note that the etching step may use not only a chemical method but also a mechanical polishing method such as CMP (Chemical Mechanical Polishing). Moreover, you may use a chemical method and a mechanical method together.
[0157]
According to the present embodiment, since the channel formation region can be formed in a self-aligned manner by the second insulating film 303, the channel formation region is erroneously formed on the convex portion of the second insulating film due to the pattern shift. This can prevent the occurrence of crystal grain boundaries in the channel formation region.
[0158]
As for the subsequent steps, it is only necessary to refer to the steps after FIG. 10 of the third embodiment, and thus the description in the present embodiment is omitted. Note that this embodiment mode can be freely combined with any of Embodiment Modes 1 to 7.
[0159]
[Embodiment 11]
In this embodiment mode, a liquid crystal display panel and an organic EL (electroluminescence) panel are given as examples of the semiconductor device of the present invention, and an example in which the present invention is applied to each pixel structure is shown. The organic EL display panel is sometimes called an organic light emitting diode display panel (OLED), but refers to the same object.
[0160]
FIG. 35A illustrates an example of a pixel structure of a liquid crystal display panel. In FIG. 35A, a TFT 503 is provided as a switching element at an intersection of the gate line 501 and the data line 502. One end of the TFT 503 is connected to the data line 502, and the other end is connected to the storage capacitor (Cs) 504 and the liquid crystal element 505. This structure is the same as the pixel structure of the liquid crystal display device described in Embodiment Mode 3, and the present invention is very useful in forming the TFT 503 and the storage capacitor 504. That is, particularly when the liquid crystal display panel is a transmissive type, it is essential to reduce the element size in order to increase the aperture ratio. As described in Embodiment 3, the storage capacitor 504 has an occupied area. Although it is small, charges can be accumulated at high density.
[0161]
FIG. 35B illustrates an example of a pixel structure of an organic EL display panel. In FIG. 35B, a switching TFT 513 is provided as a switching element at the intersection of the gate line 511 and the data line 512. One end of the switching TFT 513 is connected to the data line 512, and the other end is connected to the storage capacitor (Cs) 514 and the gate of the driving TFT 515. The drain of the driving TFT 515 is connected to the light emitting element 516, and the source is connected to the power supply line 517. In this structure, the thin film transistor obtained by implementing the present invention can be used as both the switching TFT 513 and the driving TFT 515. Further, as described in Embodiment Mode 4, the storage capacitor 514 can accumulate charges with high density even though the occupation area is small.
[0162]
There are various examples of the circuit structure of the organic EL display panel, but the present invention can be applied to any circuit structure. Specifically, a driving method for holding the power supply line 517 at a constant voltage or a driving method for holding at a constant current may be used. The present invention can also be applied to a pixel structure described in Japanese Patent Application Laid-Open No. 2001-343933 or Japanese Patent Application No. 2001-289983 by the present applicant.
[0163]
As described above, the present invention is a very useful technique in a semiconductor device in which a capacitor element needs to be formed over a substrate, particularly a display panel having a pixel portion, and is not limited to the two examples described above. The present invention can be applied to various types of semiconductor devices. Note that this embodiment can be combined with any of Embodiments 1 to 6.
[0164]
[Embodiment 12]
In this embodiment mode, a dynamic random access memory (DRAM) and a capacitive DA converter (C-DAC) are given as examples of the semiconductor device of the present invention, and examples in which the present invention is applied to respective circuit configurations are shown.
[0165]
FIG. 36A illustrates an example of a circuit configuration of a DRAM. In FIG. 36A, a TFT 523 is provided as a switching element at the intersection of the word line 521 and the bit line 522. One end of the TFT 523 is connected to the bit line 522, and the other end is connected to the storage capacitor (Cs) 524. This configuration is similar to the pixel structure of the liquid crystal display device described in Embodiment 3, and in reality, it is integrated like a pixel to constitute a memory circuit. The present invention is very useful in forming the TFT 523 and forming the storage capacitor 524. That is, in view of the current situation where memory miniaturization is required, how to reduce the exclusive area is the key to integration. As described in Embodiment 4, the storage capacitor 524 has an occupied area. Although it is small, charges can be accumulated at high density.
[0166]
FIG. 36B shows an example of a C-DAC circuit configuration, which corresponds to a 3-bit (D0, D1, D2) input line. To explain one bit, a circuit having an inverter 532, two transfer gates 533, and a capacitor 534 as basic components is provided corresponding to the input line 531. Capacitance elements 534 to 536 are provided in the basic circuits corresponding to these three-bit input lines. When the capacitance of the capacitance element 534 is represented by C, the capacitance of the capacitance element 535 is 2C, and the capacitance of the capacitance element 536 is There is a relationship represented by 4C.
[0167]
The digital signals input to the input lines D0, D1, and D2 are finally output as analog signals from the output line 537. Reference numeral 538 denotes a reset circuit formed by combining an inverter and a transfer gate.
[0168]
When such a C-DAC circuit is configured, the capacitance elements 534 to 536 have the same inter-electrode distance and the same dielectric constant of the dielectric, so that the capacitance can be set to have a relationship of C, 2C, and 4C. The larger the is, the larger the occupation area of the capacitive element is. If a capacitive element can be obtained by implementing the present invention in such a case, a necessary and sufficient capacitance can be secured while preventing an increase in occupied area, and a highly integrated C-DAC circuit can be obtained. It becomes possible.
[0169]
As described above, the present invention is a very useful technique even in a semiconductor device in which a capacitor element needs to be formed over a substrate, particularly a display device having a memory using a capacitor, and is limited to the above two examples. In addition, the present invention can be applied to various types of semiconductor devices. Note that this embodiment can be combined with any of Embodiments 1 to 7. In particular, in the semiconductor device described in Embodiment 7, the present invention is very useful when forming a pixel portion, a driver circuit portion, and a memory portion over the same substrate.
[0170]
[Embodiment 13]
The present invention can be applied to various semiconductor devices, and the form of a display panel manufactured based on Embodiment Modes 1 to 12 will be described. Note that specific examples of the display panel described in this embodiment include a display panel using a transistor as a semiconductor element, such as a liquid crystal display panel, an EL (electroluminescence) display panel, or a display panel for FED (field emission display). . Of course, these display panels include those distributed in the market as modules.
[0171]
In FIG. 18, a substrate 900 includes a pixel portion 902, gate signal side driver circuits 901a and 901b, a data signal side driver circuit 901c, an input / output terminal portion 908, and a wiring or a wiring group 917.
[0172]
The seal pattern 940 is a pattern for creating a sealed space between the counter substrate 920 and the substrate 900. The liquid crystal display panel encloses liquid crystal, and the EL panel protects the EL material (especially organic EL material) from the outside air. Play a role. The gate signal side driver circuits 901a and 901b, the data signal side driver circuit 901c, and a wiring or a wiring group 917 that connects the driver circuit portion and the input terminal may partially overlap. In this way, the area of the frame region (the peripheral region of the pixel portion) of the display panel can be reduced. An FPC (flexible printed circuit) 936 is fixed to the external input terminal portion.
[0173]
Furthermore, a chip on which various logic circuits, high-frequency circuits, memories, microprocessors, media processors / DSPs (Digital Signal Processors), graphics LSIs, cryptographic LSIs, amplifiers, and the like are formed using transistors obtained by implementing the present invention. 950 may be mounted. These functional circuits are formed with design rules different from those of the pixel portion 902, the gate signal side drive circuits 901a and 901b, and the data signal side drive circuit 901c. Specifically, a design rule of 1 μm or less is applied. The Note that the external input terminal portion and the chip 950 are preferably protected by a resin (Mole resin or the like) 937. The mounting method is not limited, and a method using a TAB tape, a COG (chip on glass) method, or the like can be applied.
[0174]
Note that in this embodiment, FIGS. 13A and 13B are suitable as the gate structure of the transistor. For example, the transistor described in any of Embodiments 3 to 4 can be used as a switching element of the pixel portion 902, and further as an active element constituting the gate signal side driver circuits 901a and 901b and the data signal side driver circuit 901c. Of course, this embodiment shows an example of a display panel obtained by carrying out the present invention, and is not limited to the configuration of FIG.
[0175]
[Embodiment 14]
In this embodiment mode, an example in which a semiconductor device is manufactured by implementing the present invention using a base having a flexible last name (typically, a plastic base or a plastic film) as a supporting base is shown. For each circuit configuration formed on the substrate, the configuration described with reference to FIG. 18 in Embodiment 13 can be selected. Furthermore, in addition to being thin and lightweight, a semiconductor device using a flexible base can be applied to a display having a curved surface, a show window, and the like. Therefore, the application is not limited to portable devices, and the range of applications is diverse.
[0176]
By the way, when the substrate is non-planar, the problem is how much the curvature can be increased. When the curvature of the base is increased, a situation occurs in which the semiconductor element formed on the insulating film cannot obtain desired characteristics due to the stress generated in the insulating film formed on the base. This tendency is particularly strong as the thickness of the insulating film increases.
[0177]
Therefore, as in this embodiment, when the present invention is applied to a flexible substrate, the longitudinal direction of the insulating film extending in a linear stripe pattern (the Y-axis direction in FIG. 2A) and It is preferable to make the longitudinal direction of the generatrix on the curved surface of the substrate equal. Of course, the longitudinal direction of the generatrix on the curved surface of the substrate differs depending on the application of the semiconductor device. Therefore, when incorporating the semiconductor device into an electronic device or attaching it to a show window, it may be used with the above points in mind. It means that it is preferable.
[0178]
FIG. 37 shows a state where a semiconductor device manufactured using a substrate having a flexible surname according to the embodiment of the present invention is bent. A pixel portion 602, a scanning line driver circuit 603, and a signal line driver circuit 604 are formed on the base body 601. A material that can withstand a processing temperature in a later process is used for the base 601. Typically, PET (polyethylene terephthalate), PES (polyethylene sulfite), PC (polycarbonate), or PEN (polyethylene naphthalate) may be used. In particular, PC has high heat resistance and is useful.
[0179]
In the scan line driver circuit 603 and the signal line driver circuit 604, the first crystallinity obtained by the implementation of the present invention is formed in the recesses provided between the insulating films 605 extending in a linear stripe pattern. A thin film transistor having a channel formation region using a semiconductor region is formed. The longitudinal direction of the insulating film 605 extending in a linear stripe pattern and the longitudinal direction of the bus bar on the curved surface of the base 601 coincide with the direction indicated by the arrow. By doing so, the above-described stress can be dispersed, and the influence of the stress on the thin film transistor can be reduced.
[0180]
Note that this embodiment is an example of a semiconductor device, and can be implemented by freely combining with Embodiments 1 to 13. In addition, the combination does not impair the effects of the other embodiments, and it can be said that the technical significance of carrying out the present invention is great on a flexible substrate on which it is difficult to form a semiconductor film with good crystallinity.
[0181]
[Embodiment 15]
Various electronic devices can be completed using the present invention. Examples thereof include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, television receivers, mobile phones, and the like. An example of these is shown in FIG. Note that the electronic device shown here is just an example, and the present invention is not limited to these applications.
[0182]
FIG. 19A illustrates an example in which a television receiver is completed by applying the present invention, which includes a housing 3001, a support base 3002, a display portion 3003, and the like. In addition to the display portion 3003, a transistor manufactured according to the present invention can be formed using various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, and graphics LSIs on a glass substrate. According to the invention, a television receiver can be completed.
[0183]
FIG. 19B shows an example of a video camera completed by applying the present invention, which includes a main body 3011, a display portion 3012, an audio input portion 3013, an operation switch 3014, a battery 3015, an image receiving portion 3016, and the like. . In addition to the display portion 3012, various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, and graphics LSIs can be formed over the glass and incorporated in the transistor manufactured according to the present invention. A video camera can be completed by the invention.
[0184]
FIG. 19C illustrates an example in which a laptop personal computer is completed by applying the present invention, which includes a main body 3021, a housing 3022, a display portion 3023, a keyboard 3024, and the like. In addition to the display portion 3023, a transistor manufactured according to the present invention can be formed using various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, and cryptographic LSIs on a glass substrate. The personal computer can be completed according to the present invention.
[0185]
FIG. 19D shows an example in which a PDA (Personal Digital Assistant) is completed by applying the present invention, which includes a main body 3031, a stylus 3032, a display portion 3033, operation buttons 3034, an external interface 3035, and the like. In addition to the display portion 3033, various transistors, such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, and cryptographic LSIs, can be formed over a glass and manufactured by the present invention. According to the present invention, a PDA can be completed.
[0186]
FIG. 19E is an example in which a sound reproducing device is completed by applying the present invention, specifically, an in-vehicle audio device, which includes a main body 3041, a display portion 3042, operation switches 3043, 3044, and the like. Has been. In addition to the display portion 3042, a transistor manufactured according to the present invention can include various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, and amplifier circuits formed on glass. The audio device can be completed according to the present invention.
[0187]
FIG. 19F is an example in which a digital camera is completed by applying the present invention. A main body 3051, a display portion (A) 3052, an eyepiece portion 3053, an operation switch 3054, a display portion (B) 3055, a battery 3056. Etc. Transistors manufactured according to the present invention include a display portion (A) 3052 and a display portion (B) 3055 as well as various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, and cryptographic LSIs. Can be formed and incorporated on glass, and a digital camera can be completed by the present invention.
[0188]
FIG. 19G illustrates an example in which a cellular phone is completed by applying the present invention, which includes a main body 3061, an audio output portion 3062, an audio input portion 3063, a display portion 3064, operation switches 3065, an antenna 3066, and the like. Yes. In addition to the display portion 3064, the transistor manufactured by the present invention includes various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, cryptographic LSIs, and mobile phone LSIs formed on glass. The mobile phone can be completed according to the present invention.
[0189]
[Embodiment 16]
In this embodiment mode, a structure of a laser irradiation apparatus used for carrying out the present invention will be described with reference to FIG. Reference numeral 11 denotes a laser oscillation device. In FIG. 20, two laser oscillators are used, but the number of laser oscillators is not limited to this number, and may be three, four, or more.
[0190]
Further, the laser oscillation device 11 may use a chiller 12 to keep the temperature constant. The chiller 12 is not necessarily provided. However, by keeping the temperature of the laser oscillation device 11 constant, it is possible to suppress the energy of the output laser light from varying depending on the temperature.
[0191]
Reference numeral 14 denotes an optical system, which can focus the laser beam by changing the optical path output from the laser oscillation device 11 or processing the shape of the laser beam. Furthermore, in the laser irradiation apparatus of FIG. 20, the laser beams of the laser beams output from the plurality of laser oscillation apparatuses 11 can be combined by the optical system 14 by overlapping a part thereof.
[0192]
Note that an AO modulator 13 that can primarily and completely shield the laser light may be provided in the optical path between the substrate 16 that is the object to be processed and the laser oscillation device 11. Further, instead of the AO modulator, an attenuator (light quantity adjustment filter) may be provided to adjust the energy density of the laser light.
[0193]
Further, a means (energy density measuring means) 20 for measuring the energy density of the laser beam output from the laser oscillation device 11 is provided in the optical path between the substrate 16 that is the object to be processed and the laser oscillation device 11 for measurement. The computer 10 may monitor the change in energy density over time. In this case, the output from the laser oscillation device 10 may be increased so as to compensate for the attenuation of the energy density of the laser beam.
[0194]
The combined laser beam is applied to the substrate 16 as the object to be processed through the slit 15. The slit 15 is preferably formed of a material that can block the laser beam and that is not deformed or damaged by the laser beam. The slit 15 has a variable slit width, and the width of the laser beam can be changed according to the width of the slit.
[0195]
Note that the shape of the laser beam on the substrate 16 of the laser beam oscillated from the laser oscillation device 11 when not passing through the slit 15 differs depending on the type of laser, and can also be formed by an optical system.
[0196]
The substrate 16 is placed on the stage 17. In FIG. 20, the position control means 18 and 19 correspond to means for controlling the position of the laser beam on the object to be processed, and the position of the stage 17 is controlled by the position control means 18 and 19. In FIG. 20, the position control means 18 controls the position of the stage 17 in the X direction, and the position control means 19 controls the position of the stage 17 in the Y direction.
[0197]
Further, the laser irradiation apparatus of FIG. 20 has a computer 10 having both storage means such as a memory and a central processing unit. The computer 10 controls the position control means 18 and 19 so as to control the oscillation of the laser oscillating device 151, determine the scanning path of the laser light, and scan the laser beam of the laser light according to the determined scanning path. The substrate can be moved to a predetermined position.
[0198]
In FIG. 20, the position of the laser beam is controlled by moving the substrate, but it may be moved using an optical system such as a galvanometer mirror, or both.
[0199]
Further, in FIG. 20, the width of the slit 15 can be controlled by the computer 10, and the width of the laser beam can be changed according to the mask pattern information. Note that the slit is not necessarily provided.
[0200]
Further, the laser irradiation apparatus may include a means for adjusting the temperature of the object to be processed. Further, since the laser light is light having high directivity and energy density, a damper may be provided to prevent the reflected light from being irradiated to an inappropriate place. The damper desirably has a property of absorbing reflected light, and cooling water may be circulated in the damper to prevent the temperature of the partition wall from rising due to absorption of the reflected light. Further, the stage 157 may be provided with means for heating the substrate (substrate heating means).
[0201]
When the marker is formed by a laser, a marker laser oscillation device may be provided. In this case, the computer 10 may control the oscillation of the marker laser oscillator. Further, in the case where a marker laser oscillation device is provided, an optical system for condensing the laser beam output from the marker laser oscillation device is separately provided. The laser used for forming the marker is typically a YAG laser or CO. ₂ A laser or the like can be mentioned, but it is of course possible to form using other lasers.
[0202]
Further, one CCD camera 21 may be provided for positioning using the marker, and in some cases, several CCD cameras 21 may be provided. The CCD camera means a camera using a CCD (charge coupled device) as an image sensor. Further, the substrate may be aligned by recognizing the pattern of the insulating film or the semiconductor film by the CCD camera 21 without providing the marker. In this case, the positional information of the substrate is grasped by comparing the pattern information of the insulating film or semiconductor film by the mask inputted to the computer 10 with the actual pattern information of the insulating film or semiconductor film collected by the CCD camera 21. can do. In this case, it is not necessary to provide a marker separately.
[0203]
In addition, the laser light incident on the substrate is reflected by the surface of the substrate and returns to the same optical path as the incident light, which is so-called return light, but the return light is a change in laser output and frequency, rod breakage, etc. Adverse effects. Therefore, an isolator may be installed in order to remove the return light and stabilize the oscillation of the laser.
[0204]
Note that FIG. 20 shows the configuration of a laser irradiation apparatus provided with a plurality of laser oscillation apparatuses, but there is an advantage that the optical system can be easily designed by doing so. In the present invention, it is preferable to use a linear laser beam particularly from the viewpoint of improving throughput when the amorphous semiconductor film is melted. However, since the optical design becomes very precise when the longer length direction (X-axis direction in FIG. 3) becomes longer, the burden of optical design can be reduced by using a plurality of linear laser beams in a superimposed manner. Can do.
[0205]
For example, it is possible to optically combine a plurality of laser beams oscillated from a plurality of laser oscillation devices to form one linear laser beam. FIG. 21A shows an irradiation cross section of each laser beam. Here, a case where the laser light irradiation area has an elliptical shape is taken as an example, but there is no difference depending on the shape.
[0206]
The shape of the laser light varies depending on the type of laser, and can also be shaped by an optical system. For example, the shape of a laser beam emitted from a Lambda XeCl excimer laser (wavelength 308 nm, pulse width 30 ns) L3308 is a rectangular shape of 10 mm × 30 mm (both half-value width in the beam profile). The shape of the laser light emitted from the YAG laser is circular if the rod shape is cylindrical, and rectangular if it is slab type. By further shaping such laser light with an optical system, laser light of a desired size can be produced.
[0207]
FIG. 21B shows the energy density distribution of the laser light in the long axis direction (X-axis direction) of the laser light shown in FIG. The laser beam shown in FIG. 21A is 1 / e of the peak value of the energy density in FIG. ² This corresponds to a region satisfying the energy density of. The distribution of the energy density of the laser beam having an elliptical laser beam becomes higher toward the center O of the ellipse. As described above, in the laser light illustrated in FIG. 21A, the energy density in the central axis direction follows a Gaussian distribution, and a region where it can be determined that the energy density is uniform becomes narrow.
[0208]
Next, FIG. 21C shows an irradiation cross-sectional shape of the linear laser light when the two laser lights shown in FIG. Note that FIG. 21C illustrates the case where one linear laser beam is formed by superimposing two laser beams, but the number of laser beams to be superimposed is not limited thereto.
[0209]
As shown in FIG. 21C, the laser beams are synthesized by matching the major axes of the ellipses and overlapping a part of the laser beams to form one linear laser beam 30. . Hereinafter, a straight line obtained by connecting the centers O of the ellipses will be referred to as a central axis of the laser beam 30.
[0210]
FIG. 21D shows a distribution of energy density in the direction of the central axis y of the combined linear laser light shown in FIG. Note that the laser light illustrated in FIG. 21C is 1 / e of the peak value of the energy density in FIG. ² This corresponds to a region satisfying the energy density of. The energy density is added at the portion where the laser beams before synthesis overlap. For example, as shown in the figure, when the energy densities L1 and L2 of the overlapping laser beams are added, the energy density peak value L3 of each laser beam is approximately equal, and the energy density is flattened between the centers O of the ellipses. .
[0211]
Note that, when L1 and L2 are added, it is ideal to be equal to L3, but in reality, it is not necessarily equal. The allowable range of deviation between the value obtained by adding L1 and L2 and the value L3 can be set as appropriate by the designer.
[0212]
When the laser beam is used alone, the energy density follows a Gaussian distribution, so that it is difficult to irradiate the entire semiconductor film in contact with the flat portion of the insulating film with a uniform energy density. However, as can be seen from FIG. 21D, by superimposing a plurality of laser beams and complementing each other with a low energy density, energy can be obtained rather than using a plurality of laser beams without overlapping. The region having a uniform density is enlarged, and the crystallinity of the semiconductor film can be increased efficiently.
[0213]
In addition, the distribution of energy density in BB ′ and CC ′ is slightly smaller than that in CC ′, but it can be regarded as almost the same size. 1 / e of the peak value of the laser beam ² The shape of the synthesized linear laser beam in the region satisfying the energy density of can be said to be linear.
[0214]
Note that a region having a low energy density exists in the vicinity of the outer edge of the irradiation region of the synthesized linear laser light 30. If the region is used, there is a possibility that the crystallinity may be lost. Therefore, it is preferable that the outer edge of the linear laser beam is not used as in the case of using the slit 15 in FIG.
[0215]
The laser irradiation apparatus described in the present embodiment can be used for performing laser light irradiation of the present invention, and can be used for implementing any one of the first to tenth embodiments. In addition, although there is a merit to obtain a linear laser beam by synthesis, the cost of the optical system and the laser oscillation device increases. Therefore, a desired linear laser beam can be obtained with one laser oscillation device and one optical system. If it can be obtained, there is no problem in using such a laser irradiation apparatus in the practice of the present invention.
[0216]
【Example】
[Example 1]
In this example, a crystalline semiconductor film obtained by carrying out the present invention is shown. In addition, since the present Example performed the crystallization process according to Embodiment 2 and 3, it demonstrates with reference to FIGS.
[0217]
In this embodiment, a silicon nitride oxide film with a thickness of 50 nm is used as the first insulating film 302 in FIG. 6, and a silicon oxynitride film with a thickness of 200 nm is used as the second insulating film 303. In this case, when the second insulating film 303 was etched, the underlying first insulating film 302 was also etched, and as a result, the height corresponding to the step d in FIG. 1 was 250 nm. The width of the second insulating film 303 (corresponding to W1 in FIG. 1) was 0.5 μm, and the distance between adjacent portions (corresponding to W2 in FIG. 1) was 0.5 μm.
[0218]
Further, a silicon oxynitride film having a thickness of 20 nm is provided as the third insulating film 305 over the second insulating film 303, and then the amorphous semiconductor film 306 is continuously formed to a thickness of 150 nm without being released to the atmosphere. An amorphous silicon film was formed. The amorphous silicon film was crystallized using the crystallization technique of the second embodiment. Specifically, after a 10 ppm nickel acetate aqueous solution was held on the amorphous silicon film and crystallized by heat treatment at 550 ° C. for 4 hours, linear laser light was irradiated. The linear laser beam is YVO in continuous oscillation mode. _Four Using a laser oscillator, the output of 5.5 W of the second harmonic (wavelength 532 nm) was condensed into a linear laser beam by an optical system, and scanned at a speed of 50 cm / sec at room temperature.
[0219]
FIG. 25A is a TEM (transmission electron microscope) photograph in a state where the crystalline silicon film 307 is formed (the state shown in FIG. 8), and FIG. 25B is a schematic diagram thereof. The stacked body of the first insulating film 302 and the second insulating film 303 exists in a state of being completely buried under the crystalline silicon film 307.
[0220]
FIG. 26A is a cross-sectional TEM photograph in which the cross section of FIG. 25A is observed, and FIG. 26B is a schematic diagram thereof. A crystalline silicon film 307a is formed so as to be filled between the second insulating films 303 formed in a stripe pattern (concave portion), and crystals are formed on the upper surface portion (convex portion) of the second insulating film 303. A conductive silicon film 307b is formed.
[0221]
FIG. 27A is a cross-sectional TEM photograph in which the cross section of FIG. 26A is enlarged and observed, and FIG. 27B is a schematic diagram thereof. In the photograph, the third insulating film 305 is observed. No crystal grain boundaries or defects appearing inside the crystalline silicon film 307a are observed, and it can be seen that the crystalline silicon film 307a has extremely high crystallinity.
[0222]
In the present invention, the crystalline silicon film 307a with good crystallinity is used as a channel formation region, and the crystalline silicon film 307b with poor crystallinity is positively used as an electrode or wiring, so that high-speed operation is possible and current driving is performed. A thin film transistor or a thin film transistor group with high capability and small variation among a plurality of elements can be provided.
[0223]
[Example 2]
In this embodiment, when forming the second insulating films 103 to 105 shown in FIG. 1, an insulating film corresponding to the first insulating film is formed on the second insulating films 103 to 105 using the glass substrate as an etching stopper. An example is shown.
[0224]
In FIG. 39, first, second insulating films 853 to 895 are formed on a glass substrate 851 using silicon oxide or silicon oxynitride in a linear stripe pattern with a thickness of 10 to 3000 nm, preferably 100 to 2000 nm. Details are the same as in the first embodiment. Etching using buffered hydrofluoric acid or CHF _Three Performed by dry etching using In this example, CHF _Three Dry etching using gas is used. In this case, the gas flow rate is 30 to 40 sccm, the reaction pressure is 2.7 to 4.0 KPa, the applied power is 500 W, and the substrate temperature is 20 ° C.
[0225]
In the case of this embodiment, it is preferable to use a material having a high selection ratio with the second insulating film (silicon oxide film) (for example, a 1737 glass substrate manufactured by Corning) as the glass substrate 851. This is because the glass substrate 851 can be used as an etching stopper when the second insulating films 853 to 855 are formed if the selectivity is high.
[0226]
After the second insulating films 853 to 855 are formed, the second insulating films 853 to 855 are covered with a first insulating film 852 made of silicon nitride, silicon oxynitride, silicon oxynitride, or a laminated film thereof, and an amorphous semiconductor is further formed thereon. The film 856 is formed in the state of FIG. In this embodiment, a silicon oxynitride film and a silicon oxynitride film are stacked as a first insulating film on a second insulating film, and an amorphous semiconductor film is formed thereon. The details of the first insulating film 852 and the amorphous semiconductor film 856 may be referred to the description in Embodiment Mode 1. In addition, steps after FIG. 39B may be performed in accordance with Embodiment 1, and thus description thereof is omitted here.
[0227]
According to this embodiment, since the selection ratio between the glass substrate 851 and the second insulating films 853 to 855 can be made sufficiently high, the second insulating films 853 to 855 are formed in a linear stripe pattern. The process margin is improved. In addition, the flatness is improved without causing problems such as erosion at the lower ends of the second insulating films 853 to 855.
[0228]
[Example 3]
In this embodiment, when the second insulating films 103 to 105 shown in FIG. 1 are formed, the glass substrate is covered with the second insulating films 103 to 105, and the insulating film corresponding to the first insulating film is formed thereon. An example of forming a film is shown.
[0229]
In FIG. 38, first, second insulating films 953 to 955 are formed on a glass substrate 951 with silicon oxide or silicon oxynitride to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm. Then, the second insulating film is formed in a linear stripe pattern on the glass substrate. At this time, the second insulating film is not etched to reach the glass substrate, but is etched while leaving a certain thickness on the glass substrate. Details are the same as in the first embodiment. Etching using buffered hydrofluoric acid or CHF _Three Performed by dry etching using In this example, CHF _Three Dry etching using gas is used. In this case, the gas flow rate is 30 to 40 sccm, the reaction pressure is 2.7 to 4.0 KPa, the applied power is 500 W, and the substrate temperature is 20 ° C.
[0230]
When the second insulating films 953 to 955 are formed, the second insulating films 953 to 955 are covered with a first insulating film 952 made of silicon nitride, silicon oxynitride, silicon oxynitride, or a laminated film thereof, and further an amorphous semiconductor is formed thereon. The film 956 is formed in the state shown in FIG. In this embodiment, a silicon nitride oxide film and a silicon oxynitride film are stacked as a first insulating film on a second insulating film, and an amorphous semiconductor film is formed thereon. The details of the first insulating film 952 and the amorphous semiconductor film 956 may be referred to the description in Embodiment Mode 1. In addition, steps after FIG. 38B may be performed in accordance with Embodiment 1, and thus description thereof is omitted here.
[0231]
According to this embodiment, since the glass substrate 951 is covered with the second insulating films 953 to 955, the second insulating film such as silicon oxynitride can be expected to have a blocking effect on sodium (Na). It is effective as a pollution countermeasure.
【The invention's effect】
As described above, a linear stripe pattern having a concavo-convex shape is formed by an insulating film, an amorphous semiconductor film is deposited thereon, and crystallized through a molten state by irradiation with laser light to form a recess. By pouring and solidifying the semiconductor, strain or stress accompanying crystallization can be concentrated in a region other than the concave portion, and a region having poor crystallinity such as a crystal grain boundary can be selectively formed.
[0232]
Then, a semiconductor element such as a transistor, in particular, a location of a channel formation region thereof can be designated to form a crystalline semiconductor film having no crystal grain boundary. As a result, it is possible to eliminate a factor in which the characteristics vary due to inadvertently interposed crystal grain boundaries and crystal defects, and it is possible to form a transistor or a transistor element group having a small characteristic variation.
[0233]
As described above, the present invention can operate at high speed by using a crystalline semiconductor film with good crystallinity as a channel formation region and positively using a crystalline semiconductor film with poor crystallinity as an electrode or a wiring. It is possible to provide a semiconductor device having a high current driving capability and a small variation among a plurality of elements or a semiconductor device configured by integrating the semiconductor element groups with a high degree of integration.
[0234]
Furthermore, it is possible to form a semiconductor element that can operate at high speed, has a high current drive capability, and has a small variation among a plurality of elements, and at the same time, can form a storage capacitor having a small charge area and a high density charge retention capability. Therefore, in a semiconductor device that needs to use a capacitor element, it is possible to achieve effects such as improvement in integration degree in a memory and improvement in an effective display area in a pixel portion.
[Brief description of the drawings]
FIG. 1 is a perspective view illustrating a crystallization method of the present invention.
FIG. 2 is a perspective view illustrating a crystallization method of the present invention.
FIG. 3 is a perspective view illustrating a crystallization method according to the present invention.
FIG. 4 is a perspective view illustrating a crystallization method of the present invention.
FIG. 5 is a vertical cross-sectional view illustrating the relationship between the shape of an opening in crystallization and the form of a crystalline semiconductor film.
FIGS. 6A and 6B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 7A and 7B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 8A and 8B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 9A and 9B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 10A and 10B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 11A and 11B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
12A to 12C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
FIG. 13 is a vertical cross-sectional view illustrating an example of a gate structure that can be used in the transistor of the present invention.
FIGS. 14A and 14B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 15A and 15B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIG. 16 is a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
FIGS. 17A to 17C are vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIG. 18 is a diagram showing an example of an external view of a semiconductor device of the present invention.
FIG. 19 is a diagram showing a specific example of an electronic device according to the invention.
FIG. 20 is a diagram showing a laser irradiation apparatus used for carrying out the present invention.
FIG. 21 is a diagram showing a configuration of a laser beam used for carrying out the present invention.
FIGS. 22A and 22B are a TEM photograph and a schematic diagram of an observed top surface of a crystalline silicon film obtained by carrying out the present invention after secco-etching. FIGS.
FIGS. 23A and 23B are a TEM photograph and a schematic diagram of an observed top surface of a crystalline silicon film obtained by carrying out the present invention after secco-etching. FIGS.
FIG. 24 is EBSP mapping data showing the orientation of crystals formed in the recesses.
FIG. 25 is a TEM photograph of an upper surface of a crystalline silicon film obtained by carrying out the present invention and a schematic diagram thereof.
FIGS. 26A and 26B are a TEM photograph and a schematic view of a cross section of a crystalline silicon film obtained by carrying out the present invention. FIGS.
FIG. 27 is a TEM photograph of an observed cross section of a crystalline silicon film obtained by carrying out the present invention, and a schematic diagram thereof.
28A to 28C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
29A to 29C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
30A to 30C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
FIGS. 31A to 31C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
FIGS. 32A and 32B are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention. FIGS.
33A and 33B are a cross-sectional view and a schematic view of a storage capacitor obtained by implementing the present invention.
34A to 34C are a top view and a vertical cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
FIG 35 shows an example of a semiconductor device of the invention.
FIG 36 illustrates an example of a semiconductor device of the invention.
FIG. 37 is a diagram showing an example of an external view of a semiconductor device of the present invention.
FIG. 38 is a perspective view illustrating a crystallization method of the present invention.
FIG. 39 is a perspective view illustrating a crystallization method of the present invention.

Claims (12)

A semiconductor device configured by integrating semiconductor elements formed on a substrate having an insulating surface,
Chi also a predetermined interval on said substrate, adjacent two or more island-shaped insulating film is shaped on one island is formed an insulating film group, and the one by one on one island-shaped insulating film group and the other of the island-shaped insulating film group island shaped insulating film is formed on so that oppose each other with a predetermined interval for,
The first connected between the neighboring island-like insulating films of the other island-like insulating film group facing each other from between the neighboring island-like insulating films of the one island-like insulating film group. A crystalline semiconductor region of
The first island-shaped insulating film group is formed between adjacent island-shaped insulating film groups and between the other island-shaped insulating film groups facing each other. on the first crystalline semiconductor region, and the second crystalline semiconductor regions formed in said top of one island-shaped insulating film group and the other of the island-shaped insulating film group and,
A channel forming region which does not include the first grain boundaries than twin crystal formed on a part of the crystalline semiconductor region,
An impurity region in which a region other than the channel formation region of the first crystalline semiconductor region and the second crystalline semiconductor region is doped with an impurity of one conductivity type;
A gate insulating film and a gate electrode formed on the channel formation region;
Consists of at least
Said top surface of said impurity region of the second crystalline semiconductor region is flattened, and the flattened said channel forming region formed between the impurity region and the first crystalline semiconductor A semiconductor device, wherein the semiconductor device is formed higher than an upper surface of the impurity region formed in the region . A semiconductor device configured by integrating semiconductor elements formed on a substrate having an insulating surface,
Chi also a predetermined interval on said substrate, adjacent two or more island-shaped insulating film is shaped on one island is formed an insulating film group, and the one by one on one island-shaped insulating film group and the other of the island-shaped insulating film group island shaped insulating film is formed on so that oppose each other with a predetermined interval for,
The first connected between the neighboring island-like insulating films of the other island-like insulating film group facing each other from between the neighboring island-like insulating films of the one island-like insulating film group. A crystalline semiconductor region of
The first island-shaped insulating film group is formed between adjacent island-shaped insulating film groups and between the other island-shaped insulating film groups facing each other. on the first crystalline semiconductor region, and the second crystalline semiconductor regions formed in said top of one island-shaped insulating film group and the other of the island-shaped insulating film group and,
A channel forming region not including a crystal grain boundary other than a planar grain boundary formed in a part of the first crystalline semiconductor region ;
An impurity region in which a region other than the channel formation region of the first crystalline semiconductor region and the second crystalline semiconductor region is doped with an impurity of one conductivity type;
A gate insulating film and a gate electrode formed on the channel formation region;
Consists of at least
Said top surface of said impurity region of the second crystalline semiconductor region is flattened, and the flattened said channel forming region formed between the impurity region and the first crystalline semiconductor A semiconductor device, wherein the semiconductor device is formed higher than an upper surface of the impurity region formed in the region . According to claim 1 or claim 2, impurity regions the one conductivity type impurity is doped, and wherein a used as a wiring. In any one of claims 1 to 3, the impurity region in which the one conductivity type impurity is doped, and wherein a is a source region or a drain region. In any one of claims 1 to 4, wherein the semiconductor device includes a capacitive element,
The capacitive element includes a plurality of crystalline semiconductor regions provided in parallel;
An insulating film covering the plurality of crystalline semiconductor regions;
A semiconductor device comprising a wiring facing the plurality of crystalline semiconductor regions with the insulating film interposed therebetween. 6. The semiconductor device according to claim 5 , wherein a storage capacitor is formed by a side surface and an upper surface of the plurality of crystalline semiconductor regions. In claims 5 to 6, that the spacing of the plurality of crystalline semiconductor region adjacent and at 0.01μm than 2μm or less, the thickness of the plurality of crystalline semiconductor region is 0.01μm or more 3μm or less A semiconductor device characterized by the above. In any one of claims 1 to 7, wherein the substrate is a semiconductor device which is a glass substrate. In any one of claims 1 to 4, wherein the width of the one and the other of the island-shaped insulating film group adjacent direction of the island-shaped insulating film is at 0.1μm or 10μm or less, the one and the other The width of the crystalline semiconductor region formed between the island-shaped insulating film groups is 0.01 μm to 2 μm, and the film thickness of the one and the other island-shaped insulating film groups is 0.01 μm to 3 μm. A semiconductor device, wherein: In any one of claims 1 to 9, wherein the channel forming region, a laser toward the island-shaped insulating film group of the other side of the arranged facing from one island-shaped insulating film group A semiconductor device characterized by being crystallized by irradiation with light. In the claims 1 to any one of claims 1 0, impurity regions of the one conductivity type, on the one and the other of the island-shaped insulating film group, characterized in that a part including a crystal grain boundary Semiconductor device. In any one of claims 1 to 1 1, the thickness of the channel formation region, wherein a same approximate the thickness of the one and the other of the island-shaped insulating film group.

Images