JP2010118677A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device to suppress the threshold voltage low, when using, as a gate electrode, a metal film or a film of a metallic compound having a work function whose extent does not worsen the contactness while having thermal stability. <P>SOLUTION: A CMIS element includes an n-type MIS element and a p-type MIS element. In the n-type MIS element, a gate electrode 10 of a tantalum silicon nitride film is formed on a gate insulating film 9 of a hafnium aluminate film. Meanwhile, in the p-type MIS element, a threshold adjusting film 7 of an aluminum oxide film is formed on a gate insulating film 9 of a hafnium aluminate film. Moreover, on the threshold adjusting film 7, a gate electrode 11 of a tantalum silicon nitride film is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device that can suppress a threshold voltage of a MIS (Metal Insulator Semiconductor) element to a low level and a technique effective when applied to a manufacturing method thereof.

  Conventionally, in order to realize a low threshold voltage in both an n-type MOS element and a p-type MOS element of a complementary metal oxide semiconductor (CMOS) element, they have different work functions (in the case of polysilicon, Fermi level). A so-called dual gate is formed in which a gate electrode is formed using a material. That is, by introducing an n-type impurity and a p-type impurity into the polysilicon film forming the n-type MOS element and the p-type MOS element, respectively, the work function (Fermi of the gate electrode material of the n-type MOS element). The threshold voltage is lowered by setting the level) in the vicinity of the conduction band of silicon and setting the work function (Fermi level) of the gate electrode material of the p-type MOS element in the vicinity of the valence band of silicon.

  However, in recent years, with the miniaturization of CMOS elements, the gate insulating film has become thinner, and depletion of the gate electrode when a polysilicon film is used as the gate electrode cannot be ignored. That is, it has been necessary to reduce the electrical silicon oxide equivalent film thickness of the gate insulating film made of a silicon oxide film or the like to about 2 nm or less due to miniaturization, but in this case, it occurs in the gate electrode due to depletion of the gate electrode. Parasitic capacitance (capacitance with a thickness of about 0.3 nm) cannot be ignored. For this reason, use of a metal film instead of a polysilicon film as a gate electrode material has been studied (for example, see Patent Document 1).

JP 2002-118175 A (pages 3 to 6, FIG. 1)

  When a metal film is used as the gate insulating film, the metal film as the gate electrode material is required to have a predetermined work function in order to reduce the threshold voltage of the MOS element. For example, in order to keep the threshold value low, the n-type MOS element is required to be a metal material having a work function in the vicinity of 4.05 eV, which is the conduction band of silicon. On the other hand, a metal material having a work function in the vicinity of 5.17 eV, which is the valence band of silicon, is required for the p-type MOS element.

  However, the above-described metal material having a work function in the vicinity of 4.05 eV has poor thermal stability and has a problem that it reacts with the gate insulating film by heat treatment applied in the manufacturing process of the semiconductor device.

  In addition, the metal material having a work function in the vicinity of 5.17 eV described above has a problem in that the adhesiveness with the adjacent gate insulating film is badly separated.

  An object of the present invention is to suppress the threshold voltage to a low level when a metal film or a film made of a metal compound having a work function that does not deteriorate the adhesiveness while being thermally stable is used as a gate electrode. It is to provide a semiconductor device.

  Another object of the present invention is to provide a threshold voltage in the case where a metal film or a film made of a metal compound having a work function that does not deteriorate the adhesion while being thermally stable is used as a gate electrode. An object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the above-mentioned low.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  The present invention provides a film comprising (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, and (c) an insulator formed on the gate insulating film. It has a MIS element comprising a threshold adjustment film for adjusting a value voltage, and (d) a gate electrode made of a material containing a metal, which is formed on the threshold adjustment film. .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  When a metal film or a film made of a metal compound having a work function that does not deteriorate the adhesiveness while using thermal stability is used as the gate electrode, the threshold voltage can be suppressed low.

It is sectional drawing of the semiconductor device which is Embodiment 1 of this invention. 5 is a graph showing a flat band voltage when a threshold adjustment film is formed and when a threshold adjustment film is not formed. It is sectional drawing which showed the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; 7 is a cross-sectional view showing a semiconductor device in a modification of the first embodiment. FIG. 7 is a cross-sectional view showing a semiconductor device in a modification of the first embodiment. FIG. It is sectional drawing which showed the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18; FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 19; FIG. 21 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; It is the graph which showed the relationship between the temperature of heat processing, and a flat band voltage. FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
In the first embodiment, the present invention is applied to a CMIS (Complementary Metal Insulator Semiconductor) element.

  FIG. 1 is a cross-sectional view showing a CMIS element according to the first embodiment. In FIG. 1, in the CMIS element according to the first embodiment, an element isolation region 2 for isolating an element formation region is first formed on a semiconductor substrate 1 made of silicon single crystal. The element isolation region 2 separates an n-type MIS element formation region that forms an n-type MIS element and a p-type MIS element formation region that forms a p-type MIS element.

  A p-type well 3 into which a p-type impurity such as boron is introduced is formed in the semiconductor substrate 1 in the n-type MIS element formation region, while phosphorus or arsenic is present in the semiconductor substrate 1 in the p-type MIS element formation region. An n-type well 4 into which an n-type impurity such as is introduced is formed.

  A gate insulating film 9 is formed on predetermined regions of the p-type well 3 and the n-type well 4, and the gate insulating film 9 is formed of, for example, a hafnium aluminate film. This hafnium aluminate film is a so-called High-k film having a dielectric constant higher than that of the silicon oxide film, and has a dielectric constant ε of about 16.

  Conventionally, a silicon oxide film has been used as the gate insulating film 9 from the viewpoints of high insulation resistance, low leakage current, and excellent electrical and physical stability at the silicon-silicon oxide interface. . However, with the miniaturization of elements, the thickness of the gate insulating film 9 is required to be 2 nm or less. When such a thin gate oxide film is used, a so-called tunnel current is generated in which electrons flowing through the channel of the MOS element tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode. Therefore, a High-k film that can increase the physical film thickness by using a material having a dielectric constant higher than that of silicon oxide has been used. For example, since the dielectric constant of the silicon oxide film is about 4, when the above-described hafnium aluminate film having a dielectric constant of about 16 is used for the gate insulating film 9, the silicon oxide film has a thickness of about 1 nm to 2 nm. In order to obtain an equivalent capacity, the physical film thickness of the hafnium aluminate film can be about 4 nm to 8 nm.

Although the example in which the gate insulating film 9 is formed of a hafnium aluminate film has been shown, the present invention is not limited to this. For example, alumina (aluminum oxide), hafnia (hafnium oxide), zirconia (zirconium oxide), silicon nitride, La ₂ O ₃ may be formed from a film such as rare earth oxides such as. As described above, a high-k film is preferably used as the gate insulating film 9, but the present invention can be applied even when a silicon oxide film is used.

  A gate electrode 10 is formed on the gate insulating film 9 in the n-type MIS element forming region, while a threshold adjustment film 7 is formed on the gate insulating film 9 in the p-type MIS element forming region. Yes. A gate electrode 11 is formed on the threshold adjustment film 7. The gate electrodes 10 and 11 are made of a material containing metal. That is, the gate electrodes 10 and 11 are formed from a metal or a metal compound, and in the first embodiment, for example, are formed from a tantalum siliconitride film. This tantalum silicon nitride has a work function of 4.3 eV, which is between 4.05 eV and 5.17 eV, and thus has thermal stability and good film adhesion.

  The threshold adjustment film 7 is a film provided to suppress a threshold voltage (threshold voltage) in the p-type MIS element to be low, and is formed of, for example, an aluminum oxide film. The film thickness of the aluminum oxide film is preferably about 0.3 nm to about 2.0 nm, for example, from the viewpoint of miniaturizing the MIS element to be formed. Here, the threshold voltage is a gate voltage at which the drain current of the MIS element stops flowing.

  Thus, the present inventor has found that the threshold voltage in the p-type MIS element can be lowered by forming the aluminum oxide film between the gate insulating film 9 and the gate electrode 11. For example, in the case of p-type MIS, conventionally, a metal (or metal compound) material is selected from the viewpoint that the work function of the gate electrode material in contact with the gate insulating film is as close as possible to the valence band of silicon, The threshold voltage of the MIS type element was suppressed low. However, the present invention has been made from a completely different viewpoint. In other words, the work function of the material of the gate electrode in contact with the gate insulating film is not adjusted to a predetermined value, but the threshold is determined by forming a specific film made of an insulator between the gate insulating film and the gate electrode. It has been found that the value voltage can be suppressed low.

  In the above description, the threshold adjustment film 7 is formed of an aluminum oxide film. However, the threshold adjustment film 7 may be formed of, for example, an aluminum oxynitride film. That is, the first embodiment is a film made of (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, and (c) an insulator formed on the gate insulating film. A MIS element comprising: a threshold adjustment film for adjusting a threshold voltage; and (d) a gate electrode formed on the threshold adjustment film and made of a material containing a metal. The threshold adjustment film is formed of an aluminum oxide film or an aluminum oxynitride film.

  Next, sidewalls 16 are formed on both sides of the gate electrodes 10 and 11. In the n-type MIS element formation region, low-concentration n-type impurity diffusion layers 12 and 13 into which an n-type impurity such as phosphorus is introduced are formed below the side wall 16. High concentration n-type impurity diffusion layers 17 and 18 are formed beside the diffusion layers 12 and 13. As described above, the source region composed of the low-concentration n-type impurity diffusion layer 12 and the high-concentration n-type impurity diffusion layer 17 and the drain region composed of the low-concentration n-type impurity diffusion layer 13 and the high-concentration n-type impurity diffusion layer 18 are formed. Yes. In this way, an n-type MIS element is formed.

  Similarly, in the p-type MIS element formation region, a source region composed of a low-concentration p-type impurity diffusion layer 14 and a high-concentration p-type impurity diffusion layer 19, a low-concentration p-type impurity diffusion layer 15, and a high-concentration p-type impurity diffusion layer. A drain region made of 20 is formed. In this way, a p-type MIS element is formed.

  An interlayer insulating film 21 is formed on the n-type MIS element and the p-type MIS element formed on the semiconductor substrate 1, and the interlayer insulating film 21 includes source regions of the n-type MIS element and the p-type MIS element. A through hole 22 penetrating the drain region is formed.

  A titanium / titanium nitride film 23 is formed on the inner wall of the through hole 22, and a tungsten film 24 is embedded in the through hole 22 through the titanium / titanium nitride film 23 to form a plug. The titanium / titanium nitride film 23 has, for example, a function of suppressing diffusion of tungsten and a function of improving adhesiveness with the base.

  On the interlayer insulating film 21, a patterned wiring 28 made of a titanium / titanium nitride film 25, an aluminum film 26, and a titanium / titanium nitride film 27 is formed. Although not shown, a multilayer wiring is formed on the wiring 28 via a plug penetrating the interlayer insulating film.

  Next, threshold voltages of the n-type MIS element and the p-type MIS element having the above-described configuration will be described.

  FIG. 2 is a graph showing the relationship between the n-type MIS element and the flat band voltage of the p-type MIS element. The horizontal axis shows the material configuration of the gate insulating film and gate electrode of the MIS element, and the vertical axis shows the flat band voltage in volts (V).

  In the configuration in which a hafnium aluminate film is used for the gate insulating film 9 and a tantalum siliconitride film is used for the gate electrode 10 in FIG. 2, that is, the configuration of the n-type MIS element shown in FIG. Was about -0.65V.

  Here, the flat band voltage and the threshold voltage are expressed by predetermined formulas. Roughly speaking, when the flat band voltage is about −0.9V, the threshold voltage of the n-type MIS element is about 0V. The threshold voltage rises as the flat band voltage rises in the + direction. Therefore, when the flat band voltage is about −0.65V, the threshold voltage of the n-type MIS element is about 0.25V.

  On the other hand, when the flat band voltage is about 0.1 V, the threshold voltage of the p-type MIS element is about 0 V, and the threshold voltage increases as the flat band voltage decreases in the-direction. Accordingly, when the p-type MIS element has a configuration in which a hafnium aluminate film is used for the gate insulating film 9 and the gate electrode 11 made of a tantalum siliconitride film is formed on the gate insulating film 9, the threshold is used. The value voltage is about 0.75V.

  However, a hafnium aluminate film is used for the gate insulating film 9, a tantalum siliconitride film is used for the gate electrode 11, and a threshold adjustment film 7 made of an aluminum oxide film is formed between the gate insulating film 9 and the gate electrode 11. When the formed configuration, that is, the configuration of the p-type MIS element shown in FIG. 1, was taken, the flat band voltage was changed from about −0.65 V to about −0.32 V. That is, the flat band voltage could be shifted by about 0.33 V in the + direction. Thus, the fact that the flat band voltage can be shifted by about +0.33 V means that the threshold voltage of the p-type MIS element can be lowered by about 0.33 V, and the threshold value of the p-type MIS element. The voltage will be about 0.42V. However, in the case of this configuration, the threshold voltage of the n-type MIS element increases by about 0.33V.

  Therefore, as shown in FIG. 1, in the n-type MIS element, the gate electrode 10 made of a tantalum siliconitride film is formed on the gate insulating film 9 made of a hafnium aluminate film, whereas in the p-type MIS element, By adopting a configuration in which a threshold adjustment film 7 made of an aluminum oxide film is formed between a gate insulating film 9 made of a hafnium aluminate film and a gate electrode 11 made of a tantalum silicon nitride film, the n-type MIS element and the p Both threshold voltages of the type MIS element can be suppressed low.

  The reason why the flat band voltage is shifted in the positive direction by forming the threshold adjustment film 7 made of the aluminum oxide film between the gate insulating film 9 and the gate electrode 11 is that the negative band existing in the aluminum oxide film is present. It is inferred that the fixed charge has an effect. That is, it is considered that the flat band voltage is shifted in the positive direction because the aluminum oxide film has a relatively large amount of negative fixed charges. Therefore, it is presumed that the flat band voltage can be shifted in the positive direction as long as the film has a relatively large amount of negative fixed charges, not only the aluminum oxide film.

  Here, the fixed charge refers to a charge that is fixed without being moved by an electric field or the like. Note that the amount of fixed charges in the film may vary depending on the film production conditions.

  Next, an example of a method for manufacturing a CMIS element in the first embodiment will be described with reference to the drawings.

  First, as shown in FIG. 3, a semiconductor substrate 1 made of single crystal silicon is prepared. Then, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 using a thermal oxidation method or the like, and a silicon nitride film is formed on the silicon oxide film using a CVD method, for example. Thereafter, the silicon nitride film is patterned using a photolithography technique and an etching technique. The patterning is performed so that no silicon nitride film remains in a region where the element isolation region 2 is to be formed. Subsequently, an element isolation region 2 made of a silicon oxide film as shown in FIG. 4 is formed by a selective oxidation method utilizing the oxidation resistance of the silicon nitride film. Thereafter, the patterned silicon nitride film is removed.

  Next, after applying a photosensitive resist film on the semiconductor substrate 1, the resist film is patterned by exposure and development. The patterning is performed so as to selectively open the n-type MIS element formation region. Then, by using an ion implantation method as shown in FIG. 5, p-type impurities such as boron and boron fluoride are introduced into the n-type MIS element formation region of the semiconductor substrate 1 to form the p-type well 3. Similarly, an n-type well 4 is formed by introducing an n-type impurity such as phosphorus or arsenic into the p-type MIS element formation region of the semiconductor substrate 1 by using an ion implantation method.

Subsequently, as shown in FIG. 6, a hafnium aluminate film 5 is formed by using, for example, an ALD (Atomic Layer Deposition) method. Specifically, first, trimethylaluminum (Al (CH ₃ ) ₃ ) as a raw material is introduced onto the semiconductor substrate 1 heated to about 300 ° C. Then, after exhausting trimethylaluminum, water vapor (H ₂ 0) is introduced onto the semiconductor substrate 1 and exhausted. Subsequently, tetradimethylaminohafnium (Hf [N (CH ₃ ) ₂ ] ₄ ) is introduced onto the semiconductor substrate 1 heated to about 300 ° C. Thereafter, water vapor is introduced onto the semiconductor substrate 1 and exhausted. In this way, a hafnium aluminate film 5 of about 2 nm to 3 nm is formed. The hafnium aluminate film 5 may be formed using a CVD method or the like.

  Next, as shown in FIG. 7, an aluminum oxide film 6 is formed on the hafnium aluminate film 5 by using, for example, an ALD method. Specifically, trimethylaluminum is introduced onto the semiconductor substrate 1 heated to about 300 ° C. Then, after exhausting trimethylaluminum, water vapor is introduced onto the semiconductor substrate 1 and exhausted. In this way, an aluminum oxide film 6 having a thickness of about 0.3 nm to about 2.0 nm is formed. The aluminum oxide film 6 may be formed using a CVD method or the like.

  Subsequently, the aluminum oxide film 6 is etched using a photolithography technique and an etching technique to form a threshold adjustment film 7 shown in FIG. Then, as shown in FIG. 9, a tantalum silicate nitride film 8 is formed on the semiconductor substrate 1 using a CVD method or the like. After that, as shown in FIG. 10, the tantalum siliconitride film 8 is patterned using a photolithography technique and an etching technique, and a gate insulating film 9 made of a hafnium aluminate film 5 in the n-type MIS element formation region and the gate insulating film A gate electrode 10 made of a tantalum siliconitride film 8 is formed on the substrate 9. Further, a gate insulating film 9 made of a hafnium aluminate film 5 is formed in the p-type MIS element forming region, a threshold adjustment film 7 made of an aluminum oxide film 6 is formed on the gate insulating film 9, and on the threshold adjustment film 7. A gate electrode 11 made of the tantalum siliconitride film 8 is formed.

  Next, by introducing an n-type impurity such as phosphorus into the region in the semiconductor substrate 1 on both sides of the formed gate electrode 10 using an ion implantation method, a low concentration as shown in FIG. N-type impurity diffusion layers 12 and 13 are formed. Similarly, low-concentration p-type impurity diffusion layers 14 and 15 are formed on both sides of the gate electrode 11. Thereafter, an annealing process is performed to activate ions.

  Subsequently, after forming a silicon oxide film on the semiconductor substrate 1 using a CVD method or the like, anisotropic etching is performed to form the sidewalls 16 as shown in FIG. Then, the high concentration n-type impurity diffusion layers 17 and 18 are formed by using the ion implantation method, and then the high concentration p-type impurity diffusion layers 19 and 20 are formed again by using the ion implantation method. Thereafter, an annealing process is performed to activate ions. In this way, LDD (Lightly Doped Drain) type source and drain regions can be formed in the n-type MIS element and the p-type MIS element, respectively.

  Next, as shown in FIG. 13, an interlayer insulating film 21 made of a silicon oxide film is formed on the semiconductor substrate 1 using a CVD method, and then a chemical mechanical polishing (CMP) method is used. To flatten the surface. Thereafter, through holes 22 penetrating into the source region and the drain region are formed in the interlayer insulating film 21 by using a photolithography technique and an etching technique. Subsequently, after forming a titanium / titanium nitride film 23 on the semiconductor substrate 1 using a sputtering method, a tungsten film 24 is formed using a CVD method. At this time, a titanium / titanium nitride film 23 is formed on the bottom and inner wall of the through hole 22, and a tungsten film 24 is embedded in the through hole 22 through the titanium / titanium nitride film 23. Subsequently, the semiconductor substrate 1 is polished using a CMP method so that the titanium / titanium nitride film 23 and the tungsten film 24 remain only in the through holes 22.

  Next, a titanium / titanium nitride film 25, an aluminum film 26, and a titanium / titanium nitride film 27 are sequentially formed by sputtering. Then, by using a photolithography technique and an etching technique, the above-described film is patterned to form a wiring 28 as shown in FIG. In this way, the CMIS element shown in FIG. 1 can be formed.

  In the first embodiment, the gate electrode 10 of the n-type MIS element and the gate electrode 11 of the p-type MIS element are formed of tantalum siliconitride, which is the same material, but other materials may be used.

  Further, the gate electrode 10 of the n-type MIS element and the gate electrode 11 of the p-type MIS element may be formed of different materials. For example, the material used for the gate electrode 10 is formed from one that lowers the threshold voltage of the n-type MIS element, while the material used for the gate electrode 11 is formed from one that lowers the threshold voltage of the p-type MIS element. be able to. For example, the gate electrode 10 of the n-type MIS element can be formed from tantalum nitride, hafnium nitride, zirconium nitride, tantalum silicide, hafnium silicide, zirconium silicide, or a mixture thereof. The gate electrode 11 of the p-type MIS element can be formed from tungsten, tungsten nitride, molybdenum, molybdenum nitride, iridium oxide, tungsten silicide, or a mixture thereof. The films made of these materials described above have thermal stability and good film adhesion.

  In the first embodiment, the threshold adjustment film 7 is formed only on the p-type MIS element. However, the present invention is not limited to this, and the threshold adjustment film 30 is also provided on the n-type MIS element as shown in FIG. May be formed. The threshold adjustment film 30 is made of a material whose flat band voltage shifts in the negative direction. Specifically, the threshold adjustment film 30 is formed of a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, a hafnium oxynitride film, a zirconium oxide film, a zirconium oxynitride film, or the like. These films are presumed to be films having a relatively large amount of positive fixed charges. However, the fixed charge amount in these films may vary depending on the film formation conditions. The film thickness of the threshold adjustment film 30 is desirably about 0.3 nm to about 2.0 nm from the viewpoint of miniaturizing the element.

  In summary, the modification of the first embodiment includes (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, and (c) formed on the gate insulating film. A MIS device comprising: a threshold adjustment film for adjusting a threshold voltage; and (d) a gate electrode made of a material containing a metal and formed on the threshold adjustment film. And the threshold adjustment film is a film having a relatively large amount of positive fixed charges.

  More specifically, the modification of the first embodiment includes (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, and (c) on the gate insulating film. A MIS element comprising: a threshold adjustment film for adjusting a threshold voltage; and (c) a gate electrode formed on the threshold adjustment film and made of a material containing a metal. The threshold adjustment film is formed of any one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, and zirconium oxynitride.

  Further, depending on the selection of the gate electrodes 10 and 11, the threshold adjustment film 30 may be formed in the n-type MIS element while the threshold adjustment film 7 is not formed in the p-type MIS element.

  Further, as shown in FIG. 15, for example, a threshold adjustment film 33 may be formed between the gate insulating film 31 and the gate insulating film 32 of the n-type MIS element. That is, when the gate insulating film is formed of a plurality of films, the threshold adjustment film 33 may be formed between any of them. Similarly, a threshold adjustment film 36 may be formed between the gate insulating film 34 and the gate insulating film 35 of the p-type MIS element.

  FIG. 15 shows an example in which the threshold adjustment film is formed between the gate insulating films in both the n-type MIS element and the p-type MIS element, but the threshold adjustment film is formed only on one side. Alternatively, the threshold adjustment film formed on one side may be formed between the gate insulating film and the gate electrode.

  Note that the threshold adjustment film may be formed not between the gate insulating film and the gate electrode but between the semiconductor substrate and the gate insulating film. However, since the threshold adjustment film is presumed to be a film having a relatively large amount of positive fixed charges or negative fixed charges, the threshold adjustment film is too close to the channel through which electrons pass. There is a risk of scattering electrons passing through the channel. Therefore, from the viewpoint of preventing electrons from being scattered, it is desirable to separate the threshold adjustment film from the channel formation region as much as possible. That is, from the above viewpoint, it is desirable to form a threshold adjustment film between the gate insulating film and the gate electrode.

(Embodiment 2)
In the second embodiment, the present invention is applied to a method of manufacturing a p-type MISFET element that can suppress the threshold voltage to a low level.

  In the second embodiment, an example of a method of manufacturing a p-type MIS element that can suppress the threshold voltage to be low will be described with reference to the drawings. First, as shown in FIG. 16, a semiconductor substrate 40 made of single crystal silicon is prepared. Next, after the semiconductor substrate 40 is cleaned, an element isolation region 41 made of a silicon oxide film is formed using a selective oxidation method as described in the first embodiment (FIG. 17). The width of the element isolation region 41 is about 500 nm.

  Subsequently, a photosensitive resist film is applied on the semiconductor substrate 40, and then patterned by exposure and development. The patterning is performed so as to selectively open the p-type MIS element formation region. Then, as shown in FIG. 18, an n-type well 42 is formed by introducing an n-type impurity such as phosphorus or arsenic using an ion implantation method. Then, the patterned resist film is removed.

  Next, a photosensitive resist film is applied again on the semiconductor substrate 40. Then, the resist film is patterned by exposure and development, and a dummy gate electrode 43 is formed on the semiconductor substrate 40 as shown in FIG. Although the dummy gate electrode 43 is formed from a resist film, the present invention is not limited to this and may be formed from an insulating film.

  Subsequently, by introducing a p-type impurity such as boron into the semiconductor substrate 40 on both sides of the dummy gate electrode 43 using an ion implantation method, the source region 44 and the drain as shown in FIG. Region 45 is formed. Next, as shown in FIG. 20, after the dummy gate electrode 43 is removed and cleaning is performed, annealing for activating ions introduced into the source region 44 and the drain region 45 is performed at about 600 ° C. to about 1100 ° C. To do.

  Next, as shown in FIG. 21, a silicon oxide film 46 is formed on the semiconductor substrate 40 using a thermal oxidation method. Then, a tantalum nitride film 47 is formed on the silicon oxide film 46 by using a CVD method or the like.

  Subsequently, the silicon oxide film 46 and the tantalum nitride film 47 are processed by using a photolithography technique and a reactive ion etching (RIE) technique, and a gate insulating film 48 and a gate electrode 49 as shown in FIG. Form.

  Next, heat treatment is performed on the formed gate insulating film 48 and the gate electrode 49. As a method of performing the heat treatment, for example, a laser annealing method that can be locally heated can be used. The heat treatment can also be performed by a lamp heating method. As described above, the present inventor has found that the threshold voltage of the MIS element to be formed can be changed by performing the heat treatment on the gate insulating film 48 and the gate electrode 49.

  FIG. 23 shows the relationship between the heat treatment temperature and the flat band voltage. In FIG. 23, the horizontal axis indicates the heat treatment temperature (° C.), and the vertical axis indicates the flat band voltage (V). When the heat treatment temperature is about 400 ° C., the flat band voltage is about −0.65V. As described in the first embodiment, in the case of the p-type MIS element, the threshold voltage is about 0 V when the flat band voltage is about 0.1 V. Therefore, when the flat band voltage is about −0.65V, the threshold voltage is about 0.75V.

  However, it can be seen that the flat band voltage increases as the temperature of the heat treatment increases. An increase in the flat band voltage means that the threshold voltage is lowered when viewed from the p-type MIS element. Therefore, the threshold voltage can be lowered by performing heat treatment at an elevated temperature.

  Specifically, when the heat treatment temperature is about 600 ° C., the flat band voltage is about 0.6 V and the threshold voltage is about 0.7 V. Then, when the temperature of the heat treatment reaches about 800 ° C., the flat band voltage rapidly increases to about −0.35V. For this reason, the threshold voltage rapidly decreases to about 0.45V. Thereafter, when the temperature of the heat treatment is raised to about 1000 ° C., the flat band voltage becomes about −0.33 V, so that the threshold voltage becomes about 0.43 V. Therefore, it can be seen that the temperature of the heat treatment is desirably about 800 ° C. to about 1000 ° C. from the viewpoint of lowering the threshold voltage of the p-type MIS element.

  As described above, according to the method of manufacturing a semiconductor device in the second embodiment, the threshold voltage of the p-type MIS element can be lowered simply by performing heat treatment. Therefore, since the threshold voltage of the p-type MIS element can be lowered without adding a manufacturing process accompanied by an increase in masks or a complicated manufacturing process, the yield of products can be improved.

  After the heat treatment described above is applied to the gate insulating film 48 and the gate electrode 49, an interlayer insulating film 50 made of silicon oxide is formed on the semiconductor substrate 40 using a CVD method or the like as shown in FIG. Then, the surface is polished by a CMP method.

  Subsequently, as shown in FIG. 25, a through-hole 51 that penetrates to the source region 44 and the drain region 45 is formed in the interlayer insulating film 50. Then, after forming a titanium / titanium nitride film 52 on the semiconductor substrate 40 using a sputtering method, a tungsten film 53 is formed using a CVD method. At this time, a titanium / titanium nitride film 52 is formed on the bottom and inner wall of the through hole 51, and a tungsten film 53 is embedded in the through hole 51 through the titanium / titanium nitride film 52. Subsequently, the semiconductor substrate 40 is polished by using the CMP method so that the titanium / titanium nitride film 52 and the tungsten film 53 remain only in the through hole 51.

  Next, a titanium / titanium nitride film 54, an aluminum film 55, and a titanium / titanium nitride film 56 are sequentially formed by sputtering. Then, using the photolithography technique and the etching technique, the above-described film is patterned to form the wiring 57 as shown in FIG. In this manner, a p-type MIS element using the method for manufacturing a semiconductor device in the second embodiment can be formed.

  Although the silicon oxide film is used as the gate insulating film of the p-type MIS element formed in the second embodiment, the present invention is not limited to this, and may be a so-called High-k film such as a hafnium aluminate film.

  In the method for manufacturing a semiconductor device according to the second embodiment, the heat treatment is performed immediately after the gate insulating film 48 and the gate electrode 49 are formed. However, after the interlayer insulating film 50 is formed, the heat treatment in the present invention is performed. Also good.

  Further, the heat treatment in the present invention may be performed before the gate insulating film 48 and the gate electrode 49 are formed. That is, the heat treatment in the present invention may be performed at the stage where the silicon oxide film (insulating film) 46 and the tantalum nitride film (conductor film) 47 are formed on the semiconductor substrate 40. In this case, the manufacturing method of the semiconductor device according to the second embodiment includes (a) a step of preparing a semiconductor substrate, (b) a step of forming a dummy gate electrode on a predetermined region of the semiconductor substrate, and (c). Forming a source region and a drain region by ion implantation using the dummy gate electrode as a mask; (d) removing the dummy gate electrode; and (e) forming an insulating film on the semiconductor substrate. (F) forming a conductor film on the insulating film; (g) adjusting the threshold voltage by applying a heat treatment to the insulating film and the conductor film; ) Processing the insulating film and the conductive film to form a gate insulating film on a region between the source region and the drain region, and forming a gate electrode made of a material containing a metal on the gate insulating film. It is characterized in that to form the MIS device and a process.

  The invention made by the present inventor has been specifically described based on the above embodiment, but the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 P-type well 4 N-type well 5 Hafnium aluminate film 6 Aluminum oxide film 7 Threshold adjustment film 8 Tantalum silicon nitride film 9 Gate insulating film 10 Gate electrode 11 Gate electrode 12 Low concentration n-type Impurity diffusion layer 13 Low-concentration n-type impurity diffusion layer 14 Low-concentration p-type impurity diffusion layer 15 Low-concentration p-type impurity diffusion layer 16 Side wall 17 High-concentration n-type impurity diffusion layer 18 High-concentration n-type impurity diffusion layer 19 High-concentration p Type impurity diffusion layer 20 High-concentration p-type impurity diffusion layer 21 Interlayer insulating film 22 Through hole 23 Titanium / titanium nitride film 24 Tungsten film 25 Titanium / titanium nitride film 26 Aluminum film 27 Titanium / titanium nitride film 28 Wiring 30 Threshold adjustment Film 31 Gate insulation film 32 Gate insulation film 33 Threshold adjustment film 34 Gate insulation 35 Gate insulating film 36 Threshold adjustment film 40 Semiconductor substrate 41 Element isolation region 42 N-type well 43 Dummy gate electrode 44 Source region 45 Drain region 46 Silicon oxide film 47 Tantalum nitride film 48 Gate insulating film 49 Gate electrode 50 Interlayer insulating film 51 Through-hole 52 Titanium / titanium nitride film 53 Tungsten film 54 Titanium / titanium nitride film 55 Aluminum film 56 Titanium / titanium nitride film 57 Wiring

Claims (6)

In a semiconductor device having a p-type MIS element on a semiconductor substrate,
The p-type MIS element is
A silicon insulating film provided on the semiconductor substrate;
An aluminum insulating film provided on the silicon insulating film;
An electrode provided on the aluminum insulating film;
A semiconductor device including:   The semiconductor device according to claim 1, wherein the silicon insulating film is a silicon oxide film.   The semiconductor device according to claim 1, wherein the silicon insulating film is a silicon nitride film.   The semiconductor device according to claim 1, wherein the aluminum insulating film is an aluminum oxide film.   The semiconductor device according to claim 1, wherein the aluminum insulating film is an aluminum oxynitride film. In a semiconductor device having an n-type MIS element and a p-type MIS element on a semiconductor substrate,
The n-type MIS element is
A first insulating film provided on the semiconductor substrate;
A first threshold adjustment film provided on the first insulating film and lowering a threshold of the n-type MIS element;
A first gate electrode provided on the first threshold adjustment film;
Including
The p-type MIS element is
A second insulating film provided on the semiconductor substrate and provided in a region different from a region in which the first insulating film, the first threshold adjustment film, and the first gate electrode are provided;
Provided on the second insulating film, provided in a region different from a region in which the first insulating film, the threshold adjustment film, and the first gate electrode are provided; and Have different components, and a second threshold adjustment film that lowers the threshold of the p-type MIS element;
A second gate electrode provided on the second threshold adjustment film and provided in a region different from a region in which the first insulating film, the first threshold adjustment film, and the first gate electrode are provided. When,
A semiconductor device including:

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