JP2004006679A - Semiconductor element and semiconductor device using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element capable of high speed operation and exhibiting large current driving power while suppressing variations between the elements. <P>SOLUTION: The semiconductor element having a first crystallinity semiconductor region including a plurality of crystal orientations substantially having no crystal grain boundary is formed on an insulating surface wherein the first crystallinity semiconductor region is provided contiguously to a conductive second crystallinity semiconductor region. The first crystallinity semiconductor region extends in a direction parallel with an insulation film provided in linear stripe pattern on the insulating surface. The second crystallinity semiconductor region is provided across the insulation film extending in linear stripe pattern. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element formed using a semiconductor film having a crystal structure, a manufacturing method thereof, a semiconductor device including a circuit in which the semiconductor element is integrated, and a manufacturing method thereof. In particular, the present invention relates to a field effect transistor (typically, a thin film transistor) in which a channel formation region is formed using a crystalline semiconductor film formed over an insulating surface, a thin film diode using the crystalline semiconductor film, and the like as a semiconductor element.
[0002]
[Prior art]
A technique has been developed in which an amorphous silicon film is formed on an insulating substrate made of glass or the like, and the amorphous silicon film is crystallized to form a semiconductor element such as a transistor. In particular, a technique of irradiating a laser beam to crystallize an amorphous silicon film is applied to a manufacturing technique of a thin film transistor (TFT). A transistor manufactured using a semiconductor film having a crystal structure (crystalline semiconductor film) is applied to a flat display device (flat panel display) represented by a liquid crystal display device.
[0003]
The application of laser light in the semiconductor manufacturing process is a technique for recrystallizing a damaged layer or an amorphous layer formed on a semiconductor substrate or a semiconductor film, and a technique for crystallizing an amorphous semiconductor film formed on an insulating surface. Has been expanded to. As a laser oscillation device to be applied, a gas laser typified by an excimer laser or a solid laser typified by a YAG laser is usually used.
[0004]
One example of crystallization of an amorphous semiconductor film by irradiation with laser light is to set the scanning speed of laser light to a beam spot diameter × 5000 / sec or more without bringing the amorphous semiconductor film into a completely molten state by high-speed scanning. Some are polycrystalline (for example, see Patent Document 1). Further, there is a technique in which a semiconductor film formed in an island shape is irradiated with an elongated laser beam to substantially form a single crystal region (for example, see Patent Document 2). Alternatively, there is known a method of processing and irradiating a linear beam with an optical system like a laser processing apparatus (for example, see Patent Document 3).
[0005]
[Patent Document 1]
JP-A-62-104117
[Patent Document 2]
U.S. Pat. No. 4,330,363
[Patent Document 3]
JP-A-8-195357
[0006]
Further, Nd: YVO ₄ A solid-state laser oscillation device such as a laser is used to irradiate the amorphous semiconductor film with laser light, which is the second harmonic, to form a crystalline semiconductor film having a larger crystal grain size than in the past, and to manufacture a transistor. There is a technology (for example, see Patent Document 4).
[0007]
[Patent Document 4]
JP 2001-144027 A
[0008]
[Problems to be solved by the invention]
However, when an amorphous semiconductor film formed on a flat surface is crystallized by irradiating a laser beam with a laser beam, the crystal becomes polycrystalline, and defects such as crystal grain boundaries are formed arbitrarily and a crystal having a uniform orientation is obtained. I couldn't get it.
[0009]
The crystal grain boundary contains crystal defects, which serve as carrier traps and cause a reduction in electron or hole mobility. In addition, due to volume shrinkage of the semiconductor film caused by crystallization, thermal stress with the base, lattice mismatch, and the like, a semiconductor film free from distortion and crystal defects cannot be formed. Therefore, when a special method such as a bonded SOI (Silicon on Insulator) is omitted, a crystalline semiconductor film formed on an insulating surface and crystallized or recrystallized is equivalent to a MOS transistor formed on a single crystal substrate. The quality could not be obtained.
[0010]
In the above-described flat display device and the like, a transistor is formed by forming a semiconductor film on a glass substrate. However, it is almost impossible to arrange the transistor so as to avoid arbitrarily formed crystal grain boundaries. . That is, it has not been possible to strictly control the crystallinity of a channel formation region of a transistor and eliminate crystal grain boundaries and crystal defects that are unintentionally included. As a result, not only are the electrical characteristics of the transistors inferior, but also the characteristics of the individual elements vary.
[0011]
In particular, when a crystalline semiconductor film is formed using laser light on an alkali-free glass substrate that is widely used in industry, the focal point of the laser light varies due to the influence of the undulation of the alkali-free glass substrate itself. There is a problem that crystallinity variation is caused. Further, a non-alkali glass substrate needs to be provided with a protective film such as an insulating film as a base film in order to avoid contamination by an alkali metal, on which a crystalline semiconductor film from which crystal grain boundaries and crystal defects are eliminated is largely formed. It was almost impossible to form with a particle size.
[0012]
The present invention has been made in view of the above-described problems, and forms a crystalline semiconductor film having no crystal grain boundary in at least a channel formation region on an insulating surface, particularly, on an insulating surface having a glass substrate as a supporting base, It is an object of the present invention to provide a semiconductor device including a semiconductor element or a semiconductor element group which can operate at high speed, has high current driving capability, and has small variations among a plurality of elements.
[0013]
[Means for Solving the Problems]
In order to solve the above problem, the present invention forms an insulating film provided with a concave portion and a convex portion extending in a linear stripe pattern on a substrate having an insulating surface, and forms an amorphous film on the insulating film. A semiconductor film is formed, a crystalline semiconductor film is formed by melting and pouring the semiconductor film into a portion corresponding to a concave portion of the insulating film (hereinafter, simply referred to as a concave portion), and an unnecessary region is removed by etching. A crystalline semiconductor film in which a crystalline semiconductor film divided into an island shape from a crystalline semiconductor film (to be a part of a semiconductor element later) is formed, and at least a portion for forming a channel formation region is formed in the above-described concave portion. And a gate insulating film and a gate electrode are provided on the crystalline semiconductor film.
[0014]
Note that, of the insulating film provided with a portion corresponding to the concave portion or the convex portion (hereinafter, simply referred to as a convex portion), the crystallinity of the crystalline semiconductor film formed over the convex portion is determined by the crystallinity formed in the concave portion. Although inferior to a semiconductor film, in the present invention, a crystalline semiconductor film formed over the projection is used as an electrode (corresponding to a source region or a drain region in the case of a thin film transistor) or a wiring. It is characterized by the following. When used as a wiring, the degree of freedom in designing the occupied area is high. Therefore, the wiring length can be adjusted to be used as a resistor, or the bent shape can have a function as a protection circuit.
[0015]
The above-described concave portion may be formed by directly etching the surface of the insulating substrate, or may be formed by using a silicon oxide, silicon nitride, silicon oxynitride film, or the like and performing an etching process on the film. The recess is preferably formed in accordance with the arrangement of the island-shaped semiconductor film including the channel formation region of the semiconductor element, particularly the transistor, and is desirably formed so as to match at least the channel formation region. Further, the recess is provided to extend in the channel length direction. The recess has a width of 0.01 μm or more and 2 μm or less, preferably 0.1-1 μm, and a depth of 0.01 μm or more and 3 μm or less, preferably 0.1 μm or less. It is formed with a thickness of 1 μm or more and 2 μm or less.
[0016]
Of course, it is also possible to form an island-shaped insulating film on the insulating surface and positively form the convex portion. In this case, the convex portions extending in a plurality of linear stripe patterns form portions relatively corresponding to concave portions between adjacent portions, so that the concave portions are formed as island-shaped semiconductors including the channel formation region of the semiconductor element. What is necessary is just to form according to the arrangement | positioning of a film | membrane, and just to set width as mentioned above.
[0017]
In the first stage, a semiconductor film formed over the insulating film and over the concave portion is an amorphous semiconductor film or a polycrystalline semiconductor film formed by a plasma CVD method, a sputtering method, a low-pressure CVD method, or a polycrystalline semiconductor film formed by solid phase growth. A crystalline semiconductor film or the like is applied. Note that the term “amorphous semiconductor film” in the present invention means not only a film having a completely amorphous structure in a narrow sense, but also a state containing fine crystal grains, or a so-called microcrystalline semiconductor film, Includes a semiconductor film having a crystal structure. Typically, an amorphous silicon film is applied. In addition, an amorphous silicon germanium film, an amorphous silicon carbide film, or the like can be used. The polycrystalline semiconductor film is obtained by crystallizing these amorphous semiconductor films by a known method.
[0018]
As a means for melting and crystallizing the crystalline semiconductor film, a pulsed or continuous wave laser beam using a gas laser oscillator or a solid laser oscillator as a light source is used. The laser light to be irradiated is linearly condensed by an optical system, and its intensity distribution has a uniform region in the longitudinal direction and may have a distribution in the lateral direction. As the oscillation device, a rectangular beam solid laser oscillation device is applied, and particularly preferably, a slab laser oscillation device is applied. Alternatively, it is a solid-state laser oscillation device using a rod doped with Nd, Tm, and Ho, and in particular, YAG, YVO ₄ , YLF, YAlO ₃ A solid-state laser oscillation device using a crystal in which Nd, Tm, and Ho are doped into a crystal such as the above may be combined with a slab structure amplifier. Crystals such as Nd: YAG, Nd: GGG (gadolinium gallium garnet), and Nd: GSGG (gadolinium scandium gallium garnet) are used as the slab material. In the slab laser, the laser beam travels in a zigzag optical path in this plate-shaped laser medium while repeating total reflection.
[0019]
Further, strong light corresponding thereto may be applied. For example, the light emitted from a halogen lamp, a xenon lamp, a high-pressure mercury lamp, a metal halide lamp, or an excimer lamp may be a light having a high energy density collected by a reflecting mirror or a lens.
[0020]
The laser light or intense light that is condensed linearly and extended in the longitudinal direction irradiates the crystalline semiconductor film, and relatively moves the irradiation position of the laser light and the substrate on which the crystalline semiconductor film is formed, The crystalline semiconductor film is melted by scanning a part or the entire surface of the crystalline semiconductor film with the laser light, and crystallization or recrystallization is performed through the state. The scanning direction of the laser light is along the longitudinal direction of the concave portion formed in the insulating film and extending in a linear stripe pattern or along the channel length direction of the transistor. Thereby, the crystal grows along the scanning direction of the laser beam, and it is possible to prevent the crystal grain boundary from intersecting with the channel length direction.
[0021]
The laser light irradiation is typically performed from the upper surface side of the semiconductor film. However, irradiation from the lower surface side (substrate side), irradiation from the upper surface side diagonal direction or from the lower surface side diagonal direction, or upper surface side and lower surface side is performed. Irradiation from both sides (including irradiation from an oblique direction) may be performed.
[0022]
As another structure, the crystalline semiconductor film is provided over a metal layer containing one or more kinds selected from W, Mo, Ti, Ta, and Cr on a glass or quartz substrate. An insulating layer may be provided between the semiconductor film and the semiconductor film. Alternatively, a metal layer containing one or more kinds selected from W, Mo, Ti, Ta, and Cr on a glass or quartz substrate and an insulating layer made of aluminum nitride or aluminum oxynitride are provided over the metal layer. Alternatively, a structure in which a crystalline semiconductor film is provided thereon may be adopted. The metal layer formed here can function as a light-blocking film that blocks light incident on the channel formation region, or can apply a specific potential to control the spread of fixed charges or a depletion layer. Further, a function as a heat radiating plate for dissipating Joule heat can be provided.
[0023]
When the depth of the concave portion is approximately equal to or greater than the thickness of the semiconductor film, the semiconductor film melted by irradiation with laser light or strong light is aggregated and solidified in the concave portion by surface tension. As a result, the thickness of the semiconductor film on the convex portion of the insulating film becomes thin, and stress strain can be concentrated there. Further, the side surface of the concave portion has an effect of defining the crystal orientation to some extent.
[0024]
In a molten state, the semiconductor film is aggregated in the recess formed on the insulating surface by surface tension, and the crystal is grown from the approximate intersection of the bottom and the side of the recess, so that the strain caused by crystallization is concentrated in the area other than the recess. Can be done. That is, the crystalline semiconductor region (first crystalline semiconductor region) formed so as to fill the concave portion can be released from distortion. The crystalline semiconductor region (second crystalline semiconductor region) remaining on the insulating film and including a crystal grain boundary and a crystal defect is a portion other than a channel formation region of a semiconductor element, typically, a source region or a drain region. Used as an area.
[0025]
Then, after forming a crystalline semiconductor film having no crystal grain boundary in the concave portion, an active layer (a semiconductor layer functioning as a carrier moving path) of the semiconductor element is formed by patterning, and a gate insulating film in contact with the active layer is formed. Then, a gate electrode is formed. Thereafter, a field-effect transistor can be formed by a known method.
[0026]
According to the present invention, it is possible to specify a semiconductor element such as a transistor, in particular, a region where a channel formation region is formed, and to form a crystalline semiconductor region having no crystal grain boundary in the region. As a result, it is possible to eliminate a factor in which the characteristics vary due to carelessly interposed crystal grain boundaries and crystal defects. That is, it is possible to form a semiconductor element or a semiconductor device including a semiconductor element group which can operate at high speed, has high current driving capability, and has small variation among a plurality of elements.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
Hereinafter, an embodiment of manufacturing a thin film transistor using the present invention will be described with reference to the drawings. The perspective view shown in FIG. 1 shows a mode in which a first insulating film 102 and second insulating films 103 to 105 formed in a linear stripe pattern are formed on a substrate 101. FIG. 1 shows three linear stripe patterns formed by the second insulating film, but the number is not limited to the number.
[0028]
As the substrate, a commercially available alkali-free glass substrate, a quartz substrate, a sapphire substrate, a substrate in which the surface of a single crystal or polycrystalline semiconductor substrate is covered with an insulating film, and a substrate in which the surface of a metal substrate is covered with an insulating film can be used. In order to form a linear stripe pattern according to a submicron design rule, it is desirable that unevenness of the substrate surface, undulation or twist of the substrate be less than the depth of focus of an exposure apparatus (particularly a stepper). Specifically, it is desirable that the undulation or torsion of the substrate be 1 μm or less, preferably 0.5 μm or less in a single exposure light irradiation area. Attention should be paid to this point, especially when non-alkali glass is used as the supporting substrate.
[0029]
The width W1 of the second insulating film formed in the linear stripe pattern is 0.1 to 10 μm (preferably 0.5 to 1 μm), and the distance W2 between adjacent second insulating films is 0.01 to 2 μm ( Preferably, the thickness is 0.1 to 1 μm), and the thickness d of the second insulating film is 0.01 to 3 μm (preferably 0.1 to 2 μm). Furthermore, the relationship between the thickness of the amorphous semiconductor film provided to cover the second insulating film and the film thickness t02 may be d ≧ t02. Care must be taken since the crystalline semiconductor film does not remain.
[0030]
Further, the step shape does not need to be a regular periodic pattern, and may be arranged at different intervals according to the width of the island-shaped semiconductor film. The length L is not particularly limited in numerical value, and can be formed to be long from one end to the other end of the substrate. For example, the length L is set to such a length that a channel formation region of a transistor can be formed. It is also possible.
[0031]
The first insulating film 102 may be made of any material that can secure a selectivity with respect to a second insulating film to be formed later; typically, silicon nitride, silicon oxide, or an acid whose oxygen content is larger than the nitrogen content is used. Silicon nitride (shown as SiOxNy), silicon oxynitride (shown as SiNxOy), whose nitrogen content is larger than oxygen content, aluminum nitride (shown as AlxNy), oxynitridation whose oxygen content is larger than the nitrogen content It is formed of a material selected from aluminum (shown as AlOxNy), aluminum oxynitride (shown as AlNxOy) or aluminum oxide having a nitrogen content larger than the oxygen content, and is formed with a thickness of 30 to 300 nm. In particular, since an aluminum oxide film can be expected to have a blocking effect on sodium (Na), it is effective as a countermeasure against contamination from a glass substrate.
[0032]
In addition, as a silicon oxynitride (SiOxNy) film, a film containing 25 to 35 atomic% of Si, 55 to 65 atomic% of oxygen, 1 to 20 atomic% of nitrogen, and 0.1 to 10 atomic% of hydrogen is used. You can use it. As the silicon oxynitride (SiNxOy) film, a film containing 25 to 35 atomic% of Si, 15 to 30 atomic% of oxygen, 20 to 35 atomic% of nitrogen, and 15 to 25 atomic% of hydrogen is used. good. As the aluminum oxynitride (AlOxNy) film, a film containing 30 to 40 atomic% of Al, 50 to 70 atomic% of oxygen, and 1 to 20 atomic% of nitrogen may be used. Further, as the aluminum oxynitride (AlNxOy) film, a film containing 30 to 50 atomic% of Al, 30 to 40 atomic% of oxygen, and 10 to 30 atomic% of nitrogen may be used.
[0033]
The second insulating films 103 to 105 may be formed using silicon oxide or silicon oxynitride with a thickness of 10 to 3000 nm, preferably 100 to 2000 nm. Silicon oxide is composed of tetraethyl orthosilicate (TEOS) and O ₂ Can be mixed and formed by a plasma CVD method. Silicon oxynitride film is SiH ₄ , NH ₃ , N ₂ O or SiH ₄ , N ₂ It can be formed by a plasma CVD method using O as a raw material.
[0034]
As shown in FIG. 1, when a linear stripe pattern is formed with two layers of insulating films, it is necessary to provide a selectivity between the first insulating film 102 and the second insulating films 103 to 105 in the etching process. There is. Actually, it is desirable to appropriately adjust the material and the film forming conditions so that the etching rate of the second insulating films 103 to 105 is relatively higher than that of the first insulating film 102. As an etching method, etching using buffered hydrofluoric acid or CHF ₃ This is performed by dry etching using. The angle of the side surface of the concave portion formed by the second insulating films 103 to 105 may be appropriately set in the range of 5 to 120 degrees, preferably 80 to 100 degrees.
[0035]
Note that as the second insulating films 103 to 105, an insulating film formed by a CVD method (typically, a plasma CVD method or a thermal CVD method) or a PVD method (typically, a sputtering method or a vapor deposition method) is used. Preferably, it is used. This is because, when crystallizing an amorphous semiconductor film, it is considered that the softness enough to relieve the stress accompanying crystallization plays an important role in obtaining good crystallinity. is there. The reason will be described later.
[0036]
Next, as shown in FIG. 2, the amorphous semiconductor film 106 covering the surface of the first insulating film 102 and the second insulating films 103 to 105 and covering the recesses is formed to have a thickness of 0.01 to 3 μm (preferably 0.1 to 0.1 μm). １1 μm). At this time, the thickness of the amorphous semiconductor film 106 is desirably equal to or greater than the depth of the concave portion formed by the second insulating films 103 to 105. For the amorphous semiconductor film, silicon, a compound or alloy of silicon and germanium, or a compound or alloy of silicon and carbon can be used.
[0037]
As shown, the amorphous semiconductor film 106 is formed so as to cover the uneven structure formed by the underlying first insulating film 102 and second insulating films 103 to 105. In addition, the influence of chemical contamination, such as boron, attached to the surfaces of the first insulating film 102 and the second insulating films 103 to 105 is eliminated, and the insulating surface is not directly contacted with the amorphous semiconductor film. Immediately before the formation of the crystalline semiconductor film 106, a silicon oxynitride film may be formed continuously as a third insulating film (not shown) without being exposed to the air in the same film forming apparatus. The thickness of the third insulating film is intended to eliminate the influence of the above-mentioned chemical contamination and to improve the adhesion, and even if it is thin, it is sufficiently effective. Typically, the thickness may be 5 to 50 nm (preferably 20 nm or more to enhance the blocking effect of chemical contamination).
[0038]
Then, the amorphous semiconductor film 106 is instantaneously melted and crystallized. In this crystallization, laser light or radiation light from a lamp light source is condensed by an optical system to an energy density at which the semiconductor film is melted and irradiated. In this step, it is particularly preferable to apply laser light using a continuous wave laser oscillation device as a light source. The applied laser light is linearly condensed by the optical system and expanded in the longer direction, and its intensity distribution has a uniform region in the longer direction, It is desirable to have some distribution in the short direction.
[0039]
In the crystallization, it is preferable that a position where a marker to be used for patterning mask alignment after the end of the substrate is formed is not crystallized. This is because, when a crystalline semiconductor film (especially a crystalline silicon film) is crystallized, the transmittance of visible light increases, and it becomes difficult to identify the crystalline semiconductor film as a marker. However, there is no problem when performing a type of alignment control that optically identifies a difference in contrast or the like due to a step of the marker.
[0040]
As the laser oscillation device, a rectangular beam solid laser oscillation device is applied, and particularly preferably, a slab laser oscillation device is applied. Crystals such as Nd: YAG, Nd: GGG (gadolinium gallium garnet), and Nd: GSGG (gadolinium scandium gallium garnet) are used as the slab material. In the slab laser, the laser beam travels in a zigzag optical path in this plate-shaped laser medium while repeating total reflection. Alternatively, it is a solid-state laser oscillation device using a rod doped with Nd, Tm, and Ho, and in particular, YAG, YVO ₄ , YLF, YAlO ₃ A solid-state laser oscillation device using a crystal in which Nd, Tm, and Ho are doped into a crystal such as the above may be combined with a slab structure amplifier.
[0041]
Then, as shown by arrows in FIG. 3, the second insulating films 103 to 105 in which the length direction of the irradiation region 100 of the linear laser light (the X-axis direction in the drawing) is a linear stripe pattern are formed. A linear laser beam or intense light is scanned so as to intersect each other. Here, the term “linear” means that the ratio of the length in the longer direction (X-axis direction) to the length in the shorter direction (Y-axis direction in the drawing) is 1:10 or more. Say something. Although only a part is shown in FIG. 3, the end of the irradiation area 100 of the linear laser light may be rectangular or may have a curvature.
[0042]
The wavelength of the continuous wave laser light is preferably 400 to 700 nm in consideration of the light absorption coefficient of the amorphous semiconductor film. Light in such a wavelength band is obtained by extracting the second harmonic and the third harmonic of the fundamental wave using a wavelength conversion element. ADP (ammonium dihydrogen phosphate), Ba ₂ NaNb ₅ O _Fifteen (Sodium barium niobate), CdSe (selenium cadmium), KDP (potassium dihydrogen phosphate), LiNbO ₃ (Lithium niobate), Se, Te, LBO, BBO, KB5 and the like are applied. It is particularly desirable to use LBO. A typical example is Nd: YVO ₄ A second harmonic (532 nm) of a laser oscillation device (fundamental wave 1064 nm) is used. The laser oscillation mode is TEM ₀₀ Apply the single mode that is the mode.
[0043]
For silicon, which is chosen as the most suitable material, the absorption coefficient is 10 ³ -10 ⁴ cm ^-1 Is substantially in the visible light range. When crystallizing a substrate having a high visible light transmittance such as glass and an amorphous semiconductor film formed with silicon to have a thickness of 30 to 200 nm, irradiation with light in a visible light region having a wavelength of 400 to 700 nm is performed. By selectively heating the semiconductor film, crystallization can be performed without damaging the base insulating film. Specifically, the penetration length of light having a wavelength of 532 nm is approximately 100 nm to 1000 nm with respect to the amorphous silicon film, and sufficiently reaches the inside of the amorphous semiconductor film 106 having a thickness of 30 nm to 200 nm. it can. That is, heating can be performed from the inside of the semiconductor film, and substantially the entire semiconductor film in the laser light irradiation region can be uniformly heated.
[0044]
The laser light is scanned in a direction parallel to the direction in which the linear stripe pattern extends, and the melted semiconductor flows into the recesses due to surface tension and solidifies. In the solidified state, the surface becomes almost flat as shown in FIG. This is because once the semiconductor is melted, the interface between the melted semiconductor and the gas phase reaches an equilibrium state, whether on a convex portion or a concave portion, and a flat interface is formed. Further, a crystal growth end and a crystal grain boundary are formed on the second insulating film (on the convex portion) (region 110 shown by hatching in the figure). Thus, the crystalline semiconductor film 107 is formed.
[0045]
After that, heat treatment is preferably performed at 500 to 600 ° C. to remove strain accumulated in the crystalline semiconductor film. This distortion is caused by volume shrinkage of the semiconductor caused by crystallization, thermal stress with the base, lattice mismatch, and the like. This heat treatment may be performed using a normal heat treatment apparatus, but may be performed, for example, for 1 to 10 minutes using a gas heating type instantaneous thermal annealing (RTA) method. This step is not an essential requirement in the present invention, and may be appropriately selected and performed.
[0046]
Thereafter, as shown in FIG. 4, the crystalline semiconductor film 107 is etched to form an active layer 108 of the thin film transistor. At this time, the region 110 where the growth edge and the crystal grain boundary are concentrated may be left partially. A feature of the present invention is that the second crystalline semiconductor region including the region 110 is positively utilized as an electrode such as a source region and a drain region of a thin film transistor, so that an electrode ( The purpose is to secure a design margin of a contact portion (regions 111 and 112 in FIG. 4) with a source electrode or a drain electrode. Needless to say, the semiconductor regions with high crystallinity (first crystalline semiconductor regions) 109a and 109b formed in the concave portions are used as channel formation regions of the thin film transistor.
[0047]
The semiconductor regions 109a and 109b having high crystallinity have a feature that they have a plurality of crystal orientations and no crystal grain boundaries are formed. Then, a gate insulating film and a gate electrode are formed so that the semiconductor regions 109a and 109b become channel formation regions. Through these steps, the transistor can be completed.
[0048]
FIG. 5 is a conceptual diagram showing the knowledge of crystallization obtained from the experimental results by the present inventors. FIGS. 5A to 5E schematically illustrate the relationship between the crystal growth and the depth and interval of the concave portion formed by the first insulating film and the second insulating film.
[0049]
Note that, regarding the reference numerals related to the length shown in FIG. 5, t01: the thickness of the amorphous semiconductor film on the second insulating film (convex portion), t02: the thickness of the amorphous semiconductor film in the concave portion, and t11: the second thickness. The thickness of the crystalline semiconductor film on the insulating film (convex portion), t12: the thickness of the crystalline semiconductor film in the concave portion, d: the thickness of the second insulating film (depth of the concave portion), W1: the second insulating film , W2: width of the concave portion.
[0050]
FIG. 5A shows the case where d <t02 and W1 and W2 are about the same as or less than 1 μm, and when the depth of the groove of the concave portion is smaller than that of the amorphous semiconductor film 204, the melt crystallization is performed. Even after the above process, the surface of the crystalline semiconductor film 205 is not sufficiently flattened because the recess is shallow. That is, the surface state of the crystalline semiconductor film 205 is a state in which the unevenness of the base is reflected.
[0051]
FIG. 5B shows the case where d ≧ t02 and W1 and W2 are about the same as or less than 1 μm, and when the depth of the recessed groove is substantially equal to or larger than the amorphous semiconductor film 203, Then, the surface tension acts and collects in the concave portions. As a result, in the solidified state, the surface becomes substantially flat as shown in FIG. In this case, t11 <t12, and stress concentrates on the thinner portion 220 on the second insulating film 202, where distortion is accumulated and a crystal grain boundary is formed.
[0052]
A scanning electron microscope (SEM) photograph shown in FIG. 23A shows an example of the state shown in FIG. 5B, on a base insulating film provided with a step of 170 nm and a width and interval of a projection of 0.5 μm. 3 shows a result of forming a 150 nm amorphous silicon film and crystallizing the same. In addition, the surface of the crystalline semiconductor film has a Seco solution (HF: H ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ (A chemical solution prepared using the method described above) (also referred to as Seco etching).
[0053]
The results shown in FIG. 23 indicate that potassium dichromate (K ₂ Cr ₂ O ₇ 2.) 2.2 g was dissolved in 50 cc of water to prepare a 0.15 mol / l solution, and 100 cc of a hydrofluoric acid aqueous solution was added to the solution, which was further diluted 5-fold with water and used as a Seco solution. Further, the conditions of the Seco etching were 75 seconds at room temperature (10 to 30 ° C.). In this specification, the term “Seco solution or Seco etching” refers to the solution and conditions described herein.
[0054]
FIG. 23B is a schematic diagram of the photograph of FIG. In the figure, reference numeral 31 denotes an insulating film (second insulating film) extending in a linear stripe pattern, and crystal grain boundaries 33 clarified by secco etching are intensively formed on the convex portions 32. You can see how they are. It should be noted that the region 34 described as the disappeared portion is a region corresponding to the starting point of the stripe pattern, and the scanning of the laser beam is started from this starting point. Although the detailed reason is unknown, the silicon film on the starting point is an area where the second insulating film located at the starting point has been exposed by being pushed in the scanning direction when melted. Since the Seco solution etches the silicon oxide film, the region located at the starting point has disappeared by Seco etching.
[0055]
By the way, when compared with the photograph shown in FIG. 23A, the crystalline semiconductor film formed in the concave portion 35 does not show crystal grain boundaries or defects as clarified by secco etching. Then, it turns out that it does not substantially exist. Although the crystal grain boundaries that are clarified by Seco etching have not been identified at present, it is a well-known fact that stacking faults and crystal grain boundaries are preferentially etched by Seco etching. It can be said that the crystalline semiconductor film obtained by performing the method has a significant feature in that there is substantially no crystal grain boundary or defect which becomes obvious by the seco etching.
[0056]
Of course, since it is not a single crystal, there may naturally be grain boundaries and defects that do not become apparent by seco etching, but such grain boundaries and defects are not those that affect the electrical characteristics when a semiconductor device is manufactured. No, it is considered electrically inactive. Generally, such electrically inactive grain boundaries are referred to as planar grain boundaries (lower or higher order twins or corresponding grain boundaries), and are grain boundaries that are not revealed by seco etching. Is assumed to be a planar grain boundary. From that point of view, the fact that there is substantially no crystal grain boundary or defect can be said to mean that there is no crystal grain boundary other than the planar grain boundary.
[0057]
FIG. 25 shows the result of determining the orientation of the crystalline semiconductor film formed in the concave portion 35 shown in FIG. 23B by using a backscattered electron diffraction pattern (EBSP). The EBSP is provided with a dedicated detector in a scanning electron microscope (SEM), irradiates the crystal surface with an electron beam, and allows the computer to recognize the crystal orientation from the Kikuchi line using a computer to recognize the microscopic image. The crystallinity is measured not only in the surface orientation but also in all directions of the crystal (hereinafter, this method is referred to as EBSP method for convenience).
[0058]
The data in FIG. 25 shows that crystals grow in the concave portion 35 in a direction parallel to the scanning direction of the laser light condensed linearly. The crystal orientation of growth is dominant in the <110> orientation (that is, the main orientation plane is the {110} plane), but there is also a growth in the <100> orientation.
[0059]
FIG. 5C shows a case where d ≧ t02 and W1 and W2 are about the same as or slightly larger than 1 μm. When the width of the concave portion is widened, the crystalline semiconductor film 205 fills the concave portion and has an effect of flattening. A crystal grain boundary is generated near the center of the concave portion. In addition, stress is similarly concentrated on the second insulating film, where strain is accumulated, and a crystal grain boundary is formed. It is presumed that this is because the effect of stress relaxation is reduced by increasing the interval. This condition is not preferable because crystal grain boundaries may be generated in a semiconductor region serving as a channel formation region.
[0060]
FIG. 5D shows a case where d ≧ t02 and W1 and W2 are larger than 1.0 μm, and the state of FIG. 5C becomes more apparent. Under this condition, a crystal grain boundary is generated in the semiconductor region serving as a channel formation region with a considerable probability, which is not preferable.
[0061]
A scanning electron microscope (SEM) photograph shown in FIG. 24A shows an example of the state of FIG. 5D, on a base insulating film provided with a step of 170 nm and a width and interval of a 1.8 μm convex portion. 3 shows a result of forming a 150 nm amorphous silicon film and crystallizing the same. The surface of the crystalline semiconductor film is etched with the above-mentioned Seco solution in order to make crystal grain boundaries visible.
[0062]
FIG. 24B is a schematic diagram of the photograph of FIG. In the drawing, reference numeral 41 denotes an insulating film (second insulating film) extending in a linear stripe pattern, and a crystal grain boundary 43 clarified by secco etching is concentrated on its convex portion 42 and its end. It can be seen that this has occurred. The region 44 described as a lost portion is a region corresponding to the starting point of the stripe pattern, and has been lost by secco etching for the above-described reason. Note that, in comparison with the photograph shown in FIG. 24A, the crystal grain boundaries are generated not only in the convex portions 42 but also in the concave portions 45 of the stripe pattern.
[0063]
FIG. 5E is a reference example in the present invention, where d >> t02 and W1 and W2 are 1 μm or less. That is, when the thickness d of the second insulating film is too thick compared to the thickness t02 of the amorphous semiconductor film in the concave portion, the crystalline semiconductor film 204 is formed so as to fill the concave portion. Hardly survive. Therefore, the crystalline semiconductor film over the second insulating film cannot be used as a contact portion between the source region and the source electrode (or the drain region and the drain electrode) as in the present invention.
[0064]
As described above with reference to FIGS. 5A to 5D, in the case of forming a semiconductor element, particularly, in the case of forming a channel formation region in a thin film transistor, the mode of FIG. It is thought that there is. That is, when the Seco etching is performed with the Seco solution described above, a crystalline semiconductor film in which crystal grain boundaries and defects hardly become apparent, in other words, a crystalline semiconductor film in which crystal grain boundaries and defects are substantially absent, It is desirable to use it for a channel formation region.
[0065]
In addition, here, the unevenness of the base for forming the crystalline semiconductor film is described as an example in which the base is formed of the first insulating film and the second insulating film; however, the present invention is not limited to this embodiment and has a similar shape. If there is, it can be replaced. For example, a recess having a desired depth may be formed by etching an insulating film having a thickness of about 200 nm to 2 μm.
[0066]
In the above crystallization step, if the second insulating film is a soft insulating film (low-density insulating film) as described above, an effect of relieving stress due to shrinkage of the semiconductor film during crystallization is expected. it can. Conversely, a hard insulating film (a high-density insulating film) generates stress in a manner that opposes the semiconductor film that is about to shrink or expand, so that stress distortion and the like are likely to remain in the crystallized semiconductor film. It could be the cause of For example, in a known graphoepitaxy technique (“MW Geis, DC Flanders, HI Smith: Appl. Phys. Lett. 35 (1979) pp71”), irregularities on a substrate are hardened quartz glass. In this case, it has been found that the orientation axis of the crystalline Si is the [100] axis, that is, the main orientation plane is the {100} plane.
[0067]
However, when the present invention is implemented, the main orientation plane is {110} as shown in FIG. 25, and it is apparent that semiconductor films having different crystal forms are clearly formed. The difference is due to the soft insulating film in which the irregularities on the substrate are formed by the above-described CVD method or PVD method. That is, by using a material that is softer than quartz glass for the second insulating film serving as a base, the generation of stress during crystallization can be further reduced, or the stress can be concentrated on the crystalline semiconductor film on the convex portion. did it.
[0068]
Note that an insulating film softer than quartz glass means an insulating film having a higher etching rate or an insulating film having a higher hardness than, for example, general quartz glass (quartz glass industrially used as a substrate). . Quartz glass is treated with ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ As a result of performing wet etching using a mixed solution containing 15.4% of F) (trade name: LAL500, manufactured by Stella Chemifa), the etching rate of the quartz substrate was 38 nm / min. On the other hand, since the etching rate of the second insulating film serving as the base with the same etchant is 50 to 1000 nm / min, it can be said that the insulating film is softer than quartz glass. Since the etching rate and the hardness may be determined only by relative comparison with quartz glass, they do not depend on the measurement conditions of the etching rate or the hardness.
[0069]
For example, if a silicon oxynitride film is used as the second insulating film, SiH ₄ Gas, N ₂ A silicon oxynitride film formed by a plasma CVD method using O gas as a raw material is preferable. The silicon oxynitride film is formed of ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ The etching rate at 20 ° C. of the mixed aqueous solution containing 15.4% of F) is 110 to 130 nm / min (90 to 100 nm / min after heat treatment at 500 ° C., 1 hour + 550 ° C. for 4 hours).
[0070]
If a silicon oxynitride film is used as the second insulating film, SiH ₄ Gas, NH ₃ Gas, N ₂ A silicon oxynitride film formed by a plasma CVD method using O gas as a raw material is preferable. The silicon oxynitride film is formed of ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ The etching rate at 20 ° C. of the mixed aqueous solution containing 15.4% of F) is 60 to 70 nm / min (40 to 50 nm / min after heat treatment at 500 ° C., 1 hour + 550 ° C. for 4 hours).
[0071]
As described above, a linear stripe pattern having a concave portion and a convex portion is formed by an insulating film, an amorphous semiconductor film is deposited thereon, and crystallized through a molten state by irradiation with a laser beam. The semiconductor is poured into the substrate and solidified, and strain or stress due to crystallization can be concentrated in a region other than the concave portion, so that a region having poor crystallinity such as a crystal grain boundary can be selectively formed. A feature of the present invention is that a semiconductor region with good crystallinity is used as a region where carrier movement is performed, such as a channel formation region of a thin film transistor, and a semiconductor region with poor crystallinity is used as a contact portion with an electrode.
[0072]
That is, a crystalline semiconductor film in which a plurality of crystal grains having a plurality of crystal orientations in a recess and having a plurality of crystal grains extending in a direction parallel to a direction in which a linear stripe pattern extends without forming a crystal grain boundary are formed. Can be formed. By forming a transistor so that a channel formation region is provided with such a crystalline semiconductor film, a transistor or a transistor group which can operate at high speed, has high current driving capability, and has small variation among a plurality of elements. Can be formed.
[0073]
[Embodiment 2]
In the formation of the crystalline semiconductor film of the present invention, in addition to the method of irradiating the amorphous semiconductor film with laser light to crystallize it as described in Embodiment 1, the laser light May be applied for melting and recrystallization.
[0074]
For example, after the amorphous semiconductor film 106 is formed in FIG. 2, crystallization is promoted by lowering the crystallization temperature of the amorphous semiconductor film (eg, an amorphous silicon film) to improve the orientation. Ni is added as a catalytic metal element.
[0075]
The details of this technique are described in JP-A-11-354442 by the present applicant. A crystalline semiconductor film formed by adding Ni has a feature that a main orientation plane is a {110} plane. When such a crystalline semiconductor film is used for a channel formation region of a thin film transistor, electron mobility and electron mobility can be reduced. The hole mobility is greatly improved, and the field-effect mobility of the N-channel transistor and the P-channel transistor is greatly improved. Particularly, the improvement of the field-effect mobility of the P-channel transistor accompanying the improvement of the hole mobility is remarkable, and is one of the advantages of setting the main orientation plane to {110}.
[0076]
The method for adding Ni is not limited, and a spin coating method, an evaporation method, a sputtering method, or the like can be used. In the case of spin coating, a 5 ppm aqueous solution of nickel acetate is applied to form a metal element-containing layer. Of course, the catalyst element is not limited to Ni, and other known materials may be used.
[0077]
Thereafter, the amorphous semiconductor film 106 is crystallized by a heat treatment at 580 ° C. for 4 hours. The crystallized semiconductor film is irradiated with a laser beam or an equivalent strong light to be melted and recrystallized. Thus, a crystalline semiconductor film whose surface is almost flattened as in FIG. 3 can be obtained. In this crystalline semiconductor film, similarly, a region where the growth edge and the crystal grain boundary 110 are formed is formed.
[0078]
The advantage of using a crystallized semiconductor film as an object to be irradiated with laser light lies in the rate of change of the light absorption coefficient of the semiconductor film. Even if the crystallized semiconductor film is irradiated with laser light and melted, the light absorption coefficient is reduced. Hardly fluctuates. Therefore, the margin of the laser irradiation condition can be widened.
[0079]
Although the metal element remains in the thus formed crystalline semiconductor film, it can be removed by gettering. For details of this technique, refer to Japanese Patent Application No. 2001-019367 (or Japanese Patent Application No. 2002-020801). Further, the heat treatment accompanying the gettering treatment also has an effect of alleviating distortion of the crystalline semiconductor film.
[0080]
After that, as in Embodiment 1, a thin film transistor is formed using the crystalline semiconductor film in the concave portion as a channel formation region and using the crystalline semiconductor film in the convex portion as a source region or a drain region. Since the crystalline semiconductor film in the concave portion has a feature that it has a plurality of crystal orientations and no crystal grain boundary is formed, high-speed operation is possible, current driving capability is high, and variation among a plurality of elements is caused. , Or a semiconductor device including the transistor group or the transistor group can be formed.
[0081]
[Embodiment 3]
Next, an embodiment in which a crystalline silicon film is formed over a base insulating film having a recess in this embodiment and a transistor in which a channel formation region is provided in a semiconductor region formed in the recess is described. It will be described using FIG. In each of the drawings according to the present embodiment, (A) shows a top view, and (B) and subsequent drawings show longitudinal sectional views of corresponding parts.
[0082]
In FIG. 6, a first insulating film 302 made of 30 to 300 nm of silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride whose nitrogen content is larger than oxygen content is formed over a glass substrate 301. A linear stripe pattern having a concave portion and a convex portion thereon is formed by the second insulating film 303 made of silicon oxide or silicon oxynitride. The silicon oxide film is made of TEOS and O by plasma CVD. ₂ At a reaction pressure of 40 Pa, a substrate temperature of 400 ° C., and a high frequency (13.56 MHz) power density of 0.6 W / cm. ² And deposit the film to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm, and then form the concave portion 304 by etching. The width of the concave portion is formed at 0.01 to 1 μm, preferably 0.05 to 0.2 μm, particularly at a position where the channel formation region is arranged.
[0083]
Next, as shown in FIG. 7, on the first insulating film 302 and the second insulating film 303, a third insulating film 305 made of an oxide film or a silicon oxynitride film and an amorphous silicon film 306 are formed by the same plasma CVD apparatus. The film is continuously formed without being exposed to the atmosphere. The amorphous silicon film 305 is formed of a semiconductor film containing silicon as a main component, and is made of SiH by a plasma CVD method. ₄ Is formed as a source gas. At this stage, the bottom and side surfaces of the recess 304 are covered to form an uneven surface shape as shown in the figure.
[0084]
The crystallization is performed by irradiating continuous wave laser light. FIG. 8 shows the state after the crystallization. Crystallization conditions are YVO in continuous oscillation mode. ₄ Using a laser oscillator, the output of the second harmonic (wavelength: 532 nm) of 5 to 10 W is condensed by an optical system into a linear laser beam having a ratio of the longitudinal direction to the lateral direction of 10 or more, and the longitudinal direction. The light is condensed so as to have a uniform energy density distribution, and is crystallized by scanning at a speed of 5 to 200 cm / sec. Uniform energy density distribution does not exclude anything that is completely constant, and the allowable range of energy density distribution is ± 10%.
[0085]
It is desirable that the intensity distribution of the laser light condensed linearly is uniform in the direction of longer length (the X-axis direction in FIG. 3). The purpose of this is to make the temperature of the semiconductor to be heated uniform over the entire irradiation area of the laser beam. This is because if a temperature distribution occurs in the X-axis direction of the laser light condensed linearly, the direction of crystal growth of the semiconductor film cannot be defined in the scanning direction of the laser light. By arranging the linear stripe pattern in alignment with the scanning direction of the irradiation region of the laser beam condensed linearly, the crystal growth direction and the channel length direction of all transistors can be matched. . Thus, variation in characteristics between the elements of the transistor can be reduced.
[0086]
Further, the crystallization by the laser light condensed linearly may be completed by only one scan (that is, in one direction), or may be performed by reciprocating scan to further improve the crystallinity. Furthermore, after crystallization by laser light, the surface of the silicon film is treated with an alkaline solution such as removal of oxides by hydrofluoric acid or an aqueous solution of ammonia and hydrogen peroxide to selectively remove poor-quality portions having a high etching rate. After removal, the same crystallization treatment may be performed again. Thus, crystallinity can be improved.
[0087]
By irradiating a laser beam under these conditions, the amorphous semiconductor film is instantaneously melted and crystallized. The crystallization proceeds while the melting zone moves substantially. The molten silicon is aggregated and solidified in the concave portions by the surface tension. Thus, a crystalline semiconductor film 307 having a flat surface is formed so as to fill the concave portion 304 as shown in FIG.
[0088]
After that, as shown in FIG. 9, the crystalline semiconductor film 307 is etched to form semiconductor regions 308 to 310 to be active layers of the thin film transistor. FIG. 9 does not limitly show the shapes of the semiconductor regions 308 to 310, and as described in the first embodiment, is not particularly limited as long as it follows a predetermined design rule.
[0089]
The crystalline semiconductor film 307 can be selectively etched with the third insulating film 305 by using a fluorine-based gas and oxygen as an etching gas. Of course, even if the third insulating film 305 is etched, there is no problem as long as the selectivity with the underlying first and second insulating films 302 and 303 can be ensured.
[0090]
In addition, as an etching method, CF ₄ And O ₂ Mixed gas and NF ₃ It may be performed by a plasma etching method using a gas, ₃ Plasmaless gas etching using a halogen fluoride gas such as a gas without being excited may be performed. Plasmaless gas etching is an effective method for suppressing crystal defects because plasma damage to a crystalline semiconductor film is not required.
[0091]
Next, as shown in FIG. 10, a fourth insulating film (functioning as a gate insulating film) 311, a conductive film 312 used as a gate electrode is formed so as to cover the upper surfaces of the semiconductor regions 308 to 310 and the second insulating film 303. 313 is formed. The fourth insulating film 311 is formed using the silicon oxide film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film, aluminum oxynitride film, or aluminum oxide film described in Embodiment 1. Any of them may be used, or a laminated film in which these are appropriately combined may be used.
[0092]
In order to improve the coverage of the gate insulating film, a silicon oxide film using TEOS is preferable for a silicon oxide film, and an aluminum oxynitride film formed by an RF sputtering method is used for an aluminum oxynitride film. It is preferable to use a stacked film of an aluminum oxide film and a silicon oxide film (a silicon oxide film may be obtained by oxidizing a semiconductor film to be an active layer with hydrogen peroxide).
[0093]
The conductive films 312 and 313 used as the gate electrodes are formed using tungsten, an alloy containing tungsten, aluminum, an aluminum alloy, or the like.
[0094]
Next, as shown in FIG. 11, impurity regions 314 to 319 of one conductivity type are formed in the semiconductor regions 308 to 310. Here, n-type impurity regions 314, 315, 318 and 319 and p-type impurity regions 316 and 317 are provided for convenience. These impurity regions may be formed in a self-aligned manner using the conductive films 312 and 313 used as gate electrodes as a mask, or may be formed by masking with a photoresist or the like. The impurity regions 314 to 319 form source and drain regions, and a low-concentration drain region (generally called an LDD region) can be provided as necessary.
[0095]
For the impurity regions 314 to 319, an ion implantation method or an ion doping method in which impurity ions are accelerated by an electric field and implanted into a semiconductor region is applied. In this case, the presence or absence of mass separation of the ion species to be implanted is not an essential problem in applying the present invention.
[0096]
At this time, of the semiconductor regions 308 to 310, the semiconductor region 320 below the gate electrodes 312 and 313 and formed in the recess 304 becomes a channel formation region of the thin film transistor of the present invention.
[0097]
Then, as shown in FIG. 12, a fifth insulating film (functioning as a passivation film) 321 of a silicon nitride film or a silicon oxynitride film containing hydrogen of about 50 to 100 nm is formed. By performing a heat treatment at 400 to 450 ° C. in this state, hydrogen contained in the silicon nitride film or the silicon oxynitride film is released, so that the island-shaped semiconductor film can be hydrogenated.
[0098]
Next, a sixth insulating film (functioning as an interlayer insulating film) 322 formed of a silicon oxide film or the like is formed, and wirings 323 to 327 connected to the impurity regions 314 to 319 are formed. Thus, n-channel transistors 328 and 330 and a p-channel transistor 329 can be formed.
[0099]
In an n-channel transistor 328 and a p-channel transistor 329 illustrated in FIG. 12, a plurality of channel formation regions 320 are provided in parallel and a pair of impurity regions 314 and 315 (or 316 and 317) 3 shows a multi-channel transistor provided in series. Specifically, an example is shown in which an n-channel multi-channel transistor 328 and a p-channel multi-channel transistor 329 form an inverter circuit which is a basic circuit having a CMOS structure. In this configuration, the number of channel formation regions arranged in parallel is not limited, and a plurality of channel formation regions may be arranged as needed. For example, a single channel like the n-channel transistor 330 may be used.
[0100]
[Embodiment 4]
In Embodiment 3, the transistor has a single-drain structure; however, a low-concentration drain (LDD) may be provided. FIG. 13 illustrates an example of an n-channel multi-channel transistor having an LDD structure.
[0101]
The structure of the transistor illustrated in FIG. 13A is an example in which a gate electrode is formed using a nitride metal 340a such as titanium nitride or tantalum nitride and a high-melting metal 340b such as tungsten or a tungsten alloy. Provided. The spacer 341 may be formed of an insulator such as silicon oxide, may be formed of n-type polycrystalline silicon for imparting conductivity, and is formed by anisotropic dry etching. By forming the LDD regions 342a and 342b before forming the spacer, the LDD regions 342a and 342b can be formed in a self-aligned manner with respect to the gate electrode 340b. When the spacer is formed using a conductive material, a gate-overlapped LDD (Gate-Overlapped LDD) structure in which the LDD regions 342a and 342b substantially overlap the gate electrode can be provided.
[0102]
On the other hand, FIG. 13B shows a structure in which the gate electrode 340a is not provided. In this case, an LDD structure is provided.
[0103]
In FIG. 13C, an n-type impurity region 344 forming an LDD region is formed adjacent to the n-type impurity region 315. The gate electrode 343 has a two-layer structure of a lower gate electrode 343a and an upper gate electrode 343b, and can form n-type impurity regions 314 and 315 and LDD regions 344a and 344b in a self-aligned manner. For details of such a gate electrode and an impurity region and a manufacturing method thereof, refer to Japanese Patent Application No. 2000-128526 or Japanese Patent Application No. 2001-011085.
[0104]
In any case, the structure in which the LDD region is formed in a self-aligned manner by such a gate structure is particularly effective in miniaturizing a design rule. Although a unipolar transistor structure is shown here, a CMOS structure can be formed as in the fourth embodiment.
[0105]
Note that the present embodiment is the same as Embodiment 3 except for the configuration of the gate electrode and the LDD region, and a detailed description is omitted.
[0106]
[Embodiment 5]
This embodiment is an embodiment different from the structure described in Embodiment 1, and relates to an invention in which one conductivity type impurity region functioning as an electrode is used as a wiring as it is. In this embodiment, the number of contact portions is reduced to improve the degree of integration by reducing the design margin and to improve the yield.
[0107]
FIG. 14 is used for the description. FIG. 14A is a top view, and FIGS. 14B to 14F are cross-sectional views of corresponding portions. FIG. 12 is a diagram corresponding to the state of FIG. 11 in the first embodiment. Embodiment 1 can be referred to for a process to reach this state and a subsequent transistor formation process.
[0108]
In FIG. 14A, 401 to 405 are impurity regions of one conductivity type, 401 and 402 are source and drain regions of a P-channel transistor, respectively, and 403 and 404 are source regions of an N-channel transistor, respectively. , 405 function as drain regions of N-channel transistors. At this time, a feature is that the drain region 405 functions as a wiring for electrically connecting the two transistors.
[0109]
As a feature of the present invention, a semiconductor region with poor crystallinity can also be used as an electrode. Therefore, as in this embodiment, the number of contact portions can be reduced by using it as a wiring, and the contact formation can be reduced. Design margin can be expanded. Therefore, it is very effective especially when forming a miniaturized logic circuit.
[0110]
Note that this embodiment is merely an example, and in the present invention, discloses a technical idea that an impurity region of one conductivity type can be used not only as an electrode but also as a wiring. Therefore, the effects described in the present embodiment can be obtained by combining any of the techniques disclosed in the first to fourth embodiments.
[0111]
Embodiment 6
This embodiment is another embodiment different from the structure described in Embodiment 1, in which a transistor having a structure in which a plurality of transistors are connected in series is formed by using an impurity region of one conductivity type as a wiring. The invention relates to the invention characterized in that: This embodiment discloses that a transistor having a plurality of channel formation regions between a source region and a drain region can be obtained, and shows a further embodiment of the present invention.
[0112]
FIG. 15 is used for the description. FIG. 15A is a top view, and FIGS. 15B to 15F are cross-sectional views of corresponding portions. FIG. 12 is a diagram corresponding to the state of FIG. 11 in the first embodiment. Embodiment 1 can be referred to for a process to reach this state and a subsequent transistor formation process.
[0113]
In FIG. 15A, reference numerals 411 to 418 denote impurity regions of one conductivity type, reference numerals 411 and 414 denote source and drain regions of a P-channel transistor, and reference numerals 412 and 413 denote impurity regions used as wiring. Note that a feature of the present invention is that the area occupied by the impurity regions 412 and 413 can be increased, so that the portion can be used simply as a wiring or can be used as an electrode with an increased area. In addition, it is also possible to provide a function as a protection circuit by processing into a bent shape.
[0114]
Reference numeral 415 denotes a source region of the single-channel N-channel transistor, and 416 denotes a drain region thereof. Further, a transistor including the drain region 416 as a source region and the impurity region 418 as a drain region is formed. In this case, the impurity region 417 functions as a wiring. The transistor has a total of three channel formation regions, two of which are provided in parallel and connected in series with the other. Needless to say, this embodiment is not limited to the structure of the transistor.
[0115]
Note that this embodiment is merely an example, and in the present invention, discloses a technical idea that an impurity region of one conductivity type can be used not only as an electrode but also as a wiring. Therefore, it may be combined with any of the techniques disclosed in the first to fifth embodiments.
[0116]
Embodiment 7
In the transistor of the present invention, by providing a conductive layer on the lower layer side, a so-called substrate bias can be applied. The method for manufacturing the transistor is in accordance with Embodiment Mode 3, but the difference will be described with reference to FIGS.
[0117]
In FIG. 16A, a silicon nitride film is formed as a first insulating film 802 over a substrate, and a tungsten film 803 is formed thereover by a sputtering method. In particular, when a silicon nitride film is formed by a high-frequency sputtering method, a dense film can be formed. The second insulating film 804 is formed using a silicon oxide film. The silicon oxide film forms a concave portion by etching as shown in the figure, but can be easily processed since the selectivity with the underlying tungsten film is about 30.
[0118]
Over this, a silicon oxynitride film and an amorphous silicon film 806 are successively formed as a third insulating film 805, and the amorphous semiconductor film 806 is melt-crystallized, and as shown in FIG. A silicon film 807 is formed. After that, as illustrated in FIG. 16C, a channel formation region 808 of the transistor is formed by etching, so that a gate insulating film 809 and a gate electrode 810 are formed. Since the gate insulating film 809 is formed over the tungsten film 803, there is no short circuit with the gate electrode 810.
[0119]
In such a mode, when the tungsten film 803 is fixed to the ground potential, variation in the threshold voltage of the transistor can be reduced. When the gate electrode 810 is driven by applying the same potential as that of the gate electrode 810, the on-state current can be increased.
[0120]
In order to enhance the heat dissipation effect, an aluminum oxynitride film (or aluminum nitride film) 811 is preferably formed over the tungsten film 803 as shown in FIG. The purpose of providing these films is to secure a selectivity of the etching process. That is, CHF ₃ In order to remove silicon oxide as the second insulating film 804 with a fluorine-based etching gas and not to expose the underlying tungsten film 803, a silicon nitride film has a small selectivity and an aluminum nitride film or an aluminum oxynitride film is used. Is suitable.
[0121]
This embodiment discloses a configuration in which a conductive film is provided under a second insulating film that forms a convex portion and a concave portion to achieve a heat radiation effect and control a threshold value during an actual operation. Combinations with the configurations disclosed in Embodiment Modes 1 to 6 are possible, and the effects described in the present embodiment can be imparted by the combination.
[0122]
Embodiment 8
In this embodiment, an example in which a part of the crystalline semiconductor film 307 (a part to be a channel formation region later) is thinned before the step of forming the active layer 308 of the thin film transistor in Embodiment 3 is described. Show.
[0123]
First, the state illustrated in FIG. 8 is obtained according to the manufacturing method described in Embodiment 3. Next, a resist mask 1801 is formed over a semiconductor region which is to be a source region or a drain region later in the crystalline semiconductor film 307 (FIG. 18A).
[0124]
Then, the crystalline semiconductor film 307 is etched by a dry etching method or a wet etching method using the resist mask 1801 as a mask, so that the third insulating film 305 serving as a base is exposed. Through this step, the crystalline semiconductor film 1802 can be selectively left only in the concave portions. Further, a crystalline semiconductor film 1803 having the original thickness remains under the resist mask 1801. This embodiment is characterized in that the crystalline semiconductor film 17802 is used as a channel formation region of the thin film transistor and the crystalline semiconductor film 1803 is used as a source region or a drain region of the thin film transistor.
[0125]
The etching step may use not only a chemical method but also a mechanical polishing method such as CMP (Chemical Mechanical Polishing). Further, a chemical method and a mechanical method may be used in combination.
[0126]
According to this embodiment, since the channel formation region can be formed in a self-aligned manner by the second insulating film 303, the channel formation region is erroneously formed on the convex portion of the second insulating film due to a pattern shift. Can be prevented, and a situation in which a crystal grain boundary is included in the channel formation region can be reduced.
[0127]
For the subsequent steps, the steps after FIG. 10 in the third embodiment may be referred to, and the description in the present embodiment will be omitted. This embodiment can be freely combined with any of Embodiments 1 to 7.
[0128]
Embodiment 9
The present invention can be applied to various semiconductor devices, and a mode of a display panel manufactured based on Embodiment Modes 1 to 8 will be described. Note that specific examples of the display panel described in this embodiment include a display panel using a transistor as a semiconductor element such as a liquid crystal display panel, an EL (electroluminescence) display panel, and a FED (field emission display) display panel. . Of course, these display panels include those that are marketed as modules.
[0129]
19, a substrate 900 includes a pixel portion 902, gate signal side driver circuits 901a and 901b, a data signal side driver circuit 901c, an input / output terminal portion 908, and a wiring or a wiring group 917.
[0130]
The seal pattern 940 is a pattern for creating a sealed space between the opposing substrate 920 and the substrate 900. In the case of a liquid crystal display panel, liquid crystal is sealed, and in the case of an EL panel, an EL material (particularly, an organic EL material) is protected from the outside air. Play a role. The gate signal side driver circuits 901a and 901b, the data signal side driver circuit 901c, and the wiring or the wiring group 917 connecting the driver circuit portion and the input terminal may partially overlap. With this configuration, the area of the frame region (the peripheral region of the pixel portion) of the display panel can be reduced. An FPC (flexible print circuit) 936 is fixed to the external input terminal.
[0131]
Further, a chip in which various logic circuits, high-frequency circuits, memories, microprocessors, media processors / DSPs (Digital Signal Processors), graphics LSIs, cryptographic LSIs, amplifiers, and the like are formed using transistors obtained by implementing the present invention. 950 may be implemented. These functional circuits are formed with design rules different from those of the pixel portion 902, the gate signal side drive circuits 901a and 901b, and the data signal side drive circuit 901c. Specifically, a design rule of 1 μm or less is applied. You. Note that the external input terminal portion and the chip 950 are preferably protected by a resin (mold resin or the like) 937. The mounting method is not limited, and a method using a TAB tape, a COG (chip on glass) method, or the like can be applied.
[0132]
Note that in this embodiment, FIGS. 13A and 13B are suitable as the gate structure of the transistor. For example, the transistors described in Embodiments 3 and 4 can be applied as switching elements of the pixel portion 902, and further, as active elements included in the gate signal driver circuits 901a and 901b and the data signal driver circuit 901c. Of course, the present embodiment shows an example of a display panel obtained by carrying out the present invention, and is not limited to the configuration in FIG.
[0133]
[Embodiment 10]
Various electronic devices can be completed using the present invention. Examples include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a digital camera, a personal computer, a television set, a mobile phone, and the like. Examples of those are shown in FIG. Note that the electronic device shown here is merely an example, and is not limited to these applications.
[0134]
FIG. 20A illustrates an example in which a television receiver is completed by applying the present invention, which includes a housing 3001, a support base 3002, a display portion 3003, and the like. In the transistor manufactured by the present invention, in addition to the display portion 3003, various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, and graphics LSIs can be formed and incorporated on glass. According to the invention, a television receiver can be completed.
[0135]
FIG. 20B illustrates an example in which a video camera is completed by applying the present invention, which includes a main body 3011, a display portion 3012, a sound input portion 3013, operation switches 3014, a battery 3015, an image receiving portion 3016, and the like. . In the transistor manufactured by the present invention, in addition to the display portion 3012, various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, and LSIs for graphics can be formed and incorporated on glass. According to the invention, a video camera can be completed.
[0136]
FIG. 20C illustrates an example in which a notebook personal computer is completed by applying the present invention, which includes a main body 3021, a housing 3022, a display portion 3023, a keyboard 3024, and the like. In addition to the display portion 3023, various integrated circuits such as a logic circuit, a high-frequency circuit, a memory, a microprocessor, a media processor, a graphics LSI, a cryptographic LSI, and the like can be formed and incorporated on a glass. According to the present invention, a personal computer can be completed.
[0137]
FIG. 20D shows an example in which a PDA (Personal Digital Assistant) is completed by applying the present invention, and includes a main body 3031, a stylus 3032, a display portion 3033, operation buttons 3034, an external interface 3035, and the like. In addition to the display portion 3033, various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, cryptographic LSIs, and the like can be formed on a glass and incorporated in the transistor manufactured by the present invention. According to the present invention, a PDA can be completed.
[0138]
FIG. 20E illustrates an example in which a sound reproduction device is completed by applying the present invention, specifically, an audio device for a vehicle, which includes a main body 3041, a display portion 3042, operation switches 3043, 3044, and the like. Have been. In addition to the display portion 3042, various integrated circuits such as a logic circuit, a high-frequency circuit, a memory, a microprocessor, a media processor, a graphics LSI, and an amplifier circuit can be formed over glass and incorporated in the transistor manufactured by the present invention. According to the present invention, an audio device can be completed.
[0139]
FIG. 20F illustrates an example in which a digital camera is completed by applying the present invention. A main body 3051, a display portion (A) 3052, an eyepiece portion 3053, operation switches 3054, a display portion (B) 3055, and a battery 3056 are shown. Etc. The transistors manufactured by the present invention include various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, cryptographic LSIs, in addition to the display portion (A) 3052 and the display portion (B) 3055. Can be formed and incorporated on glass, and a digital camera can be completed according to the present invention.
[0140]
FIG. 20G illustrates an example in which a mobile phone is completed by applying the present invention, which includes a main body 3061, an audio output portion 3062, an audio input portion 3063, a display portion 3064, operation switches 3065, an antenna 3066, and the like. I have. In the transistor manufactured by the present invention, in addition to the display portion 3064, various integrated circuits such as various logic circuits, high-frequency circuits, memories, microprocessors, media processors, graphics LSIs, cryptographic LSIs, and mobile phone LSIs are formed on glass. And a mobile phone can be completed by the present invention.
[0141]
[Embodiment 11]
In this embodiment mode, a structure of a laser irradiation apparatus used for carrying out the present invention will be described with reference to FIGS. Reference numeral 11 denotes a laser oscillation device. Although two laser oscillators are used in FIG. 21, the number of laser oscillators is not limited to this number, and may be three, four, or more.
[0142]
Further, the temperature of the laser oscillation device 11 may be kept constant by using the chiller 12. The chiller 12 is not necessarily provided, but by keeping the temperature of the laser oscillation device 11 constant, it is possible to suppress the energy of the output laser light from fluctuating due to the temperature.
[0143]
An optical system 14 can condense laser light by changing the optical path output from the laser oscillation device 11 or processing the shape of the laser beam. Further, in the laser irradiation apparatus of FIG. 21, the laser beams of the laser lights output from the plurality of laser oscillation apparatuses 11 can be synthesized by partially overlapping each other by the optical system 14.
[0144]
Note that the AO modulator 13 that can completely and completely block the laser light may be provided in the optical path between the substrate 16 to be processed and the laser oscillation device 11. Further, an attenuator (light amount adjustment filter) may be provided instead of the AO modulator to adjust the energy density of the laser light.
[0145]
Further, a means (energy density measuring means) 20 for measuring the energy density of the laser light output from the laser oscillation device 11 was provided in the optical path between the substrate 16 which is an object to be processed and the laser oscillation device 11, and the measurement was performed. The change over time in the energy density may be monitored by the computer 10. In this case, the output from the laser oscillation device 10 may be increased so as to compensate for the attenuation of the energy density of the laser light.
[0146]
The synthesized laser beam is applied to a substrate 16 as an object to be processed through a slit 15. The slit 15 is desirably formed of a material that can block laser light and is not deformed or damaged by the laser light. The width of the slit 15 is variable, and the width of the laser beam can be changed according to the width of the slit.
[0147]
Note that the shape of the laser beam on the substrate 16 of the laser light oscillated from the laser oscillator 11 when not passing through the slit 15 varies depending on the type of laser, and can be formed by an optical system.
[0148]
The substrate 16 is placed on a stage 17. In FIG. 21, the position control means 18 and 19 correspond to the means for controlling the position of the laser beam on the workpiece, and the position of the stage 17 is controlled by the position control means 18 and 19. In FIG. 21, the position control means 18 controls the position of the stage 17 in the X direction, and the position control means 19 controls the position of the stage 17 in the Y direction.
[0149]
Further, the laser irradiation apparatus of FIG. 21 has a computer 10 having both storage means such as a memory and a central processing unit. The computer 10 controls the oscillation of the laser oscillation device 151, determines the scanning path of the laser light, and controls the position control means 18 and 19 so that the laser beam of the laser light is scanned according to the defined scanning path. Thus, the substrate can be moved to a predetermined position.
[0150]
In FIG. 21, the position of the laser beam is controlled by moving the substrate. However, the position may be moved using an optical system such as a galvanometer mirror or both.
[0151]
Further, in FIG. 21, the width of the slit 15 can be controlled by the computer 10 to change the width of the laser beam according to the pattern information of the mask. Note that the slit need not always be provided.
[0152]
Further, the laser irradiation device may include a means for adjusting the temperature of the object to be processed. Further, since the laser light is light having high directivity and energy density, a damper may be provided to prevent the reflected light from being applied to an inappropriate portion. The damper desirably has a property of absorbing the reflected light, and cooling water may be circulated in the damper to prevent the temperature of the partition from rising due to the absorption of the reflected light. Further, means for heating the substrate (substrate heating means) may be provided on the stage 157.
[0153]
When the marker is formed with a laser, a laser oscillation device for the marker may be provided. In this case, the computer 10 may control the oscillation of the marker laser oscillator. Further, when a marker laser oscillation device is provided, an optical system for condensing laser light output from the marker laser oscillation device is separately provided. The laser used to form the marker is typically a YAG laser or CO2 laser. ₂ Although a laser and the like can be mentioned, it is of course possible to form by using another laser.
[0154]
In addition, one CCD camera 21 may be provided for positioning using a marker, and in some cases, several CCD cameras 21 may be provided. Note that a CCD camera means a camera using a CCD (charge-coupled device) as an imaging device. Alternatively, the pattern of the insulating film or the semiconductor film may be recognized by the CCD camera 21 without using the marker, and the alignment of the substrate may be performed. In this case, the position information of the substrate is grasped by comparing the pattern information of the insulating film or the semiconductor film by the mask input to the computer 10 with the actual pattern information of the insulating film or the semiconductor film collected by the CCD camera 21. can do. In this case, there is no need to separately provide a marker.
[0155]
In addition, the laser light incident on the substrate is reflected on the surface of the substrate and returns on the same optical path as when the laser light is incident. The return light becomes so-called return light. Adverse effects. Therefore, an isolator may be provided to remove the return light and stabilize laser oscillation.
[0156]
Although FIG. 21 shows the configuration of a laser irradiation device provided with a plurality of laser oscillation devices, there is an advantage that the design of the optical system is facilitated by doing so. In the present invention, it is particularly preferable to use a linear laser beam when melting the amorphous semiconductor film from the viewpoint of improving the throughput. However, if the lengthwise direction (X-axis direction in FIG. 3) becomes longer, the optical design becomes very precise. Therefore, the burden on the optical design can be reduced by using a plurality of linear laser beams in a superimposed manner. Can be.
[0157]
For example, one linear laser light can be formed by optically combining a plurality of laser lights oscillated from a plurality of laser oscillation devices. FIG. 22A shows an irradiation cross section of each laser beam. Here, the case where the laser light irradiation region has an elliptical shape is taken as an example, but there is no difference depending on the shape.
[0158]
The shape of the laser beam differs depending on the type of laser, and can be formed by an optical system. For example, the shape of the laser light emitted from a Lamda XeCl excimer laser (wavelength 308 nm, pulse width 30 ns) L3308 is a rectangular shape of 10 mm × 30 mm (both half widths in a beam profile). The shape of the laser beam emitted from the YAG laser is circular if the rod shape is cylindrical, and rectangular if the rod shape is slab. By further forming such a laser beam with an optical system, a laser beam having a desired size can be produced.
[0159]
FIG. 22B shows the energy density distribution of the laser light in the major axis direction (X-axis direction) of the laser light shown in FIG. The laser light shown in FIG. 21A is 1 / e of the peak value of the energy density in FIG. ² Corresponds to the region satisfying the energy density of The distribution of the energy density of the laser light in which the laser light has an elliptical shape becomes higher toward the center O of the ellipse. As described above, in the laser light illustrated in FIG. 22A, the energy density in the central axis direction follows a Gaussian distribution, and the area where the energy density can be determined to be uniform is narrow.
[0160]
Next, FIG. 22C shows an irradiation cross-sectional shape of a linear laser beam when two laser beams shown in FIG. 22A are combined. Note that FIG. 22C illustrates the case where one laser beam is formed by superimposing two laser beams; however, the number of laser beams to be superimposed is not limited to this.
[0161]
As shown in FIG. 22C, each laser beam is synthesized by matching the major axes of the ellipses and partially overlapping the laser beams, thereby forming one linear laser beam 30. . Hereinafter, a straight line obtained by connecting the centers O of the ellipses will be referred to as the central axis of the laser beam 30.
[0162]
FIG. 22D shows a distribution of energy density in the center axis y direction of the combined linear laser light shown in FIG. 22C. Note that the laser light illustrated in FIG. 22C is 1 / e of the peak value of the energy density in FIG. ² Corresponds to the region satisfying the energy density of The energy density is added in the portion where the respective laser beams before combining overlap. For example, as shown, when the energy densities L1 and L2 of the laser beams overlapping each other are added, the peak values L3 of the energy densities of the individual laser beams become substantially equal, and the energy densities are flattened between the centers O of the ellipses. .
[0163]
It should be noted that, when L1 and L2 are added, it is ideally equal to L3, but actually, they do not always have the same value. The allowable range of the difference between the value obtained by adding L1 and L2 and the value of L3 can be appropriately set by a designer.
[0164]
When the laser light is used alone, it is difficult to irradiate the entire semiconductor film in contact with the flat portion of the insulating film with the laser light having a uniform energy density because the energy density follows a Gaussian distribution. However, as can be seen from FIG. 22 (D), by overlapping a plurality of laser beams so as to complement portions having a low energy density with each other, the energy can be reduced more than using a plurality of laser beams alone without overlapping. The region having a uniform density is enlarged, and the crystallinity of the semiconductor film can be efficiently increased.
[0165]
Note that the distribution of energy density in BB 'and CC' is weaker in BB 'than in CC', but can be regarded as almost the same size. 1 / e of peak value of laser beam ² The shape of the combined linear laser light in the region satisfying the energy density of the above may be linear.
[0166]
Note that a region having a low energy density exists near the outer edge of the irradiation region of the combined linear laser beam 30. If the region is used, the crystallinity may be impaired rather than the region. Therefore, it is preferable that the outer edge of the linear laser beam is not used as in the case of using the slit 15 in FIG.
[0167]
The laser irradiation apparatus described in this embodiment can be used when performing laser light irradiation of the present invention, and can be used when performing any of the first to tenth embodiments. In addition, although there is an advantage of obtaining a linear laser beam by synthesis, the cost of an optical system and a laser oscillator increases, so that a single laser oscillator and a set of optical systems generate a desired linear laser beam. As long as it can be obtained, there is no problem in using such a laser irradiation apparatus in the practice of the present invention.
[0168]
Embodiment 12
In this embodiment mode, when forming the second insulating film 303 in Embodiment Mode 3, the glass substrate 301 is used as an etching stopper, and an insulating film (third insulating film) corresponding to the first insulating film 302 is formed on the second insulating film 303. An example in which the insulating film 305 is also used.
[0169]
In FIG. 29A, first, a second insulating film 602 in which a recess is formed in a predetermined shape with silicon oxide or silicon oxynitride is formed over a glass substrate 601. Details are the same as in the third embodiment. The recess may be formed by either wet etching or dry etching. In this embodiment mode, dry etching using CHF 3 gas is used. In this case, the gas flow rate is 30 to 40 sccm, the reaction pressure is 2.7 to 4.0 KPa, the applied power is 500 W, and the substrate temperature is 20 ° C.
[0170]
In this embodiment, as the glass substrate 601, a material having a high selectivity with respect to a silicon oxide film (for example, a 1737 glass substrate manufactured by Corning Incorporated) is preferably used. This is because if the selectivity is high, the glass substrate 601 can be used as it is as an etching stopper when the second insulating film 602 is formed.
[0171]
After the second insulating film 602 is formed, the second insulating film 602 is covered thereon with a first insulating film 603 formed of silicon nitride, silicon oxynitride having a nitrogen content larger than the oxygen content, or a laminate thereof, and further having an amorphous film thereon. The semiconductor layer 604 is formed to obtain the state shown in FIG. For the details of the first insulating film 603 and the amorphous semiconductor film 604, the description in Embodiment Mode 3 can be referred to. Further, the steps after FIG. 29B may be in accordance with the third embodiment, and the description is omitted here.
[0172]
According to the present embodiment, it is possible to ensure a sufficiently high selectivity between the glass substrate 601 and the second insulating film 602, so that the process margin when forming the concave portion of the second insulating film 602 is improved. . In addition, problems such as scuffing at the lower end of the second insulating film 602 do not occur. Further, the portion where the second insulating film 602 is not provided has a structure in which a silicon nitride film, a silicon oxynitride having a nitrogen content larger than the oxygen content or a laminated film thereof are formed on a glass substrate. It is not necessary to use a simple insulating film.
[0173]
Note that this embodiment can be implemented by being freely combined with any of the structures of Embodiments 1 to 11.
[0174]
[Example 1]
In this embodiment, a crystalline semiconductor film obtained by carrying out the present invention will be described. In the present example, the crystallization step was performed according to the second and third embodiments, and thus the example will be described with reference to FIGS.
[0175]
In this embodiment, a 50-nm-thick silicon oxynitride film was used as the first insulating film 302 in FIG. 6, and a 200-nm-thick silicon oxynitride film was used as the second insulating film 303. In this case, when the second insulating film 303 was etched, the underlying first insulating film 302 was also etched. As a result, the height corresponding to the step d in FIG. 1 was 250 nm. Further, the width of the second insulating film 303 (corresponding to W1 in FIG. 1) was 0.5 μm, and the distance between the adjacent layers (corresponding to W2 in FIG. 1) was 0.5 μm.
[0176]
After a silicon oxynitride film with a thickness of 20 nm is provided as a third insulating film 305 over the second insulating film 303, the amorphous semiconductor film 306 is continuously formed without being exposed to the atmosphere to a thickness of 150 nm. Was formed. The amorphous silicon film was crystallized using the crystallization technique of the second embodiment. Specifically, after a heat treatment at 550 ° C. for 4 hours was performed with a 10 ppm nickel acetate aqueous solution held on the amorphous silicon film for crystallization, linear laser light was irradiated. The linear laser light is a continuous oscillation mode YVO. ₄ Using a laser oscillator, the output of the second harmonic (wavelength: 532 nm) of 5.5 W was condensed into linear laser light by an optical system, and scanning was performed at room temperature at a speed of 50 cm / sec.
[0177]
FIG. 26A is a TEM (transmission electron microscope) photograph of the state where the crystalline silicon film 307 is formed (the state shown in FIG. 8), and FIG. 26B is a schematic view thereof. The stacked body of the first insulating film 302 and the second insulating film 303 exists under the crystalline silicon film 307 so as to be completely buried.
[0178]
FIG. 27A is a cross-sectional TEM photograph of the cross section of FIG. 26A, and FIG. 27B is a schematic diagram thereof. A crystalline silicon film 307a is formed so as to be filled between the second insulating films 303 formed by the stripe pattern (concave portions), and a crystal is formed on the upper surface portion (convex portions) of the second insulating film 303. A conductive silicon film 307b is formed.
[0179]
FIG. 28A is an enlarged cross-sectional TEM photograph of the cross section of FIG. 27A, and FIG. 28B is a schematic view thereof. In the photograph, the third insulating film 305 is observed. No crystal grain boundaries or defects seemed to be observed at all inside the crystalline silicon film 307a, indicating that the crystalline silicon film 307a has extremely high crystallinity.
[0180]
The present invention enables high-speed operation and current drive by using a crystalline silicon film 307a having good crystallinity as a channel formation region and using a crystalline silicon film 307b having poor crystallinity as an electrode or wiring. It is possible to provide a thin film transistor having high performance and small variation among a plurality of elements or a semiconductor device formed by integrating the thin film transistor group with a high degree of integration.
【The invention's effect】
As described above, a linear stripe pattern having a concavo-convex shape is formed by an insulating film, an amorphous semiconductor film is deposited thereon, and crystallized in a molten state by irradiation with laser light to form a concave portion. The semiconductor is poured and solidified, and strain or stress due to crystallization can be concentrated in a region other than the concave portion, so that a region with poor crystallinity such as a crystal grain boundary can be selectively formed.
[0181]
Then, a semiconductor element such as a transistor, in particular, a location of a channel formation region thereof is specified to form a crystalline semiconductor film having no crystal grain boundary. As a result, it is possible to eliminate a factor in which the characteristics vary due to careless intervening crystal grain boundaries or crystal defects, and it is possible to form a transistor or a transistor element group having small characteristic variations.
[0182]
As described above, the present invention enables high-speed operation by using a crystalline semiconductor film with good crystallinity as a channel formation region and using a crystalline semiconductor film with poor crystallinity as an electrode or a wiring. It is possible to provide a semiconductor device having a high current driving capability and small variation among a plurality of elements or a semiconductor device configured by integrating the semiconductor element group with a high degree of integration.
[Brief description of the drawings]
FIG. 1 is a perspective view illustrating a crystallization method of the present invention.
FIG. 2 is a perspective view illustrating a crystallization method of the present invention.
FIG. 3 is a perspective view illustrating a crystallization method according to the present invention.
FIG. 4 is a perspective view illustrating a crystallization method of the present invention.
FIG. 5 is a longitudinal sectional view illustrating the relationship between the shape of an opening and the form of a crystalline semiconductor film in crystallization.
6A to 6C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
7A to 7C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
8A to 8C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
9A to 9C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
10A to 10C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
11A to 11C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
12A to 12C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
FIG. 13 is a vertical cross-sectional view illustrating an example of a gate structure that can be used in a transistor of the present invention.
14A to 14C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
15A to 15C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
FIG. 16 is a longitudinal cross-sectional view illustrating a manufacturing process of a transistor of the present invention.
FIG. 17 is a longitudinal sectional view illustrating a manufacturing process of a transistor of the present invention.
18A to 18C are a top view and vertical cross-sectional views illustrating a manufacturing process of a transistor of the present invention.
FIG. 19 illustrates an example of an external view of a semiconductor device of the present invention.
FIG. 20 is a diagram showing a specific example of an electronic device according to the invention.
FIG. 21 is a diagram showing a laser irradiation apparatus used for carrying out the present invention.
FIG. 22 is a diagram showing a configuration of a laser beam used for implementing the present invention.
FIG. 23 is a TEM photograph showing the upper surface of a crystalline silicon film obtained by carrying out the present invention after secco etching, and a schematic diagram thereof.
FIG. 24 is a TEM photograph showing the upper surface of a crystalline silicon film obtained by carrying out the present invention after secco etching, and a schematic diagram thereof.
FIG. 25 is EBSP mapping data showing the orientation of a crystal formed in a concave portion.
FIG. 26 is a TEM photograph of the upper surface of a crystalline silicon film obtained by carrying out the present invention and a schematic diagram thereof.
FIG. 27 is a TEM photograph showing a cross section of a crystalline silicon film obtained by carrying out the present invention and a schematic diagram thereof.
FIG. 28 is a TEM photograph showing a cross section of a crystalline silicon film obtained by carrying out the present invention and a schematic diagram thereof.
FIG 29 is a longitudinal cross-sectional view illustrating a manufacturing process of a transistor of the present invention.

Claims (8)

A first crystalline semiconductor region including a plurality of crystal orientations without substantially having a crystal grain boundary on the insulating surface, wherein the first crystalline semiconductor region has conductivity; A semiconductor element provided in connection with the semiconductor region,
The first crystalline semiconductor region extends in a direction parallel to an insulating film extending in a linear stripe pattern provided on the insulating surface;
The semiconductor device according to claim 1, wherein the second crystalline semiconductor region is provided over an insulating film extending in the linear stripe pattern. A first crystalline semiconductor region including a plurality of crystal orientations without substantially having a crystal grain boundary on the insulating surface, wherein the first crystalline semiconductor region has conductivity; A semiconductor element provided in connection with the semiconductor region,
The first crystalline semiconductor region extends in a direction parallel to an insulating film extending in a linear stripe pattern provided on the insulating surface;
The semiconductor element, wherein the second crystalline semiconductor region is used as a wiring provided over an insulating film extending in the linear stripe pattern. A first crystalline semiconductor region including a plurality of crystal orientations without substantially having a crystal grain boundary on the insulating surface, wherein the first crystalline semiconductor region has conductivity; A semiconductor element provided in connection with the semiconductor region,
The first crystalline semiconductor region extends in a direction parallel to an insulating film extending in a linear stripe pattern provided on the insulating surface;
The second crystalline semiconductor region is provided over an insulating film extending in the linear stripe pattern,
The semiconductor device according to claim 1, wherein the second crystalline semiconductor region includes a portion having a smaller thickness than the first crystalline semiconductor region. A second crystalline semiconductor region having substantially no crystal grain boundaries on the insulating surface and including a plurality of crystal orientations, wherein the first crystalline semiconductor region has conductivity; A semiconductor element provided in connection with the crystalline semiconductor region,
The first crystalline semiconductor region extends in a direction parallel to an insulating film extending in a linear stripe pattern provided on the insulating surface;
The second crystalline semiconductor region is used as a wiring provided over an insulating film extending in the linear stripe pattern,
The semiconductor device according to claim 1, wherein the second crystalline semiconductor region includes a portion having a smaller thickness than the first crystalline semiconductor region. The semiconductor element according to claim 1, wherein the insulating surface is a surface of an insulating film provided on a glass substrate. 6. The insulating film according to claim 1, wherein a width of the insulating film extending in the linear stripe pattern is 0.1 to 10 μm, an interval between adjacent patterns is 0.01 to 2 μm, and A semiconductor element having a thickness of 0.01 to 3 μm. 7. The semiconductor device according to claim 1, wherein a thickness of the first crystalline semiconductor region is equal to a thickness of an insulating film extending in the linear stripe pattern. . A semiconductor device comprising a circuit in which the semiconductor element according to claim 1 is integrated.

Images