JPH09135030A - Semiconductor integrated circuit device, computer system using the device and manufacturing method for the semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing technology for a semiconductor integrated circuit device in which a high speed and a low power are together obtained by using a perfect depletion transistor and a dielectric strength can be guaranteed by using a partial depletion transistor. SOLUTION: A semiconductor integrated circuit device is constituted of a predetermined integrated circuit made on a SOT (silicon on insulator) substrate. By means of separate implantations under different ion implanting conditions, a left MOS transistor is made to a perfect depletion transistor 28 which has depletion in all region because of a dopant density of a channel region being low and a right MOS transistor 29 which has partial depletion in a channel region because of a dopant density of the channel region being high. By the steps the perfect depletion transistor and the partial depletion transistor are formed on the same SOI substrate 10 in the state of having different impurity densities.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology, and in particular, in an LSI manufactured on an SOI (Silicon On Insulator) substrate, a partially depleted transistor and a fully depleted transistor which take advantage of the advantages of the SOI substrate. The present invention relates to a semiconductor integrated circuit device suitable for forming a semiconductor device, a computer system using the same, and a technique effectively applied to a method for manufacturing a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art For example, according to a study conducted by the inventor, in an LSI manufactured on an SOI substrate, a parasitic capacitance between the wiring and the substrate, a diffusion layer capacitance and the like are caused because complete element isolation is possible. Since it can be reduced and the operation speed of the semiconductor integrated circuit device can be improved, it is conceivable that there is a possibility of lower power consumption and higher speed than the bulk LSI.

As a semiconductor integrated circuit technology formed on such an SOI substrate, for example, "IEEE JOURNAL OF SO
LID-STATE CIRCUITS, VOL.29, NO.11, NOVEMBER 1994 P132
3-P1329 ”and the like.

[0004]

In the semiconductor integrated circuit technology formed on the SOI substrate as described above, a fully depleted transistor is required to bring out the performance of the SOI substrate. It is considered that the transistor has a low breakdown voltage. In particular, in the LSI using the SOI substrate, it has been clarified as a result of the study by the present inventor that it is important to secure drain withstand voltage as well as to achieve low power consumption and high speed.

Therefore, an object of the present invention is to form a fully-depleted transistor and a partially-depleted transistor on the same substrate, thereby using a fully-depleted transistor to achieve both high speed and low power, and partial depletion. An object of the present invention is to provide a semiconductor integrated circuit device capable of ensuring a withstand voltage by using a semiconductor transistor, a computer system using the semiconductor integrated circuit device, and a method for manufacturing the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is applied to a semiconductor integrated circuit device in which a predetermined integrated circuit is manufactured on an SOI substrate. Of the integrated circuits, an external interface or a word of a DRAM is used. Circuits that require high breakdown voltage, such as line booster circuits, are configured using partially depleted transistors, and other circuits that require low power and high speed that only apply a reduced voltage use fully depleted transistors. It is composed, especially DRA
The present invention is applied to a semiconductor memory device such as M or SRAM.

Further, the computer system of the present invention has at least a central processing unit and its peripheral circuits in addition to the semiconductor integrated circuit device or the semiconductor memory device.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a predetermined integrated circuit manufactured on an SOI substrate is
Differentiating between circuits that require high breakdown voltage and circuits that require low power consumption and high speed, circuits that require high breakdown voltage are fabricated using partially depleted transistors on the same SOI substrate, and
A circuit that requires high speed is manufactured using a fully depleted transistor.

Specifically, when the partially depleted transistor or the fully depleted transistor is separately formed on the same SOI substrate, different ion implantation conditions are used for different implantation or a process similar to the LOCOS formation process (recess array array). ) Or a process of locally introducing impurities into the buried oxide film of the SOI substrate and then introducing the impurities into the single crystal silicon thin film on the buried oxide film by thermal diffusion. The impurity concentration or the film thickness is made different.

That is, in the partially depleted transistor or the fully depleted transistor, the fully depleted transistor is a transistor that can make the most of the advantage of the SOI substrate, but has the disadvantage of low drain breakdown voltage. Although the performance transistor is inferior in performance as a transistor to the fully depleted transistor, the drain breakdown voltage can be secured.

Therefore, according to the present invention, it is possible to form the fully depleted transistor and the partially depleted transistor on the same SOI substrate, and to completely deplete the circuit to which only the internally reduced voltage is applied. A transistor can be used to achieve both high speed and low power, and a partially depleted transistor can be used to secure the breakdown voltage in a circuit that requires a high breakdown voltage such as an external interface or a word line booster circuit of a DRAM.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic functional block diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a data output circuit according to the first embodiment. 3 to 10 are cross-sectional views showing the manufacturing steps of the MOS transistor according to the first embodiment.

First, a schematic configuration of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIG.

The semiconductor integrated circuit device according to the first embodiment is
For example, it is a semiconductor integrated circuit device in which a predetermined integrated circuit is manufactured on an SOI substrate, and includes an internal circuit 1, an input / output interface 2, a step-down circuit 3, and the like, and the internal circuit 1 to which only the internally stepped down voltage is applied is completely depleted. I / O interface 2
And the step-down circuit 3 of the external power supply, and the high breakdown voltage portion 4 of the internal circuit 1 which requires a high breakdown voltage are configured to include a partially depleted transistor, and these fully depleted transistor and partially depleted transistor are the same SOI substrate. Formed on.

It should be noted that the input / output interface 2 and the step-down circuit 3 can be designed so that the voltage of the external power supply is not applied between the source and drain of the transistor by devising the circuit. The portion that uses is limited to the circuit block of the high breakdown voltage portion 4 that requires a high breakdown voltage of the internal circuit 1, for example, a word line voltage booster circuit in the case of DRAM.

Specifically, the data output circuit in the internal circuit 1 and the input / output interface 2 is of a known capacitor boost type as shown in FIG. 2, for example, and the left half of the figure is the output section 5 of the internal circuit 1. A fully depleted transistor is used for this part to operate with a step-down power supply. The data output signal RD from this internal circuit 1,
/ RD is output by an AND operation through the AND gate together with the activation signal φ of the output stage.

On the other hand, the right half of FIG. 2 is the external output section 6 of the input / output interface 2, and the external power source is used as it is, so that an external high voltage is directly applied between the source and drain of the transistor. Therefore, a high breakdown voltage partially depleted transistor is used. In the external output unit 6, the data output signals from the internal circuit 1 are respectively input to the nMOS transistors, and only the inverter connected in series with the delay circuit τ1 and the capacitor connected in parallel with the capacitor and the delay circuit τ2 are provided. Data signals are output from the connection nodes of these nMOS transistors to the outside.

Next, the operation of the first embodiment will be described with reference to FIGS. 3 to 10 on the manufacturing process of the MOS transistor forming the main part of the semiconductor integrated circuit device.

First, in the element cross-sectional views of the MOS transistors shown in FIGS. 3 to 10, the MOS transistor on the left side is a fully depleted transistor in which the entire region is depleted because the dopant concentration in the channel region is low. On the other hand, the MOS transistor on the right side is a partially depleted transistor in which the channel region is partially depleted because it has a region having a high dopant concentration in the channel region. That is, the two types of transistors are formed on the same SOI substrate by changing the ion implantation conditions.

The method of manufacturing the MOS transistor of the first embodiment will be described below for the n-channel. In addition,
The p-channel can also be formed in the same step by reversing the conductivity type of the dopant, so that it is possible to form a complementary circuit on the same SOI substrate by adding a photo step.

First, for example, a buried oxide film 8 made of SiO ₂ is formed on the upper layer of the silicon single crystal 7, and a single crystal silicon thin film 9 is further formed on the buried oxide film 8.
The surface of the I substrate 10 is oxidized to form an oxide film 11 of SiO ₂ . Then, a silicon nitride film 12 of, for example, Si ₃ N ₄ is deposited on the upper layer of the silicon nitride film 12, and the silicon nitride film 12 covering a portion other than the element region is formed by a photo process.
Is removed (FIG. 3).

After that, thermal oxidation is performed to form, for example, SiO _{2 in} a portion corresponding to the opening of the silicon nitride film 12 in FIG.
An element isolation oxide film 13 made of is formed (FIG. 4). Then, the silicon nitride film 12 is removed by wet etching, the oxide film 11 is further removed, and then an oxide film 14 such as SiO ₂ is formed again by thermal oxidation (FIG. 5).

Then, as shown in FIG. 5, a resist mask 15 is applied to the portion of the element region where the fully depleted transistor is formed, and the high concentration impurity layer 16 is ion-implanted only in the element region where the partially depleted transistor is formed. To form. Specifically, boron, which is a p-type impurity, is implanted so that the peak concentration is about 1 × 10 ¹⁸ cm ⁻³ and the concentration is maximum at the interface between the single crystal silicon thin film 9 and the buried oxide film 8.

Then, the polycrystalline silicon film 17 and the silicon oxide film 18 are deposited by the known CVD method (FIG. 6). Since this polycrystalline silicon film 17 will later become a gate electrode, impurities are introduced together during the deposition, or after the deposition, ion implantation and activation annealing are performed before depositing the silicon oxide film 18. Perform processing.

Further, the silicon oxide film 18 and the polycrystalline silicon film 17 are formed on the gate electrode 1 by a photo process.
9 and 20 shapes are processed as shown in FIG. Then, using the gate electrodes 19 and 20 as a mask, ion implantation of, for example, arsenic, which is an n-type impurity, is performed to form the source / drain 21 (FIG. 7).

Subsequently, the oxide film 22 is deposited by the known CVD method (FIG. 8). When anisotropic dry etching is performed in this state, the sidewall oxide film 23 remains only on the sidewalls of the gate electrodes 19 and 20 as shown in FIG. Then, the gate electrodes 19 and 2
The second source / drain ion implantation is performed using 0 as a mask to form the source / drain 24. The second ion implantation is for reducing the resistance of the source / drain 24.

Finally, an interlayer insulating film 25 made of, for example, SiO ₂ is deposited and the gate electrodes 19 and ₂ are formed.
0, a contact hole is opened toward the source / drain 24, a metal 26 such as aluminum or tungsten is backfilled in the contact hole, and a wiring 27 is formed to complete the semiconductor device (FIG. 10).

As described above, by changing the ion implantation conditions and performing the ion implantation, the MO on the left side in FIG.
Since the S transistor has a low dopant concentration in the channel region, it becomes a fully depleted transistor 28 in which the entire region is depleted. The MOS transistor on the right side has a region having a high dopant concentration in the channel region, and therefore the channel region is partially depleted. Only the depleted transistor 29 is depleted.

Therefore, according to the semiconductor integrated circuit device of the first embodiment, the fully depleted transistor 28 and the partially depleted transistor 29 can be formed on the same SOI substrate 10 with different impurity concentrations. Because you can
A fully depleted transistor 28 that maximizes the advantages of the SOI substrate 10 is used to achieve both high speed and low power, and a drain depletion voltage is ensured by using a partially depleted transistor 29 that compensates for the drawbacks of the fully depleted transistor 28. It can be possible.

Particularly, in the manufacturing method of the first embodiment, since the fully depleted transistor 28 and the partially depleted transistor 29 can be formed by changing the impurity concentration, the number of manufacturing steps is increased in terms of the manufacturing process. It is possible to easily form a semiconductor integrated circuit device by minimizing the above.

This semiconductor integrated circuit device is applied to, for example, a DRAM or an SRAM, and by using the partially depleted transistor 29 in a circuit such as a word line boosting circuit that needs a high breakdown voltage, high speed operation and low power consumption can be achieved. Thus, it is possible to realize a semiconductor memory device capable of ensuring a high breakdown voltage.

(Second Embodiment) FIGS. 11 to 14 show an MO in a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing process of the S transistor.

The semiconductor integrated circuit device according to the second embodiment is
A semiconductor integrated circuit device in which a predetermined integrated circuit is manufactured on an SOI substrate is the same as in the first embodiment. The difference from the first embodiment is that a process (recess array) similar to the LOCOS formation process is used. , A partially depleted transistor and a fully depleted transistor are formed on the same SOI substrate by making the thickness of the portion of the partially depleted transistor formed differently from that of the portion of the fully depleted transistor formed. The point is that the transistor and the transistor are separately formed.

That is, in the semiconductor integrated circuit device of the second embodiment, in the element cross-sectional views of the MOS transistors of FIGS. 11 to 14, the MOS transistor on the left side has a thin channel region, so that the entire region is depleted. It is a fully depleted transistor. On the other hand, M on the right
Since the thickness of the channel region of the OS transistor is large,
The channel region is a partially depleted transistor that is only partially depleted. That is, the two types of transistors are formed on the same SOI substrate by changing the film thickness of the single crystal silicon thin film on the buried oxide film.

Hereinafter, a method of manufacturing the MOS transistor of the second embodiment will be described for the n-channel. Since the p-channel can be formed in the same process by reversing the conductivity type of the dopant, it is also possible to form a complementary circuit on the same SOI substrate by adding a photo process.

First, for example, a buried oxide film 8a made of SiO ₂ is formed on the upper layer of the silicon single crystal 7a, and the surface of the SOI substrate 10a on which the single crystal silicon thin film 9a is further formed is oxidized to form an oxide film. 11a is formed (FIG. 11). Then, a known selective oxidation method is used to provide a difference between the single crystal silicon thin film 9a in the region where the fully depleted transistor is formed and the region where the partially depleted transistor is formed.

That is, the silicon nitride film 12a is deposited on the oxide film 11a, and the silicon nitride film 12a which forms the partially depleted transistor is left by the photo process and etching, and the silicon which is the fully depleted transistor is formed. The nitride film 12a is removed and cleaned.

After that, thermal oxidation is performed to form the silicon oxide film 30 in the portion forming the fully depleted transistor (FIG. 12). At this time, since the single crystal silicon thin film 9a remaining between the silicon oxide film 30 and the buried oxide film 8a becomes the element region of the fully depleted transistor, the oxidizing conditions are set so that the single crystal silicon thin film 9a does not disappear by thermal oxidation. adjust.

Then, the silicon nitride film 12a and the silicon oxide film 30 are removed by wet etching to obtain the SOI substrate 10a having a desired film thickness difference (FIG. 1).
3). After that, as in the first embodiment, the element isolation step, the gate formation step, the source / drain formation step,
The semiconductor device shown in FIG. 14 is completed by the interlayer insulating film forming step and the wiring step.

That is, as shown in FIG. 14, on the SOI substrate 10a, the gate electrodes 19a, 20 made of element isolation oxide film 13a, silicon oxide film and polycrystalline silicon.
a, source / drain 21a, gate electrodes 19a, 20
a side wall oxide film 23a, source / drain 24a, and interlayer insulating film 25a are sequentially formed, and finally the gate electrode 19 is formed.
a, 20a, and the source / drain 24a are filled with metal 26a in the contact holes opened to form wiring 27a.

As described above, by using the same process as the LOCOS forming process, the M on the left side in FIG.
Since the OS transistor has a thin channel region, the entire region is fully depleted.
Since the MOS transistor on the right side has a thick channel region, the channel region becomes a partially depleted transistor 29a that is only partially depleted.

Therefore, according to the semiconductor integrated circuit device of the second embodiment, the fully depleted transistor 28a and the partially depleted transistor 29a can be formed on the same SOI substrate 10a with different film thicknesses. Because you can
As in the first embodiment, the fully depleted transistor 28a that maximizes the advantages of the SOI substrate 10a is used to achieve both high speed and low power, and to supplement the drawbacks of the fully depleted transistor 28a. It is possible to secure the drain breakdown voltage by using.

In particular, in the manufacturing method of the second embodiment, since the fully depleted transistor 28a and the partially depleted transistor 29a can be formed by changing the film thickness, the semiconductor integrated circuit device can be designed in terms of design. Control is easily possible.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments of the present invention, the present invention is not limited to the above embodiments and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range.

For example, in the semiconductor integrated circuit device of the first embodiment, the concentration of boron is maximized at the interface between the single crystal silicon thin film and the buried oxide film, and the impurity concentration is changed by changing the ion implantation conditions. Although different cases have been described, the present invention is not limited to the above-described embodiment, and ion implantation is performed under an energy condition where boron completely enters the buried oxide film, and a subsequent thermal process is performed. As a result, it can be applied to the case where the impurity layer is formed by the impurity diffusion from the buried oxide film.

In this case, a steeper impurity distribution can be formed as compared with the first embodiment, which is also advantageous for adjusting the threshold voltage and suppressing the short channel effect. Further, in terms of manufacturing process and design, although the effect is smaller than that of the first and second embodiments,
The manufacturing process can be simplified and the design can be facilitated.

Further, the present invention is not limited to the case of being used in the unit of storage device such as DRAM or SRAM, but may be, for example, a computer system, a digital still camera system,
It is widely used as a storage device for various systems such as an automobile system. As an example, a computer system will be described with reference to FIG.

In FIG. 15, this computer system includes a bus and a central processing unit CPU, a peripheral device control unit, a DRAM of the present invention as a main memory and its control unit, an SRAM as a backup memory and a backup parity and its control unit. , A ROM storing programs, a display system, and the like.

The peripheral device control section is connected to an external storage device, a keyboard KB and the like. Further, the display system is composed of a video RAM (VRAM) or the like, and is connected to a display as an output device to display V
Information stored in the RAM is displayed. Further, a power supply unit for supplying power to the internal circuit of the computer system is provided.

The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory. Here, an example in which the invention is applied to a DRAM as a main memory has been described, but the display system VRAM is a multiport VRAM.
If so, it is also possible to apply to the random access part of the VRAM.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Since the fully depleted transistor and the partially depleted transistor can be formed on the same SOI substrate, the fully depleted transistor can be used to increase the speed in a circuit to which only the internally reduced voltage is applied. It is possible to achieve both high power consumption and low power consumption and to secure the withstand voltage by using a partially depleted transistor in a circuit that requires a high withstand voltage such as an external interface. It is possible to improve the general circuit performance.

(2). When the partially depleted transistor and the fully depleted transistor are separately formed on the same SOI substrate, the ion implantation conditions are changed so that the impurity concentrations are different, thereby increasing the number of manufacturing steps. It is possible to form the semiconductor integrated circuit device by a simple manufacturing process while minimizing the above.

(3) When the partially depleted transistor and the fully depleted transistor are separately formed on the same SOI substrate, the film thickness is made different by using the same process (recess array) as the LOCOS forming process. Thus, the design control can be facilitated and the semiconductor integrated circuit device can be formed by an easy design.

(4). When the partially depleted transistor and the fully depleted transistor are separately formed on the same SOI substrate, impurities are locally introduced into the buried oxide film of the SOI substrate, and the buried oxide film is then introduced from there. By making the impurity concentration different by using the process of introducing impurities into the above single crystal silicon thin film by thermal diffusion, it becomes possible to simplify the manufacturing process and the design of the semiconductor integrated circuit device. .

(5) By the above (1) to (4), the formation of partially depleted and fully depleted transistors utilizing the advantages of the SOI substrate, and further the effects in the manufacturing process and design are maximized. Semiconductor integrated circuit device, especially D
It is possible to obtain a good manufacturing method for a semiconductor memory device such as a RAM or an SRAM, and to use a low power consumption method using the same.
It is possible to obtain various systems such as a computer system whose functionality can be improved by increasing the speed.

[Brief description of the drawings]

FIG. 1 is a schematic functional block diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a data output circuit in the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the MOS transistor according to the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of a MOS transistor (continued from FIG. 3) in the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the MOS transistor (continued from FIG. 4) in the first embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of a MOS transistor (continued from FIG. 5) in the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of a MOS transistor (continued from FIG. 6) in the first embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the MOS transistor (continued from FIG. 7) in the first embodiment.

FIG. 9 is a cross-sectional view showing a manufacturing step (following FIG. 8) of the MOS transistor in the first embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of a MOS transistor (continued from FIG. 9) in the first embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the MOS transistor in the semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing step (following FIG. 11) of a MOS transistor in the semiconductor integrated circuit device according to the second embodiment.

FIG. 13 is a cross-sectional view showing a manufacturing step (continued from FIG. 12) of a MOS transistor in the semiconductor integrated circuit device according to the second embodiment.

FIG. 14 is a cross-sectional view showing a manufacturing step (following FIG. 13) of a MOS transistor in the semiconductor integrated circuit device of the second embodiment.

FIG. 15 is a functional block diagram showing a computer system using the semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

 1 Internal Circuit 2 Input / Output Interface 3 Step-Down Circuit 4 High Voltage Section 5 Output Section 6 External Output Section 7, 7a Silicon Single Crystal 8, 8a Embedded Oxide Film 9, 9a Single Crystal Silicon Thin Film 10, 10a SOI Substrate 11, 11a Oxide Film 12, 12a Silicon nitride film 13, 13a Element isolation oxide film 14 Oxide film 15 Resist mask 16 High concentration impurity layer 17 Polycrystalline silicon film 18 Silicon oxide film 19, 19a, 20, 20a Gate electrode 21, 21a Source / drain 22 Oxidation Film 23, 23a Side wall oxide film 24, 24a Source / drain 25, 25a Interlayer insulating film 26, 26a Metal 27, 27a Wiring 28, 28a Full depletion transistor 29, 29a Partially depleted transistor 30 Silicon oxide film

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical indication location H01L 27/10 681F 29/78 618D (72) Inventor Yoji Ide 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division

Claims (7)

[Claims] 1. A semiconductor integrated circuit device in which a predetermined integrated circuit is manufactured on an SOI substrate, wherein a circuit requiring a high breakdown voltage is formed by using a partially depleted transistor, A semiconductor integrated circuit device characterized in that a circuit requiring high power and high speed is configured by using a fully depleted transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a DRAM or SR.
A semiconductor integrated circuit device characterized by being a semiconductor memory device such as an AM. 3. A computer system using the semiconductor integrated circuit device according to claim 1, further comprising at least a central processing unit and peripheral circuits thereof in addition to the semiconductor integrated circuit device or the semiconductor memory device. A computer system characterized by the above. 4. A method of manufacturing a semiconductor integrated circuit device for manufacturing a predetermined integrated circuit on an SOI substrate, wherein the integrated circuit is classified into a circuit requiring high breakdown voltage and a circuit requiring low power / high speed. Then, on the same SOI substrate, a circuit requiring the high breakdown voltage is manufactured by using a partially depleted transistor,
A method of manufacturing a semiconductor integrated circuit device, characterized in that the circuit requiring low power consumption and high speed is manufactured by using a fully depleted transistor. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein, when the partially depleted transistor or the fully depleted transistor is manufactured, ion implantation conditions are changed to perform different implantation. The impurity concentration of silicon in a portion forming a depletion transistor and the impurity concentration in a portion forming the fully depleted transistor are made different so that the partially depleted transistor and the fully depleted transistor are formed on the same SOI substrate. A method of manufacturing a semiconductor integrated circuit device, characterized in that a transistor and a transistor are manufactured separately. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the LOCOS is formed when the partially depleted transistor or the fully depleted transistor is manufactured.
By using a process similar to the formation process, the film thickness of silicon in the portion forming the partially depleted transistor and the film thickness of silicon in the portion forming the fully depleted transistor are made different, and the same A method of manufacturing a semiconductor integrated circuit device, wherein the partially depleted transistor and the fully depleted transistor are separately formed on an SOI substrate. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the SOI is formed when the partially depleted transistor or the fully depleted transistor is manufactured.
Using a process of locally introducing an impurity into the buried oxide film of the substrate and then introducing the impurity into the single crystal silicon thin film on the buried oxide film by thermal diffusion, Forming the partially depleted transistor and the fully depleted transistor separately on the same SOI substrate by making the impurity concentration of silicon different from the impurity concentration of silicon in a portion forming the fully depleted transistor. A method for manufacturing a semiconductor integrated circuit device, comprising: