JP2014175373A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To thin a semiconductor layer in an element region of a MOSFET while minimizing an increase in manufacturing process and inhibiting an increase in manufacturing cost.SOLUTION: A semiconductor device comprises: a LOCOS oxide film 9 formed in a semiconductor layer 7 on an insulation layer 5; and a MOSFET 11 formed on the semiconductor layer 7 in an element region 11a surrounded by the LOCOS oxide film 9. A channel region 19 of the MOSFET 11 is formed in a region within th element region 11a, which includes a recess region 7a where a thickness of the semiconductor layer 7 is reduced to a further degree than in the other region within the element region 11a. The recess region 7a is formed by removing the LOCOS oxide film 9 and an oxide film for recess region formation which is formed on a surface side of an SOI layer 7 in the channel region 19 at the same time.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  An SOI (Silicon on Insulator) substrate is known as a substrate on which a semiconductor layer on an insulating layer is formed. In a semiconductor device using an SOI substrate, a fully depleted MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a partially depleted MOSFET are known.

  A case where depletion of the channel region reaches a BOX (buried oxide) layer is called a complete depletion type, and a case where a neutral region remains above the BOX layer without reaching the depletion is called a partial depletion type. Both have different electrical characteristics, but both have the characteristics of SOI devices that have a small parasitic capacitance in the source region and the drain region.

  As far as the channel region is concerned, the partial depletion type shows almost the same characteristics as a general MOSFET, and the full depletion type is easier to lower the threshold than the partial depletion type, and the drain-source voltage (VDS). The withstand voltage is low.

  Both the fully depleted type and the partially depleted type have applications that should be applied, and it is necessary to use them according to the circuit contents. Therefore, a method for creating both fully depleted and partially depleted types on the same substrate has been devised. Yes.

  Fully depleted MOSFETs and partially depleted MOSFETs have their merits and demerits, but the SOI layer thickness to be formed is different. Therefore, in order to take advantage of each advantage, a method is known in which a fully depleted MOSFET and a partially depleted MOSFET are formed on the same substrate (see, for example, Patent Document 1).

  However, the conventional method in which the fully depleted MOSFET and the partially depleted MOSFET are formed on the same SOI substrate has a problem that the manufacturing process of the semiconductor device is greatly increased.

  As a conventional method, for example, oxygen ions are implanted into a predetermined region of an SOI substrate having a film thickness of an SOI layer for forming a partially depleted MOSFET, and a region corresponding to the channel region of the fully depleted MOSFET is embedded. There is a method of thickening only the oxide film thickness.

  In addition, there is a method of locally reducing the SOI layer thickness in the fully depleted MOSFET region with respect to the SOI substrate having the SOI layer thickness for forming the partially depleted MOSFET (see, for example, Patent Document 1). . In Patent Document 1, the surface of the SOI layer is oxidized by LOCOS (local oxidation of silicon), and the LOCOS oxide film is removed to reduce the thickness of the SOI layer in the fully depleted MOSFET region.

  7 and 8 are schematic cross-sectional views for explaining a conventional method for manufacturing a semiconductor device. The parentheses for each step described below correspond to the parentheses in FIGS.

(1) A P-type SOI substrate in which a buried oxide film 102 and an SOI layer 103 are formed in this order on a support substrate 101 is used. The film thickness of the SOI layer 103 is, for example, about 400 nm (nanometers). A buffer oxide film is formed on the SOI layer 103, and a silicon nitride film is further formed thereon by a CVD (chemical vapor deposition) method. The buffer oxide film and the silicon nitride film are patterned to form a buffer oxide film pattern 104 and a silicon nitride film pattern 105 that cover the element region of the partially depleted MOSFET.

(2) The LOCOS oxide film 106 is formed by performing LOCOS oxidation using the buffer oxide film pattern 104 and the silicon nitride film pattern 105 as a mask. The LOCOS oxide film 106 is formed with a thickness that does not reach the buried oxide film 102 by adjusting the oxidation time. The thickness of the LOCOS oxide film 106 is, for example, about 600 nm. The film thickness of the SOI layer 103 under the LOCOS oxide film 106 is, for example, about 100 nm.

(3) The buffer oxide film pattern 104, the silicon nitride film pattern 105, and the LOCOS oxide film 106 are removed. The film thickness of the SOI layer 103 in the element region of the fully depleted MOSFET is thinner than the film thickness of the SOI layer 103 in the element region of the partially depleted MOSFET.

(4) After forming the buffer oxide film, a silicon nitride film is formed by CVD. The buffer oxide film and the silicon nitride film are patterned to form a buffer oxide film pattern 107 and a silicon nitride film pattern 108 that cover the element region of the fully depleted MOSFET and the element region of the partially depleted MOSFET, respectively.

  The LOCOS oxide film 109 is formed by performing LOCOS oxidation using the buffer oxide film pattern 107 and the silicon nitride film pattern 108 as a mask. The LOCOS oxide film 109 is formed with a thickness that reaches the buried oxide film 102.

(5) A resist pattern 110 is formed in order to perform field dose for suppressing parasitic transistors. Boron implantation is performed using the resist pattern 110 as a mask to form a P-type region 111 in the SOI layer 103.

(6) The resist pattern 110, the silicon nitride film pattern 108, and the buffer oxide film 107 are removed. A gate oxide film 112, a gate electrode 113, an LDD (Lightly Doped Drain) region 114 (N−), a sidewall 115, a source region and a drain region 116 are formed along a general MOSFET manufacturing process. Thereby, Nch (Negative Channel) MOSFETs are formed in the element region of the fully depleted MOSFET and the element region of the partially depleted MOSFET, respectively.

  The conventional manufacturing method requires a mask pattern formation process, a LOCOS oxide film formation process, a LOCOS oxide film removal process, and a mask pattern removal process in order to thin the SOI layer (semiconductor layer) in the element region of the fully depleted MOSFET. I was trying. As described above, the conventional manufacturing method requires many steps in order to thin the semiconductor layer in the element region of the MOSFET, which greatly increases the manufacturing process of the semiconductor device, and thus increases the manufacturing cost. there were.

  An object of the present invention is to reduce the thickness of a semiconductor layer in an element region of a MOSFET while suppressing an increase in manufacturing cost without increasing the number of manufacturing steps as much as possible.

  A method for manufacturing a semiconductor device according to the present invention includes a LOCOS oxide film formed in a semiconductor layer on an insulating layer, and a semiconductor device including a MOSFET formed in a semiconductor layer in an element region surrounded by the LOCOS oxide film. A method for forming the LOCOS oxide film by thermal oxidation, wherein the LOCOS oxide film is formed in a region corresponding to the element region and has a recess region forming gap in a region corresponding to the channel region of the MOSFET. And the recess region forming gap is formed in such a dimension that the recess region forming oxide film formed in the recess region forming gap by the thermal oxidation treatment does not reach the insulating layer. Using the film pattern, the thermal oxidation treatment is performed to form the LOCOS oxide film reaching the insulating layer to form the element region. The recessed region forming oxide film that does not reach the insulating layer and the recessed region in which the thickness of the semiconductor layer in the element region is made thinner than other regions are formed under the recessed region forming oxide film. A LOCOS oxide film forming step, a recessed region forming oxide film removing step for removing the recessed region forming oxide film, a gate insulating film step for forming a gate insulating film of the MOSFET on the recessed region, and the gate A gate electrode forming step of forming the gate electrode of the MOSFET on the insulating film in that order.

  The semiconductor device manufacturing method according to the present invention can reduce the semiconductor layer in the element region of the MOSFET while suppressing an increase in manufacturing cost without increasing the number of manufacturing steps as much as possible.

1A and 1B are a schematic plan view and a cross-sectional view for explaining an embodiment of a semiconductor device. It is a schematic sectional drawing for demonstrating one Example of the manufacturing method of a semiconductor device. FIG. 3 is a schematic cross-sectional view for explaining the same embodiment, and is a view for explaining a step subsequent to FIG. 2. It is the schematic top view and sectional drawing for demonstrating the other Example of a semiconductor device. It is a schematic sectional drawing for demonstrating the other Example of the manufacturing method of a semiconductor device. FIG. 6 is a schematic cross-sectional view for explaining the embodiment, and is a diagram for explaining a process subsequent to FIG. 5. It is a schematic sectional view for explaining a conventional method for manufacturing a semiconductor device. FIG. 8 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor device, and is a diagram for explaining a process subsequent to FIG. 7.

  In the method for manufacturing a semiconductor device of the present invention, for example, at least one of the width dimension and the length dimension of the recess region forming gap is 0.6 μm or less.

  In the method for manufacturing a semiconductor device of the present invention, for example, in the oxidation resistant film pattern, a plurality of the recess region forming gaps may be formed in a region corresponding to the channel region.

  In the LOCOS oxide film forming step, for example, the oxidation-resistant film pattern corresponds to a second element region for forming a second MOSFET surrounded by the LOCOS oxide film at a position different from the element region. The LOCOS oxide film, the element region, the recess region forming oxide film, and the recess region are formed at the same time as the thermal oxidation treatment is performed, and the recess region is not included. The second element region may be formed.

  In the gate insulating film forming step, for example, the gate insulating film of the second MOSFET may be formed on the semiconductor layer in the second element region simultaneously with the formation of the gate insulating film.

  In the gate electrode formation step, for example, the gate electrode of the second MOSFET may be formed on the semiconductor layer in the second element region via a gate insulating film simultaneously with the formation of the gate electrode. .

  A semiconductor device according to the present invention includes a LOCOS oxide film formed in a semiconductor layer on an insulating layer, and a MOSFET formed in a semiconductor layer in an element region surrounded by the LOCOS oxide film, At least a part of the channel region of the MOSFET includes a region in which the thickness of the semiconductor layer is thinner than other regions in the element region.

  In the semiconductor device of the present invention, the MOSFET functions as, for example, a fully depleted MOSFET.

  The semiconductor device of the present invention may include, for example, a second MOSFET formed in the semiconductor layer of the second element region surrounded by the LOCOS oxide film at a position different from the element region. Here, the channel region of the second MOSFET is formed in the semiconductor layer not including the thinned region.

  Further, the second MOSFET functions as a partially depleted MOSFET, for example.

  The present invention utilizes the fact that the LOCOS oxide film thickness to be formed is different due to the size of the interval of the oxidation resistant film pattern used as a mask for performing LOCOS oxidation. Originally, when the LOCOS oxide film reaches the buried oxide film (insulating layer), a recess region forming gap is provided in the oxidation resistant film pattern, and the LOCOS oxide film is stopped halfway through the SOI layer in the recess region forming gap. . Accordingly, a recessed region in which the thickness of the semiconductor layer is made thinner than the other regions in the element region is formed corresponding to the position of the recessed region forming gap.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic plan view and cross-sectional view for explaining an embodiment of a semiconductor device. In FIG. 1, the cross-sectional view corresponds to the AA ′ position in the plan view.

  The SOI substrate 1 includes a support substrate 3, a buried oxide film 5 (insulating layer), and an SOI layer 7 (semiconductor layer). A LOCOS oxide film 9 for element isolation is formed on the SOI layer 7.

  Element regions 11a and 13a surrounded by the LOCOS oxide film 9 are formed. A fully depleted MOSFET 11 is formed in the element region 11a. A partial depletion type MOSFET 13 (second MOSFET) is formed in the element region 13a (second element region).

  The fully depleted MOSFET 11 and the partially depleted MOSFET 13 are Nch MOSFETs, for example. These Nch MOSFETs include a pair of N-type source and drain regions 15, 15 (N +), a pair of LDD regions 17, 17 (N-), a P-type channel region 19, a gate insulating film 21, a gate electrode 23, And side walls 25 are provided.

  A pair of source and drain regions 15 and 15 are formed in the SOI layer 7 of the element regions 11a and 13a, respectively, at intervals. A channel region 19 is formed in the SOI layer 7 between the source and drain regions 15 and 15. An LDD region 17 is formed in the SOI layer 7 between the source and drain regions 15 and the channel region 19.

  In the element region 11a of the fully depleted MOSFET 11, the channel region 19 of the fully depleted MOSFET 11 is formed in a region including the recessed region 7a in which the thickness of the SOI layer 7 is made thinner than other regions in the element region 11a. .

  The recessed region 7 a is formed by removing the recessed region forming oxide film formed on the surface side of the SOI layer 7 in the channel region 19 simultaneously with the LOCOS oxide film 9. Therefore, the SOI layer 7 in the element region 11a of the fully depleted MOSFET 11 can be thinned while suppressing an increase in manufacturing cost without increasing the number of manufacturing steps as much as possible.

The channel region 19 of the partially depleted MOSFET 13 is not completely depleted when the fully depleted MOSFET 11 operates.
The channel region 19 of the fully depleted MOSFET 11 is completely depleted during the operation of the fully depleted MOSFET 11 because the SOI layer 7 is thinned by the recessed region 7 a.

  Therefore, in this embodiment, the fully depleted MOSFET 11 and the partially depleted MOSFET 13 can be formed in the same SOI layer 7 while suppressing an increase in manufacturing cost without increasing the number of manufacturing steps as much as possible.

  In this embodiment, in the fully depleted MOSFET 11 and the partially depleted MOSFET 13, the film thickness of the SOI layer 7 in the source region and the drain region 15 is the same. On the other hand, as shown in FIG. 8, for example, in a general fully depleted MOSFET, the resistance value of the source region and the drain region increases due to the decrease in the film thickness of the SOI layer constituting the source region and the drain region. .

  In this embodiment, since the film thickness of the SOI layer 7 in the source region and the drain region 15 is the same in the fully depleted MOSFET 11 and the partially depleted MOSFET 13, the resistance values of the source region and the drain region 15 of the fully depleted MOSFET 11 as in the conventional technique are used. There is no increase.

  The fully depleted MOSFET 11 and the partially depleted MOSFET 13 are Nch MOSFETs. However, if the N type and the P type are interchanged, the same operation and effect can be obtained even when the fully depleted MOSFET and the partially depleted MOSFET are Pch MOSFETs. .

  2 and 3 are schematic cross-sectional views for explaining an embodiment of a method for manufacturing a semiconductor device. This embodiment of the manufacturing method is an example of a manufacturing method example for forming the embodiment of the semiconductor device shown in FIG. 2 and 3 correspond to the A-A ′ position in the plan view of FIG. 1. The parentheses for each step described below correspond to the parentheses in FIGS.

(1) For example, a P-type SOI substrate 1 is used. The SOI substrate 1 includes a support substrate 3, a buried oxide film 5 formed on the support substrate 3, and an SOI layer 7 formed on the buried oxide film 5. The thickness of the buried oxide film 5 is about 300 nm, for example. The film thickness of the SOI layer 7 is, for example, about 400 nm.

  A buffer oxide film is formed on the surface of the SOI layer 7. Furthermore, a silicon nitride film having a thickness of, for example, about 100 nm is formed thereon by CVD. The buffer oxide film and the silicon nitride film are patterned to form a buffer oxide film pattern 27 and a silicon nitride film pattern 29 (an oxidation resistant film pattern).

  Referring also to FIG. 1, the buffer oxide film pattern 27 and the silicon nitride film pattern 29 are formed in regions corresponding to the element region 11 a of the fully depleted MOSFET 11 and the element region 13 a of the partially depleted MOSFET 13.

  In a region corresponding to the element region 11 a of the fully depleted MOSFET 11, the buffer oxide film pattern 27 and the silicon nitride film pattern 29 have a recess region forming gap 29 a in a region corresponding to the channel region 19 of the fully depleted MOSFET 11. Yes. The recess region forming gap 29a is formed in such a size that the recess region forming oxide film 9a formed in the recess region forming gap 29a does not reach the buried oxide film 5 by a thermal oxidation process performed in a later step. Yes.

  For example, the width dimension (dimension in the channel length direction) of the recess area forming gap 29a is 0.6 μm or less. The width dimension of the recess area forming gap 29a is 0.6 μm as long as the recess area forming oxide film 9a formed in the recess area forming gap 29a does not reach the buried oxide film 5. May be larger.

  In a region corresponding to the element region 13a of the partially depleted MOSFET 13, the buffer oxide film pattern 27 and the silicon nitride film pattern 29 cover the region. In this region, the recess region forming gap 29 a is not formed in the buffer oxide film pattern 27 and the silicon nitride film pattern 29.

(2) LOCOS oxidation (thermal oxidation treatment) is performed to form the LOCOS oxide film 9 and the recess region forming oxide film 9a. The LOCOS oxidation is performed, for example, by wet oxidation at 1000 ° C. and about 800 nm in terms of the thickness of the oxide film to be formed. A LOCOS oxide film 9 reaching the buried oxide film 5 is formed, and element regions 11a and 13a (see FIG. 1) are formed.

  Simultaneously with the formation of the LOCOS oxide film 9, a recessed region forming oxide film 9a that does not reach the buried oxide film 5 is formed in the recessed region forming gap 29a. Due to the formation of the recessed region forming oxide film 9a, the recessed region 7a in which the thickness of the SOI layer 7 is made thinner than the other regions in the element region 11a of the fully depleted MOSFET 11 is the recessed region forming oxide film 9a. Formed below.

  In this LOCOS oxidation, it is important that the recessed region forming oxide film 9 a does not reach the buried oxide film 5. The oxidation time is adjusted so that the film thickness of the SOI layer 7 in the recessed region 7a under the recessed region forming oxide film 9a is, for example, about 100 nm.

(3) A resist pattern 31 is formed in order to perform field dose for suppressing parasitic transistors. Using the resist pattern 31 as a mask, boron implantation is performed under the conditions of, for example, 20 keV and 8 × 10 ₁₂ cm ⁻² to form a P-type region 33 in the SOI layer 7.

(4) The resist pattern 31 is removed. The silicon nitride film pattern 29 and the buffer oxide film pattern 27 are removed. A resist pattern 35 having an opening in a region corresponding to the channel region of the fully depleted MOSFET is formed. Oxide film wet etching is performed using resist pattern 35 as a mask to remove recess region forming oxide film 9a.

(5) The resist pattern 35 is removed. A gate insulating film 21, a gate electrode 23, an LDD region 17, a sidewall 25, a source region and a drain region 15 are formed along a general MOSFET manufacturing process. Thereby, a fully depleted MOSFET 11 and a partially depleted MOSFET 13 are formed.

  For example, the gate insulating film 21 made of a silicon oxide film is formed to a thickness of about 15 nm on the surface of the SOI layer 7 including the surface of the recessed region 7a by wet oxidation at 920 ° C. A polysilicon film having a thickness of about 350 nm is formed by LP-CVD (low pressure CVD). The gate electrode 23 is formed by patterning the polysilicon film by photolithography and etching techniques. The polysilicon film is etched by, for example, a dry etching method in which HBr and HCl gas are mixed.

After the formation of the gate electrode 23, phosphorus, which is an N-type impurity, is implanted into the SOI layer 7 under a condition of a dose of, for example, 70 keV and 2.5 × 10 ¹³ cm ⁻² to form the LDD region 17. To do. For example, an HTO (high temperature oxide) film is formed with a film thickness of about 250 nm. Etchback processing is performed on the HTO film to form sidewalls 25.

For example, phosphorus which is an N-type impurity is implanted into the SOI layer 7 under a condition of a dose of 30 keV, 5.8 × 10 ¹⁵ cm ⁻² to form the source region and the drain region 15. At this time, N-type impurities are simultaneously introduced into the polysilicon pattern constituting the gate electrode 23.

Here, the gate insulating film 21 of the fully depleted MOSFET 11 and the gate insulating film of the partially depleted MOSFET 13 are formed simultaneously, but these gate insulating films may be formed separately.
Further, although the gate electrode 23 of the fully depleted MOSFET 11 and the gate electrode 23 of the partially depleted MOSFET 13 are formed at the same time, these gate electrodes may be formed separately.

  If the N-type and P-type are interchanged, a fully depleted MOSFET and a partially depleted MOSFET made of Pch MOSFET can be formed.

  In this way, a recess region forming oxide film removing step (step (4) above) is added to the general process without increasing the number of diffusion steps for adjusting the film thickness of the SOI layer of the fully depleted MOSFET. Only by doing so, the SOI layer 7 in the element region of the MOSFET can be thinned. As a result, the fully depleted MOSFET 11 and the partially depleted MOSFET 13 can be separately formed on the same SOI layer 7 while suppressing an increase in manufacturing cost without increasing the number of manufacturing steps as much as possible.

  FIG. 4 is a schematic plan view and sectional view for explaining another embodiment of the semiconductor device. In FIG. 4, the cross-sectional view corresponds to the B-B ′ position in the plan view. In FIG. 4, parts having the same functions as those in FIG.

  Compared with the fully depleted MOSFET 11 shown in FIG. 1, the fully depleted MOSFET 11 of this embodiment has a longer channel length dimension of the channel region 19 and a length dimension of the recessed region 7a of the SOI layer 7 in the channel direction. Is formed.

  Although not shown in FIG. 4, the partially depleted MOSFET 13 may be formed in the element region 13a at a position different from the element region 11a of the fully depleted MOSFET 11, as in the embodiment shown in FIG.

  5 and 6 are schematic cross-sectional views for explaining another embodiment of the semiconductor device manufacturing method. This embodiment of the manufacturing method is an example of a manufacturing method example for forming the embodiment of the semiconductor device shown in FIG. 5 and 6 correspond to the B-B 'position in the plan view of FIG. The parentheses for each step described below correspond to the parentheses in FIGS.

(1) A buffer oxide film pattern 27 and a silicon nitride film pattern 29 are formed on the SOI layer 7 by a process similar to the process (1) described with reference to FIG. Referring also to FIG. 4, the buffer oxide film pattern 27 and the silicon nitride film pattern 29 have a plurality of recess region forming gaps 29 a in a region corresponding to the channel region 19 of the fully depleted MOSFET 11.

  Each recess region forming gap 29a is formed in such a size that the recess region forming oxide film 9a formed in the recess region forming gap 29a does not reach the buried oxide film 5 by a thermal oxidation process performed in a later step. ing.

  In addition, the buffer oxide film pattern 27 and the silicon nitride film pattern 29 between the adjacent recess region forming gaps 29 a and 29 a are also such that the recess region forming oxide film 9 a formed in the subsequent process does not reach the buried oxide film 5. It is formed with the dimension.

  Further, the size of the buffer oxide film pattern 27 and the silicon nitride film pattern 29 between the adjacent concave region forming gaps 29a and 29a is not formed with irregularities on the bottom surface of the concave region forming oxide film 9a formed in a later step. It is preferable that it is a grade.

  Note that unevenness may be formed on the bottom surface of the recess region forming oxide film 9a due to the buffer oxide film pattern 27 and the silicon nitride film pattern 29 between the adjacent recess region forming gaps 29a, 29a. In this case, unevenness is formed in the recessed region 7 a of the SOI layer 7 due to unevenness on the bottom surface of the recessed region forming oxide film 9 a. It is preferable that the concave and convex portions on the bottom surface of the oxide film 9 a for forming the concave region, and hence the concave region 7 a of the SOI layer 7, are such that a region that is not depleted is not formed in the channel region 19 when the fully depleted MOSFET 11 is operated.

(2) LOCOS oxidation (thermal oxidation treatment) is performed in the same manner as the above-described step (2) described with reference to FIG. 2, and the LOCOS oxide film 9, the recess region forming oxide film 9a, and the SOI layer 7 are formed. A recessed area 7a is formed.

  In this LOCOS oxidation, it is important that the recessed region forming oxide film 9 a does not reach the buried oxide film 5. The oxidation time is adjusted so that the film thickness of the SOI layer 7 in the recessed region 7a under the recessed region forming oxide film 9a is, for example, about 100 nm.

(3) A resist pattern 31 is formed and a P-type region 33 is formed in the SOI layer 7 in the same manner as in the step (3) described with reference to FIG.

(4) In the same manner as in the above step (4) described with reference to FIG. 3, after removing the resist pattern 31, a resist pattern 35 is formed, and the concave region forming oxide film 9a is removed.

(5) In the same manner as in the above step (5) described with reference to FIG. 3, after removing the resist pattern 35, the gate insulating film 21, gate electrode 23, LDD region 17, sidewall 25, source region and drain Region 15 is formed. Thereby, a fully depleted MOSFET 11 is formed.

  If the N-type and P-type are interchanged, a fully depleted MOSFET made of Pch MOSFET can be formed.

  Similarly to the embodiment described with reference to FIGS. 2 and 3, this embodiment also includes a step of removing the recessed region forming oxide film (the above step (4)) with respect to a general process. The SOI layer 7 in the element region of the MOSFET can be thinned.

  Further, in this embodiment, the channel length of the fully depleted MOSFET 11 can be increased as compared with the embodiment described with reference to FIGS.

  In this embodiment, the process of forming the fully depleted MOSFET 11 has been described. However, as in the embodiment described with reference to FIGS. 2 and 3, a part of the fully depleted MOSFET 11 is not located in the element region. The depletion type MOSFET 13 may be formed at the same time.

  As mentioned above, although the Example of this invention was described, the dimension, material, arrangement | positioning, shape, etc. which were shown by the said Example are examples, and this invention is not limited to the said Example. The present invention can be variously modified within the scope of the present invention described in the claims.

  For example, although P-type silicon is used as the SOI layer 7 in the above embodiment, the present invention is not limited to this. In the present invention, the semiconductor layer may be N-type silicon, non-doped, or a semiconductor layer other than silicon.

  In the above embodiment of the manufacturing method, the recess region forming gap 29a is formed in a rectangle having a longitudinal direction in the channel width direction. However, in the manufacturing method of the present invention, the shape of the recess region forming gap is It is not limited to. For example, the recess region forming gap may be a rectangle having a longitudinal direction in the channel length direction, or may have a shape other than a rectangle.

  In the above embodiment, a silicon oxide film is used as the gate insulating film 21, but the present invention is not limited to this. In the present invention, the gate insulating film may be made of another material such as a silicon oxide film, a silicon nitride film, or a laminated film of silicon oxide films called an ONO film.

  Although the SOI substrate 1 is used in the above embodiment, the configuration of the semiconductor layer on the insulating layer in the present invention is not limited to this. In the present invention, the configuration of the semiconductor layer on the insulating layer may be other configurations such as a semiconductor layer formed on a sapphire substrate.

  In the above embodiment, polysilicon is used as the material of the gate electrode 23, but the present invention is not limited to this. In the present invention, the material of the gate electrode may be amorphous silicon. Even when amorphous silicon is used as the material of the gate electrode, the same operation and effect as when polysilicon is used can be obtained.

5 buried oxide film (insulating layer)
7 SOI layer (semiconductor layer)
7a Recessed area (thinned area)
9 LOCOS oxide film 9a Recess region forming oxide film 11 Fully depleted MOSFET (MOSFET)
11a Element region 13 Partially depleted MOSFET (second MOSFET)
13a Element region (second element region)
19 Channel region 21 Gate insulating film 23 Gate electrode 29 Oxidation resistant film pattern 29a Clearance region forming gap

JP 2002-118263 A

Claims (10)

In a method of manufacturing a semiconductor device comprising a LOCOS oxide film formed in a semiconductor layer on an insulating layer and a MOSFET formed in a semiconductor layer in an element region surrounded by the LOCOS oxide film,
A step of forming the LOCOS oxide film by thermal oxidation, wherein the LOCOS oxide film is formed in a region corresponding to the element region, has a recess region forming gap in a region corresponding to the channel region of the MOSFET, and the recess region; The formation gap is formed by using an oxidation-resistant film pattern formed in such a size that the recessed region forming oxide film formed in the recessed region forming gap by the thermal oxidation treatment does not reach the insulating layer. Performing the thermal oxidation process to form the LOCOS oxide film reaching the insulating layer to form the element region, and simultaneously forming the recess region forming oxide film not reaching the insulating layer; and A LOCOS oxide film forming step of forming a recessed region in which the thickness of the semiconductor layer is made thinner than other regions in the element region under the recessed region forming oxide film;
A recess region forming oxide film removing step of removing the recess region forming oxide film;
Forming a gate insulating film of the MOSFET on the recessed region; and
And a gate electrode formation step of forming a gate electrode of the MOSFET on the gate insulating film in that order.   2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the width dimension and the length dimension of the recess region forming gap is 0.6 μm or less.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the recess region forming gaps are formed in a region corresponding to the channel region in the oxidation resistant film pattern.   In the LOCOS oxide film forming step, the oxidation-resistant film pattern is also formed in a region corresponding to the second element region for forming the second MOSFET surrounded by the LOCOS oxide film at a position different from the element region. The second element that is formed and that does not include the recess region at the same time as the thermal oxidation treatment is performed to form the LOCOS oxide film, the element region, the recess region forming oxide film, and the recess region. The method for manufacturing a semiconductor device according to claim 1, wherein the region is formed.   5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step of forming the gate insulating film, the gate insulating film of the second MOSFET is formed on the semiconductor layer in the second element region simultaneously with the formation of the gate insulating film.   6. The semiconductor device according to claim 5, wherein in the gate electrode forming step, the gate electrode of the second MOSFET is formed on the semiconductor layer in the second element region via a gate insulating film simultaneously with the formation of the gate electrode. Production method. In a semiconductor device comprising a LOCOS oxide film formed in a semiconductor layer on an insulating layer, and a MOSFET formed in a semiconductor layer in an element region surrounded by the LOCOS oxide film,
At least a part of the channel region of the MOSFET includes a region in which the thickness of the semiconductor layer is thinner than other regions in the element region.   The semiconductor device according to claim 7, wherein the MOSFET functions as a fully depleted MOSFET. A second MOSFET formed in the semiconductor layer of the second element region surrounded by the LOCOS oxide film at a position different from the element region;
9. The semiconductor device according to claim 7, wherein a channel region of the second MOSFET is formed in the semiconductor layer that does not include the thinned region.   The semiconductor device according to claim 9, wherein the second MOSFET functions as a partially depleted MOSFET.

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