JP3934537B2 - Semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device having a display portion. In particular, the present invention relates to a semiconductor device in which a thin film transistor is formed over a substrate having an insulating surface.
[0002]
[Prior art]
In recent years, the development of semiconductor devices, particularly electronic devices having a semiconductor display portion, has been remarkable, and there are various applications such as portable devices such as game machines, notebook computers, mobile phones, liquid crystal televisions, liquid crystal displays, EL displays, etc. is there. The semiconductor display unit is characterized in that it can be made lighter and thinner than conventional CRTs and consumes less power.
[0003]
As a conventional semiconductor display portion, a passive matrix semiconductor display portion having a pixel region in which striped electrodes are formed so as to intersect each other above and below a liquid crystal layer or a light emitting layer, and a thin film transistor (TFT) in a matrix An active matrix type semiconductor display portion having pixel regions arranged in a shape is known.
[0004]
In recent years, a technology for forming a TFT on a substrate has advanced, and application development of an active matrix semiconductor display unit has been advanced. In particular, a TFT using a polysilicon film has a higher field effect mobility (also called mobility) than a TFT using a conventional amorphous silicon film, and conventionally controls a pixel that has been performed by a drive circuit outside the substrate. It can be performed with a driver circuit formed over the same substrate as the pixel.
[0005]
Next, the configuration of an electronic apparatus having a conventional semiconductor display unit will be described. FIG. 21 is a simplified block diagram of a portion related to image display.
[0006]
In FIG. 21, a semiconductor device 301 is a device that captures or creates image data, processes the image data, converts the format, and displays an image. As the semiconductor device 301, for example, a game machine, a video camera, a car navigation, a personal computer, or the like can be considered.
[0007]
In the semiconductor device 301, the semiconductor display portion 302 including the pixel region 319, the scan line driver circuit 318, and the signal line driver circuit 317 is integrally formed over a substrate having an insulating surface. It is formed on a different silicon substrate and mounted as an IC chip. Some of the circuit blocks may be formed on the same silicon substrate.
[0008]
The semiconductor device 301 includes an input terminal 311, a first control circuit 312, a second control circuit 313, a CPU 314, a first memory 315, a second memory 316, and a semiconductor display unit 302. From the input terminal 311, data serving as a basis of image data is input according to each electronic device. For example, it is input data from an antenna in a broadcast receiver, and input data from a CCD in a video camera. It may be input data from a DV tape or a memory card. Data input from the input terminal 311 is converted into an image signal by the first control circuit 312. The first control circuit 312 performs image signal processing such as decoding processing of image data compressed and encoded in accordance with the MPEG standard, tape format, etc., image interpolation and resizing. The image signal output from the first control circuit 312 and the image signal created or processed by the CPU 314 are input to the second control circuit 313 and converted into a format suitable for the semiconductor display unit 302 (for example, a scanning format). Is done. The second control circuit 313 outputs a format-converted image signal and control signal.
[0009]
The CPU 314 efficiently controls signal processing in the first control circuit 312, the second control circuit 313, and other interface circuits. Also, image data is created or processed. The first memory 315 includes a memory area for storing image data output from the first control circuit 312 and image data output from the second control circuit 313, a work memory area for control by the CPU, and a CPU. Is used as a work memory area when creating image data. As the first memory 315, a DRAM or an SRAM is used. The second memory 316 is a memory area for storing color data and character data, which is required when image data is created or processed by the CPU 314, and is configured by a mask ROM or EPROM.
[0010]
The semiconductor display unit 302 includes a signal line driver circuit 317, a scanning line driver circuit 318, and a pixel region 319. The signal line driver circuit 317 receives image signals and control signals (clock signal, start pulse, etc.) from the second control circuit 313, and the scanning line driver circuit 318 receives control signals (clock signal, start pulse, etc.) from the second control circuit 313. ) And display an image in the pixel region 319.
[0011]
Note that the electronic device having the semiconductor display portion can have various structures other than the structure shown in FIG. As the simplest configuration, a configuration including a semiconductor display unit, input / output terminals, and a simple control circuit can be considered. For example, a liquid crystal display or an EL display can be considered. Further, as in the case of a high-performance game machine, when the burden on the CPU is too large in the architecture shown in FIG. 21, there may be a configuration in which a new processor for image processing is provided to reduce the load on the CPU.
[0012]
[Problems to be solved by the invention]
In the electronic apparatus having the conventional semiconductor display unit described above, circuit blocks other than the drive circuit are formed and mounted on a substrate different from the substrate on which the pixels are formed.
[0013]
With the spread of portable electronic devices, downsizing of electronic devices has become an important issue, but semiconductor devices with such a configuration must mount a large number of IC chips separately from the substrate on which pixels are formed. Because it becomes necessary, it is difficult to realize downsizing. In particular, even if the circuit block in the IC chip can be made small, it is difficult to reduce the size of the entire device because of a large margin for mounting. On the other hand, if an attempt is made to reduce the mounting margin in order to reduce the size of the device, advanced mounting technology is required, which causes problems in terms of cost and reliability in the mounting portion.
There is also a problem of wiring capacity. That is, when mounting with an IC chip, there is a problem that it is difficult to perform high-speed operation because the load of wiring increases.
[0014]
As one method for solving such a problem, it is expected that a circuit block is integrally formed with a semiconductor display portion.
[0015]
However, when a circuit block is formed on a substrate having an insulating surface, operation speed is often a problem. This is because a TFT formed over a substrate having an insulating surface such as a glass substrate has poor mobility and threshold characteristics as compared with a transistor formed over a single crystal silicon substrate.
[0016]
As a result, when a conventional semiconductor device is operated at a certain frequency, it operates in a semiconductor device in which a circuit block is mounted with an IC chip, but does not operate in a semiconductor device in which the circuit block is manufactured on a substrate having an insulating surface. Can happen.
[0017]
The present invention has been made in view of such problems. It is an object of the present invention to provide an electronic device having a semiconductor display portion that can be miniaturized, reduces defects due to mounting of a substrate such as an IC chip, and realizes high-speed operation.
[0018]
[Means for Solving the Problems]
In the present invention, in order to solve the above problems, a semiconductor display portion and other circuit blocks are integrally formed on a substrate having an insulating surface.
[0019]
Further, in order to reduce the problem of operation speed when a circuit block is formed over a substrate having an insulating surface, a TFT manufacturing process that realizes high mobility is used.
[0020]
The TFT fabrication process that realizes high mobility is the process of forming an active layer in which a semiconductor film is irradiated with an energy beam to form a melt zone, and the melt zone is continuously scanned in the channel direction for crystallization. Is used. Although details will be described in the embodiment, specifically, this is performed using a continuous wave laser.
[0021]
The circuit block constituted by the TFT thus manufactured has a higher mobility of individual TFTs than a circuit block using conventional polysilicon as an active layer of the TFT, so that the operating frequency is greatly improved.
[0022]
As a result, the display portion and other circuit blocks can be integrally formed on a substrate having an insulating surface, and high-speed operation can be realized. That is, a circuit block that could not be put into practical use even if formed on a substrate having an insulating surface due to the problem of operating speed can be put into practical use according to the present invention.
[0023]
Furthermore, in the present invention, the throughput is improved as follows while maintaining such a high operating frequency.
[0024]
For continuous wave lasers, YVO _Four Lasers, YLF lasers, YAG lasers, and the like are known, but the current output is as low as about 10 W even if it is high. Therefore, in order to perform crystallization by irradiating the active layer with continuous wave laser light, it is necessary to significantly narrow down the laser light, and the beam width is about 50 to 500 μm (typically 200 μm).
[0025]
For example, when a laser beam having a width of 200 μm is scanned over the entire surface of a 600 mm × 720 mm glass substrate at a scanning speed of 50 cm / sec, it takes 72 minutes per sheet. Actually, more time is required for changing or accelerating the scanning direction of the laser beam. In short, we face the problem of low throughput.
[0026]
The present invention is characterized in that the crystallization process using a continuous wave laser is selectively performed only on circuit blocks that require high-speed operation. This greatly improves the throughput of the crystallization process using a continuous wave laser.
[0027]
For example, by suppressing the region irradiated with continuous wave laser light to 50% or less (preferably 30% or less) of the substrate area, the time required for the crystallization process by the continuous wave laser is approximately 50% (preferably 30% or less). Can be reduced.
[0028]
Further, in order to suppress the moving distance of the continuous wave laser beam or the substrate, it is preferable to arrange circuit blocks that require high-speed operation as close to each other as possible. By doing so, the throughput of the crystallization process with a continuous wave laser is further improved.
[0029]
Furthermore, in order to improve the operating frequency of the circuit block, it is preferable to match the TFT channel length direction with the laser beam scanning direction. In the crystallization process of a semiconductor film using a continuous wave laser, the highest mobility is obtained when the channel direction of the TFT and the scanning direction of the laser beam with respect to the substrate are substantially parallel (preferably −30 ° to 30 °). Is obtained. The TFT thus manufactured has an active layer composed of a polycrystalline semiconductor in which crystal grains extend in the channel direction. This also means that the crystal grain boundary is formed substantially along the channel direction, so that the electrical characteristics of the active layer are different between the channel direction and the direction perpendicular thereto. That is, the active layer has electrical anisotropy in the channel direction.
[0030]
Note that a semiconductor active layer included in a circuit block or a pixel region that is not subjected to a crystallization process by a continuous wave laser may be manufactured by a known manufacturing method.
[0031]
In particular, it is preferable to apply a crystallization process having a higher throughput than a crystallization process using a continuous wave laser.
[0032]
In particular, the semiconductor film crystallization method (thermal crystallization using a metal catalyst) disclosed in JP-A-7-183540 is preferred. In this case, a combination process of thermal crystallization using a metal catalyst and crystallization using a continuous wave laser is performed in a region where the semiconductor film is crystallized using a continuous wave laser. In this process, a TFT having a mobility equal to or higher than that in the case where only crystallization by a continuous wave laser is performed is manufactured.
[0033]
Further, a laser crystallization method using a pulsed laser may be used for the semiconductor active layer in a region where the crystallization process using the continuous wave laser is not performed. Since a pulsed laser can realize a high output, it can irradiate a beam having a width of 100 mm or more and has a high throughput. The practitioner may carry out a combination of known methods for producing an active layer including these freely in terms of operating frequency and cost. In contrast to a crystallization process using a continuous wave laser, a TFT manufactured by such a known manufacturing method has no electrical anisotropy in the channel direction, or even if it has a crystallization process using a continuous wave laser. The active layer has a weaker electrical anisotropy.
[0034]
As described above, in the present invention, the pixel region and the circuit block are formed on the same substrate, and the crystallization process by the continuous wave laser is selectively performed only on the circuit block that requires high-speed operation. It is possible to provide a semiconductor device that realizes reduction of defects due to mounting of a substrate such as an IC chip, high operating frequency, and high throughput. Also, a high operating speed can be realized from the viewpoint of wiring capacity.
[0035]
Note that the semiconductor device in the present invention refers to all devices that function by utilizing semiconductor characteristics. For example, a semiconductor display device typified by a liquid crystal display device or a light-emitting device, or an electronic device having a semiconductor display portion. Included in that category. Note that a semiconductor display portion refers to a display portion in which an electrode or a thin film transistor is formed over a substrate having an insulating surface. For example, a liquid crystal display portion, a light-emitting display portion, a passive matrix display portion, or an active matrix display portion. Part in its category. In a case where it is obvious, the semiconductor display unit is also simply referred to as a display unit.
[0036]
In addition, the circuit block referred to in the present invention refers to a block of an electric circuit having a function of characteristics constituted by circuit elements such as a transistor, a capacitor element, and a resistor element. For example, a signal line driver circuit, a scanning line driver circuit, Registers, decoders, counters, frequency dividers, memories, CPUs, DSPs are included in the category. In particular, in this specification, since a circuit block is formed over a substrate having an insulating surface, a thin film transistor (hereinafter referred to as TFT) is a main component of the circuit block. Note that a thin film transistor (TFT) refers to the entire transistor formed using SOI technology.
[0037]
The configuration of the present invention is shown below.
[0038]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by crystallizing a semiconductor film by heat treatment,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0039]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by adding a metal element to a semiconductor film and crystallizing it by heat treatment,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0040]
The energy beam may be a continuous wave laser beam.
[0041]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by irradiating a semiconductor film with a pulsed energy beam and crystallizing,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0042]
The energy beam may be a pulsed laser beam.
[0043]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; One active layer is formed of a polycrystalline semiconductor whose crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grain shape has no anisotropy in the channel direction,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0044]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; One active layer is formed of a polycrystalline semiconductor whose crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose shape anisotropy in the channel direction of crystal grains is weaker than that of the first active layer,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0045]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction;
The second active layer is formed of a polycrystalline semiconductor having no electrical anisotropy in a channel direction;
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0046]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction;
The second active layer is formed of a polycrystalline semiconductor whose electrical anisotropy in the channel direction is weaker than that of the first active layer,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0047]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor in which crystal grains extend in a channel direction, a grain diameter in a minor axis direction is 0.5 to 100 μm, and a grain diameter in a major axis direction is 3 to 10,000 μm;
The second active layer is formed of a polycrystalline semiconductor having a grain size of 0.01 μm to 10 μm,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0048]
The driving frequency of the scanning line driving circuit is 1 kHz to 1 MHz,
The drive frequency of the signal line driver circuit is preferably 100 kHz to 100 MHz.
[0049]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by crystallizing a semiconductor film by heat treatment,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0050]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by adding a metal element to a semiconductor film and crystallizing it by heat treatment,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0051]
The energy beam may be a continuous wave laser beam.
[0052]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; The first active layer is formed by irradiating a semiconductor film with an energy beam to form a melt zone, and continuously scanning the melt zone in the channel length direction to crystallize the second active layer. It is formed by irradiating a semiconductor film with a pulsed energy beam and crystallizing,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0053]
The energy beam may be a pulsed laser beam.
[0054]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; One active layer is formed of a polycrystalline semiconductor whose crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose crystal grain shape has no anisotropy in the channel direction,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0055]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; One active layer is formed of a polycrystalline semiconductor whose crystal grains extend in the channel direction,
The second active layer is formed of a polycrystalline semiconductor whose shape anisotropy in the channel direction of crystal grains is weaker than that of the first active layer,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0056]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction;
The second active layer is formed of a polycrystalline semiconductor having no electrical anisotropy in a channel direction;
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0057]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor having electrical anisotropy in the channel direction;
The second active layer is formed of a polycrystalline semiconductor whose electrical anisotropy in the channel direction is weaker than that of the first active layer,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0058]
According to the present invention,
A pixel region, a scanning line driver circuit, and a signal line driver circuit provided on the same substrate, the first TFT having a first active layer, and the second TFT having a second active layer; 1 active layer is formed of a polycrystalline semiconductor in which crystal grains extend in a channel direction, a grain diameter in a minor axis direction is 0.5 to 100 μm, and a grain diameter in a major axis direction is 3 to 10,000 μm;
The second active layer is formed of a polycrystalline semiconductor having a grain size of 0.01 μm to 10 μm,
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
A semiconductor device is provided in which the signal line driver circuit is configured by the first TFT.
[0059]
The driving frequency of the scanning line driving circuit is 10 kHz to 1 MHz,
The drive frequency of the signal line driver circuit is preferably 100 kHz to 100 MHz.
[0060]
In the semiconductor device, a memory is provided on the same substrate as the pixel region,
The memory may be composed of the first TFT.
[0061]
The memory may be an SRAM, and a read cycle time of the SRAM may be 200 nsec or less.
[0062]
The memory may be a DRAM, and a read cycle time of the DRAM may be 1 μsec or less.
[0063]
In the semiconductor device, a CPU is provided on the same substrate as the pixel region,
The CPU may be composed of the first TFT.
[0064]
The operating frequency of the CPU is preferably 5 MHz or more.
[0065]
In the semiconductor device, an image processing circuit is provided on the same substrate as the pixel region,
The image processing circuit may be composed of the first TFT.
[0066]
The operating frequency of the image processing circuit is preferably 5 MHz or more.
[0067]
In the semiconductor device, a DSP is provided on the same substrate as the pixel region,
The DSP may be composed of the first TFT.
[0068]
The operating frequency of the image processing circuit is preferably 5 MHz or more.
[0069]
In the semiconductor device, a timing generation circuit is provided on the same substrate as the pixel region,
The timing generation circuit may be composed of the first TFT.
[0070]
The substrate having an insulating surface may be any one of a plastic substrate, a glass substrate, and a quartz substrate.
[0071]
The area of the circuit constituted by the first TFT is preferably 50% or less of the area of the substrate.
[0072]
The circuit configured by the first TFT is configured in 1 to 10 rectangular regions,
The area of the entire rectangular region is preferably 50% or less of the area of the substrate.
[0073]
The semiconductor device may be a liquid crystal display device.
[0074]
The semiconductor device may be a light emitting device.
[0075]
The semiconductor device may be one selected from a game machine, a video camera, a head-mounted display, a DVD player, a personal computer, a mobile phone, and a car audio.
[0076]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
As a typical form of a semiconductor device having a display portion of the present invention, an active matrix semiconductor display device will be described as an example.
[0077]
FIG. 2 is a configuration diagram when the active matrix semiconductor display device of the present invention is viewed from above. In FIG. 2, the active matrix semiconductor display device includes a pixel region 202 formed on a substrate 201, a scanning line driver circuit 204, a signal line driver circuit 203, a wiring 205, and an FPC 206.
[0078]
The operation of the active matrix semiconductor display device will be briefly described.
[0079]
The signal line driver circuit 203 receives an image signal, a clock signal, and a start pulse, and the scanning line driver circuit 204 receives the clock signal and the start pulse from the outside via the FPC 206, and displays an image in the pixel region 202.
[0080]
The pixel region is arranged so that a plurality of signal lines and a plurality of scanning lines intersect, and pixel TFTs are arranged at respective intersections between the signal lines and the scanning lines. A scanning line is connected to the gate electrode of the pixel TFT, a signal line is connected to one of the source electrode or the drain electrode, and a liquid crystal element is connected to the remaining one of the source electrode or the drain electrode.
[0081]
A display operation in each pixel will be described. When the scanning line is selected, the pixel TFT connected to the selected scanning line is turned on. In the meantime, when data is input to the signal line connected to the pixel TFT, the potential of the signal line is applied to the liquid crystal element, and the liquid crystal element changes the light transmittance according to the applied voltage. In this way, the luminance in each pixel is determined and displayed.
[0082]
One image is formed by sequentially selecting all the scanning lines. Further, during a period in which each scanning line is selected, data is input to all signal lines sequentially or simultaneously, and image data is input to the selected row. A period during which one image is displayed is called one frame, and is preferably 60 frames or more per second.
[0083]
According to the operation method described above, when the number of pixels is determined, the approximate drive frequency required for the drive circuit is determined. For example, in the color VGA standard, since the number of pixels is 640 × 480 × RGB, assuming that the operation is performed at 60 frames / second, the period for selecting one scanning line is approximately Tg = 1/60/480 sec = 35 μsec. . Further, assuming that image data is captured by RGB × 1 pixel per clock, one clock must be about Td = Tg / 640 sec = 54 nsec. Note that the time for inputting data to the pixel is about a period (Tg = 35 μsec) for selecting one scanning line in line sequential driving.
[0084]
The actual operating frequency depends on the number of divisions of the image data, the frame frequency, the blanking period, etc., but the pixel and scanning line driving circuit operate at a frequency of 1 to 100 kHz, and the signal line driving circuit is 0.1 It is required to operate at a frequency of ˜100 MHz.
[0085]
Here, the case of a liquid crystal display device has been described. In a display device having a light emitting layer typified by an EL layer, the driving method is slightly different, but one image is formed by sequentially selecting all the scanning lines, and each scanning line is selected. A method is common in which data is input sequentially or simultaneously to all signal lines during a period, and image data is input to a selected row. Therefore, the same concept can be applied to the drive frequency.
[0086]
In the first embodiment, a case where a high mobility TFT manufacturing process is applied to a region including the signal line driver circuit 203 that requires high-speed operation based on consideration of such an operating frequency will be described. That is, in FIG. 2, a semiconductor film crystallization method using a continuous wave laser is applied only to the first region 207. In addition, what is necessary is just to use a well-known active layer formation technique about the area | region except a 1st area | region.
[0087]
In FIG. 2, the first region 207 can be 30% or less (preferably 10% or less) of the substrate 201, and the time required for the continuous wave laser process is the continuous wave laser process for the entire substrate. As compared with the case of performing the above, it is possible to make it about 30% or less (preferably 10% or less).
[0088]
In Embodiment Mode 1, an active matrix semiconductor display device that achieves high-speed operation of the entire device is realized by using a high mobility TFT manufacturing process in the first region 207 including the signal line driver circuit that is rate limiting. is doing. In addition, high throughput is achieved despite the use of a crystallization process using a continuous wave laser.
[0089]
Note that in Embodiment Mode 1, a process for manufacturing a high-mobility TFT is applied to a region including a signal line driver circuit. Needless to say, the process may be applied to a region including a scan line driver circuit and includes a pixel. It may be applied to a region. In particular, even when a process for manufacturing a TFT with high mobility is applied to a region including all TFTs, it is preferable because throughput is improved as compared with the case of applying to a whole substrate.
[0090]
(Embodiment 2)
As a typical form of a semiconductor device having a display portion of the present invention, a semiconductor device having a display portion will be described as an example.
[0091]
FIG. 1 is a configuration diagram when a semiconductor device having a display portion of the present invention is viewed from above. In FIG. 1, a semiconductor device having a display portion includes a semiconductor display portion 102 formed over a substrate 101, a first control circuit 112, a second control circuit 113, a CPU 114, a first memory 115, and a second memory. 116 and an input / output terminal 111. The semiconductor display unit 102 includes a pixel region 119, a signal line driver circuit 117, and a scanning line driver circuit 118.
[0092]
The semiconductor device shown in FIG. 1 is an apparatus that captures or creates image data, processes the image data, converts the format, and displays the image. The block configuration is the same as the block diagram shown in FIG. 21, and the operation and function are the same as those described with reference to FIG.
[0093]
Although the operating frequency of each circuit block depends on individual semiconductor devices, it cannot be generally stated, but other circuit blocks usually operate in synchronization with the operating frequency of the CPU. Therefore, it is preferable to improve the operating frequency of each circuit block connected to the CPU 114 and the bus.
[0094]
Therefore, in the second embodiment, the first control circuit 112, the second control circuit 113, the first memory 115, the second memory 116, and the signal line driver circuit 117 connected to the CPU 114 and the bus have high mobility. A TFT manufacturing process is applied. That is, in FIG. 1, the semiconductor active layer crystallization method using the continuous wave laser is applied only to the first region 103. In addition, what is necessary is just to use a well-known active layer formation technique about the area | region except a 1st area | region.
[0095]
In FIG. 1, the first region 103 can be 50% or less (preferably 30% or less) of the substrate, and the time required for the continuous wave laser process is the same as the continuous wave laser process for the entire substrate. Compared to the case where it is performed, it can be made approximately 50% or less (preferably 30% or less).
[0096]
In addition, it is preferable that a region to which crystallization of the semiconductor active layer using a continuous wave laser is applied is localized as much as possible from the viewpoint of throughput. In the configuration shown in FIG. 1, the signal line driver circuit and the scanning line driver circuit can be interchanged, but the signal line driver circuit that requires high-speed operation is connected to the CPU 114 and the bus. 112, the second control circuit 113, the first memory 115, and the second memory 116 are arranged close to each other to localize the first region on the substrate.
[0097]
By arranging in this way, it is not necessary to move the irradiation position of the continuous wave laser light over the entire surface of the substrate, compared with the case where the continuous wave laser is irradiated to a plurality of regions scattered on the substrate with the same area, The time required for crystallization can be shortened.
[0098]
Thus, it is preferable that the irradiation position of the continuous wave laser beam is localized on the substrate. In addition, the movement of the continuous wave laser beam or the substrate is preferably simple, and the irradiation region of the continuous wave laser beam is preferably rectangular. That is, it is preferable that the irradiation region of the continuous wave laser beam is several (preferably 1 to 10) regions represented by a rectangle.
[0099]
In the second embodiment, a semiconductor device that achieves high-speed operation of the entire device is realized by using a high mobility TFT manufacturing process in the first region 103 including the system including the CPU 114 that requires high-speed operation. In addition, by reducing the proportion of the first region in the substrate, high throughput was achieved despite the use of a crystallization process using a continuous wave laser.
[0100]
Note that in Embodiment Mode 2, a high mobility TFT is provided in a region including the CPU 114, the first control circuit 112, the second control circuit 113, the first memory 115, the second memory 116, and the signal line driver circuit 117. However, depending on the circuit block configuration, the characteristics required for the TFT differ even when operating at the same frequency.
[0101]
For example, in particular, when TFTs constituting the CPU 114, the first control circuit 112, and the first memory 115 are required to have particularly high characteristics, a process for manufacturing a TFT with high mobility is applied only to a region including them. It is also effective to do.
[0102]
Even in such a case, it is preferable to devise an arrangement method of the CPU 114, the first control circuit 112, and the first memory 115 so that the crystallization time of the active layer by the continuous wave laser is shortened. Such an example is shown in FIG.
[0103]
Needless to say, a process for manufacturing a high mobility TFT may be applied not only to the first region but also to a region including a scan line driver circuit or a region including pixels. In particular, even when a process for manufacturing a TFT with high mobility is applied to a region including all TFTs, it is preferable because throughput increases as compared with the case of applying to a whole substrate.
[0104]
In this embodiment, the circuit blocks are roughly divided into CPUs and memories, but the present invention is not limited to this. As the circuit block, a smaller circuit configuration such as a register or a frequency dividing circuit may be handled. Then, application of a crystallization process using a continuous wave laser may be selected for such a small block.
[0105]
Further, when a crystallization process using a continuous wave laser is applied to a large circuit block such as a CPU or a memory, it is not necessarily applied to the entire surface. It is also possible to selectively apply only to a region having a relatively high operating frequency within the circuit block.
[0106]
Examples of the present invention are shown below.
[0107]
【Example】
[Example 1]
In this embodiment, a method for irradiating an arbitrary region on a substrate with laser light will be described with reference to FIGS.
[0108]
FIG. 6 shows an outline of an apparatus for forming a linear beam and irradiating the substrate.
[0109]
Laser light emitted from the laser 601 enters the convex lens 603 via the mirror 602. Here, the laser 601 may be a continuous wave or pulsed solid laser, a gas laser, or a metal laser. In this embodiment, a continuous wave YAG laser is used. The laser light oscillated from the laser 601 may be converted into a harmonic by a nonlinear optical element. In addition, a beam expander may be installed between the laser 601 and the mirror 602 or between the mirror 602 and the convex lens 603 so as to be enlarged to a desired size in both the long direction and the short direction. The beam expander is particularly effective when the shape of the laser light emitted from the laser is small. Further, the mirror may not be installed or a plurality of mirrors may be installed.
[0110]
The laser light is incident on the convex lens 603 at an angle. By doing so, the focal position is shifted due to aberrations such as astigmatism, and the linear beam 606 can be formed at or near the irradiated surface. Note that it is desirable that the convex lens 603 is made of synthetic quartz glass because high transmittance can be obtained. Further, it is desirable that the convex lens is an aspheric lens in which spherical aberration is corrected. If an aspheric lens is used, the light condensing property is improved, and the aspect ratio and energy density distribution are improved.
[0111]
Here, “linear” does not mean “line” in a strict sense, but means a rectangle or an ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 to 10,000). Note that the linear shape is used to secure an energy density for sufficient annealing of the irradiated object. Note that the linear beam need not be strictly linear.
[0112]
Then, while irradiating the linear beam 606 formed in this way, for example, the object 604 is moved in the direction indicated by 607 or the direction indicated by 608 with respect to the object to be irradiated 604. The entire region or the entire surface can be irradiated.
[0113]
Then, while irradiating the linear beam formed in this manner, for example, the object 604 moves in a direction indicated by 607 or a direction indicated by 608 to move the object 604 in a desired manner. The area can be irradiated. FIG. 20 shows a state when the laser is irradiated on the substrate. An arrow drawn on the laser irradiation area 609 represents the locus of the irradiation laser.
[0114]
The optical system for generating the laser may be another known one.
[Example 2]
In this embodiment, a method for crystallizing a semiconductor film using a continuous wave laser used in a manufacturing process of a high mobility TFT in a semiconductor device of the present invention will be described.
[0115]
A silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) 400 nm was formed as a base film on a glass substrate by a plasma CVD method. Subsequently, an amorphous silicon film having a thickness of 150 nm was formed as a semiconductor film on the base film by a plasma CVD method. Then, heat treatment was performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film, and then the semiconductor film was crystallized by laser annealing.
[0116]
The laser used in the laser annealing method is a continuous wave YVO. _Four A laser was used. The conditions of the laser annealing method are YVO as laser light. _Four The second harmonic of the laser (wavelength 532 nm) was used. The semiconductor film formed on the substrate surface was irradiated with laser light as a beam having a predetermined shape by an optical system.
[0117]
Further, as the optical system used when irradiating the semiconductor film formed on the substrate surface with laser light, the optical system described in Example 1 (see FIG. 6) was used.
[0118]
In this embodiment, an elliptical beam of 200 μm × 50 μm is formed with an incident angle φ of laser light to the convex lens of about 20 °, and the glass substrate 105 is irradiated while moving at a speed of 50 cm / s, thereby crystallizing the semiconductor film. Made.
[0119]
The relative scanning direction of the elliptical beam was a direction perpendicular to the major axis of the elliptical beam.
[0120]
FIG. 7 shows the result of Secco-etching the thus obtained crystalline semiconductor film and observing the surface by SEM at 10,000 times. The Seco solution in Seco Etching is HF: H ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ It is produced using. FIG. 7 is obtained by relatively scanning laser light in the direction indicated by the arrow in the figure. It can be seen that large crystal grains are formed parallel to the scanning direction of the laser beam. That is, crystal growth is performed so as to extend in the scanning direction of the laser beam.
[0121]
As described above, large-sized crystal grains are formed in the semiconductor film crystallized using the method of this embodiment. Therefore, when a TFT is manufactured using the semiconductor film as a semiconductor active layer, the number of crystal grain boundaries included in the channel formation region of the TFT can be reduced. In addition, since the inside of each crystal grain has crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor using a single crystal semiconductor can be obtained.
[0122]
Furthermore, if the TFT is arranged so that the carrier moving direction is aligned with the direction in which the formed crystal grains extend, the number of times the carriers cross the crystal grain boundary can be extremely reduced. Therefore, variations in on-current value (drain current value that flows when the TFT is on), off-current value (drain current value that flows when the TFT is off), threshold voltage, S value, and field effect mobility Can be reduced, and the electrical characteristics are remarkably improved.
[0123]
Note that in order to irradiate the elliptical beam 606 over a wide area of the semiconductor film, the operation of irradiating the semiconductor film by scanning the elliptical beam 606 in a direction perpendicular to the major axis (hereinafter referred to as scanning) is performed in a plurality of ways. I'm going to go. Here, for each scan, the position of the elliptical beam 606 is shifted in a direction parallel to the major axis. In addition, the scanning direction is reversed between consecutive scans. Here, in two consecutive scans, one is called a forward scan, and the other is called a backward scan.
[0124]
The size of shifting the position of the elliptical beam 606 in the direction parallel to the major axis for each scan is expressed as a pitch d. In the forward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains having a large grain size as shown in FIG. 7 are formed is denoted as D1. In the backward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains having a large grain size as shown in FIG. 7 are formed is denoted as D2. Also, let D be the average value of D1 and D2.
[0125]
At this time, the overlap rate R _OL [%] Is defined by equation (1).
[0126]
R _OL = (1-d / D) × 100 Formula (1)
[0127]
In this embodiment, the overlap rate R _OL Was 0%.
[0128]
[Example 3]
In this embodiment, an example different from that in Embodiment 2 is shown as a method for crystallizing a semiconductor film using a continuous wave laser used in a manufacturing process of a high mobility TFT in the semiconductor device of the present invention.
[0129]
The steps until the amorphous silicon film is formed as the semiconductor film are the same as those in the second embodiment. Thereafter, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (concentration in weight of 5 ppm, volume 10 ml) is applied onto the semiconductor film by spin coating, and in a nitrogen atmosphere at 500 ° C. Heat treatment was performed for 12 hours in a nitrogen atmosphere at 550 ° C. for 1 hour. Subsequently, the crystallinity of the semiconductor film was improved by laser annealing.
[0130]
As a laser used in the laser annealing method, a continuous wave YVO is used. _Four A laser was used. The conditions of the laser annealing method are YVO as laser light. _Four Using the second harmonic of the laser (wavelength 532 nm), an elliptical beam of 200 μm × 50 μm was formed with an incident angle φ of the laser light to the convex lens 103 in the optical system shown in FIG. While moving the glass substrate 105 at a speed of 50 cm / s, the elliptical beam was irradiated to improve the crystallinity of the semiconductor film.
[0131]
The relative scanning direction of the elliptical beam 606 was set to a direction perpendicular to the major axis of the elliptical beam 606.
[0132]
The crystalline semiconductor film thus obtained was subjected to seco etching, and the surface was observed with a SEM at a magnification of 10,000 times. The result is shown in FIG. FIG. 8 is obtained by relatively scanning the laser beam in the direction indicated by the arrow in the figure, and it shows that large crystal grains are formed extending in the scanning direction. Recognize.
[0133]
As described above, since a large crystal grain is formed in the semiconductor film crystallized using the present invention, when a TFT is manufactured using the semiconductor film, a crystal included in the channel formation region is formed. The number of grain boundaries can be reduced. Further, since individual crystal grains have crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor including a single crystal semiconductor can be obtained.
[0134]
Furthermore, the formed crystal grains are aligned in one direction. Therefore, if the TFT is arranged so that the carrier moving direction is aligned with the extending direction of the formed crystal grains, the number of times the carriers cross the crystal grain boundary can be extremely reduced. Therefore, it is possible to reduce variations in the on-current value, off-current value, threshold voltage, S value, and field effect mobility, and the electrical characteristics are remarkably improved.
[0135]
Note that in order to irradiate the elliptical beam 606 over a wide area of the semiconductor film, the operation (scanning) of irradiating the semiconductor film by scanning the elliptical beam 606 in a direction perpendicular to the major axis is performed a plurality of times. Here, for each scan, the position of the elliptical beam 606 is shifted in a direction parallel to the major axis. In addition, the scanning direction is reversed between consecutive scans. Here, in two consecutive scans, one is called a forward scan, and the other is called a backward scan.
[0136]
The size of shifting the position of the elliptical beam 606 in the direction parallel to the major axis for each scan is expressed as a pitch d. In the forward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains having a large grain size as shown in FIG. 8 are formed is denoted as D1. In the backward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 606 in the region where the crystal grains having a large grain size as shown in FIG. 8 are formed is denoted as D2. Also, let D be the average value of D1 and D2.
[0137]
At this time, similar to the equation (1), the overlap rate R _OL Define [%]. In this embodiment, the overlap rate R _OL Was 0%.
[0138]
In addition, the results of Raman scattering spectroscopy of the semiconductor film obtained by the above crystallization technique (indicated as Improved CG-Silicon in the figure) are shown by thick lines in FIG. Here, for comparison, the results of Raman scattering spectroscopy of single crystal silicon (shown as ref. (100) Si Wafer in the figure) are shown by thin lines. In addition, after forming an amorphous silicon film, heat treatment is performed to release hydrogen contained in the semiconductor film, followed by crystallization using a pulsed excimer laser (indicated as excimer laser annealing in the figure). The results of Raman scattering spectroscopy of) are shown by dotted lines in FIG.
[0139]
The Raman shift of the semiconductor film obtained by the method of this example is 517.3 cm. ^-1 It has a peak. The half width is 4.96 cm. ^-1 It is. On the other hand, the Raman shift of single crystal silicon is 520.7 cm. ^-1 It has a peak. The half width is 4.44 cm. ^-1 It is. The Raman shift of the semiconductor film crystallized using a pulsed excimer laser is 516.3 cm. ^-1 It is. The half width is 6.16 cm. ^-1 It is.
[0140]
According to the result of FIG. 9, the crystallinity of the semiconductor film obtained by the crystallization method shown in this example is higher than that of the semiconductor film crystallized using a pulsed excimer laser. It can be seen that it is close to silicon.
[0141]
[Example 4]
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method shown in Embodiment 2 will be described with reference to FIGS.
[0142]
In this embodiment, a glass substrate is used as the substrate 20, and a silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) 50 nm and a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) 100 nm were stacked. Next, an amorphous silicon film 150 nm was formed as a semiconductor film 22 on the base film 21 by a plasma CVD method. Then, a heat treatment was performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film. (Fig. 10 (A))
[0143]
After that, continuous wave YVO as laser light _Four Using the second harmonic of the laser (wavelength 532 nm, 5.5 W), an elliptical beam of 200 μm × 50 μm was formed with an incident angle φ of the laser beam with respect to the convex lens 603 in the optical system shown in FIG. The semiconductor film 22 was irradiated with the elliptical beam relatively scanned at a speed of 50 cm / s. (Fig. 10 (B))
[0144]
Then, a first doping process is performed. This is channel doping for controlling the threshold value. B as material gas ₂ H ₆ , Gas flow rate 30 sccm, current density 0.05 μA, acceleration voltage 60 keV, dose amount 1 × 10 ¹⁴ / Cm ² Went as. (Fig. 10 (C))
[0145]
Subsequently, patterning is performed to etch the semiconductor film 24 into a desired shape, and then a silicon oxynitride film having a thickness of 115 nm is formed by a plasma CVD method as the gate insulating film 27 covering the etched semiconductor film. Next, a TaN film 28 with a thickness of 30 nm and a W film 29 with a thickness of 370 nm are stacked on the gate insulating film 27 as conductive films. (Figure 10 (D))
[0146]
A mask (not shown) made of resist is formed by photolithography, and the W film, TaN film, and gate insulating film are etched.
[0147]
Then, the resist mask is removed, a new mask 33 is formed, and a second doping process is performed to introduce an impurity element imparting n-type into the semiconductor film. In this case, the conductive layers 30 and 31 serve as a mask for the impurity element imparting n-type, and the impurity region 34 is formed in a self-aligning manner. In this embodiment, the second doping process is performed under two conditions because the thickness of the semiconductor film is as thick as 150 nm. In this embodiment, phosphine (PH _Three ) And a dose amount of 2 × 10 ¹³ / Cm ² And the acceleration voltage is 90 keV, and the dose is 5 × 10 5 ¹⁴ / Cm ² The acceleration voltage was 10 keV. (Fig. 10 (E))
[0148]
Next, after removing the resist mask 33, a new resist mask 35 is formed and a third doping process is performed. By the third doping treatment, an impurity region 36 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor film that becomes the active layer of the p-channel TFT. Using the conductive layers 30 and 31 as a mask for the impurity element, an impurity element imparting p-type is added to form the impurity region 36 in a self-aligning manner. In this embodiment, the third doping process is also performed under two conditions because the semiconductor film is as thick as 150 nm. In this embodiment, diborane (B ₂ H ₆ ) And a dose amount of 2 × 10 ¹³ / Cm ² And the acceleration voltage is 90 keV, and the dose is 1 × 10 ¹⁵ / Cm ² The acceleration voltage was 10 keV. (Fig. 10 (F))
[0149]
Through the above steps, impurity regions 34 and 36 are formed in the respective semiconductor layers.
[0150]
Next, the resist mask 35 is removed, and a 50-nm-thick silicon oxynitride film (composition ratio Si = 32.8%, O = 63.7%, N) is formed as the first interlayer insulating film 37 by plasma CVD. = 3.5%).
[0151]
Next, the crystallinity of the semiconductor layers is restored and the impurity elements added to the respective semiconductor layers are activated by heat treatment. In this example, heat treatment was performed at 550 ° C. for 4 hours in a nitrogen atmosphere by a thermal annealing method using a furnace annealing furnace. (Fig. 10 (G))
[0152]
Next, a second interlayer insulating film 38 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 37. In this example, a silicon nitride film having a thickness of 50 nm was formed by a CVD method, and then a silicon oxide film having a thickness of 400 nm was formed.
[0153]
And if it heat-processes, a hydrogenation process can be performed. In this example, heat treatment was performed in a nitrogen atmosphere at 410 ° C. for 1 hour using a furnace annealing furnace.
[0154]
Subsequently, wirings 39 that are electrically connected to the respective impurity regions are formed. In this example, a stacked film of a Ti film with a thickness of 50 nm, an Al—Si film with a thickness of 500 nm, and a Ti film with a thickness of 50 nm was formed by patterning. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti. For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed. (Fig. 10 (H))
[0155]
As described above, an n-channel TFT 51 and a p-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm were formed.
[0156]
The results of measuring these electrical characteristics are shown in FIG. The electrical characteristics of the n-channel TFT 51 are shown in FIG. 11A, and the electrical characteristics of the p-channel TFT 52 are shown in FIG. 11B. The measurement conditions of the electrical characteristics were set to two measurement points, a gate voltage Vg = −16 to 16V, and a drain voltage Vd = 1V and 5V. In FIG. 11, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by a dotted line.
[0157]
Since the semiconductor film crystallized by the above-described method has large crystal grains, when the TFT is manufactured using the semiconductor film, the number of crystal grain boundaries included in the channel formation region is reduced. Can be reduced. Furthermore, since the formed crystal grains are aligned in one direction, the number of times the carriers cross the crystal grain boundary can be extremely reduced by making the TFT channel direction and the laser beam scanning direction substantially parallel. . Therefore, a TFT having good electrical characteristics can be obtained as shown in FIG. In particular, the mobility is 524 cm in an n-channel TFT. ² / Vs, 205cm for p-channel TFT ² It turns out that it becomes / Vs.
[0158]
The method for activating a semiconductor film using a continuous wave laser shown in this embodiment can be applied to a TFT constituting a circuit block that requires high-speed operation in the present invention.
In particular, by making the channel direction of the TFT and the scanning direction of the laser beam substantially parallel (within 30 °), it is possible to realize a circuit block having substantially the same operating characteristics as when formed on a single crystal silicon substrate. .
[0159]
[Example 5]
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method shown in Embodiment 3 will be described with reference to FIGS. 6, 12 to 14, and 15.
[0160]
The steps until the amorphous silicon film is formed as the semiconductor film are the same as those in the fourth embodiment. The amorphous silicon film was formed with a thickness of 150 nm. (Fig. 12 (A))
[0161]
Thereafter, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (weight-concentration concentration 5 ppm, volume 10 ml) is applied onto the semiconductor film by spin coating to form the metal-containing layer 41. To do. Then, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Thus, the semiconductor film 42 was obtained. (Fig. 12 (B))
[0162]
Subsequently, the crystallinity of the semiconductor film 42 is improved by laser annealing.
[0163]
The conditions of the laser annealing method are as follows: _Four Using the second harmonic of the laser (wavelength 532 nm, 5.5 W), an elliptical beam of 200 μm × 50 μm was formed with an incident angle φ of the laser beam with respect to the convex lens 603 in the optical system shown in FIG. The crystallinity of the semiconductor film 42 was improved by irradiating the elliptical beam while moving the substrate at a speed of 20 cm / s or 50 cm / s. In this way, a semiconductor film 43 was obtained. (Figure 12 (C))
[0164]
The steps after the crystallization of the semiconductor film in FIG. 12C are the same as the steps in FIGS. 10C to 10H described in the fifth embodiment. Thus, an n-channel TFT 51 and a p-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm were formed. These electrical characteristics were measured.
[0165]
The electrical characteristics of the TFT manufactured by the above process are shown in FIGS.
[0166]
13A and 13B show electrical characteristics of TFTs manufactured by moving the substrate at a speed of 20 cm / s in the laser annealing step of FIG. 12C. FIG. 13A shows electrical characteristics of the n-channel TFT 51. FIG. 13B shows electrical characteristics of the p-channel TFT 52. 14A and 14B show electrical characteristics of TFTs manufactured by moving the substrate at 50 cm / s in the laser annealing step of FIG. 12C. FIG. 14A shows electrical characteristics of the n-channel TFT 51. FIG. 14B shows electrical characteristics of the p-channel TFT 52.
[0167]
The electrical characteristics were measured under the conditions where the gate voltage Vg = −16 to 16V and the drain voltage Vd = 1V and 5V. In FIGS. 13 and 14, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by a dotted line.
[0168]
Since the crystallized semiconductor film shown in this embodiment has crystal grains having a large grain size, when a TFT is manufactured using the semiconductor film, a crystal grain boundary included in the channel formation region is formed. The number can be reduced. Furthermore, since the formed crystal grains are aligned in one direction and there are few grain boundaries formed in the direction intersecting the relative scanning direction of the laser beam, the number of times the carriers cross the crystal grain boundary is extremely small. Can be reduced.
[0169]
Therefore, a TFT having good electrical characteristics can be obtained as shown in FIGS. In particular, the mobility is 510 cm in the n-channel TFT in FIG. ² / Vs, 200cm for p-channel TFT ² / Vs, and 595 cm in the n-channel TFT in FIG. ² / Vs, 199 cm for p-channel TFT ² It can be seen that / Vs is very excellent. If a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.
[0170]
FIG. 15 shows the electrical characteristics of TFTs manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. FIG. 15A shows the electrical characteristics of the n-channel TFT 51. FIG. 15B shows electrical characteristics of the p-channel TFT 52.
[0171]
The electrical characteristics were measured under the conditions where the gate voltage Vg = −16 to 16V and the drain voltage Vd = 0.1V and 5V.
[0172]
As shown in FIG. 15, a TFT having good electrical characteristics can be obtained. In particular, the mobility is 657 cm in the n-channel TFT shown in FIG. ² / Vs, 219 cm in the p-channel TFT shown in FIG. ² It can be seen that / Vs is very excellent. If a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.
[0173]
The method for activating a semiconductor film using a continuous wave laser shown in this embodiment can be applied to a TFT constituting a circuit block that requires high-speed operation in the present invention.
In particular, by making the channel direction of the TFT and the scanning direction of the laser beam substantially parallel (within 30 °), it is possible to realize a circuit block having substantially the same operating characteristics as when formed on a single crystal silicon substrate. .
[0174]
[Example 6]
In this embodiment, a manufacturing process of a semiconductor device in which a plurality of circuits and an active matrix liquid crystal display portion are formed over the same substrate will be described with reference to FIGS.
[0175]
The cross-sectional views shown in FIGS. 3 and 4 include a first region, a second region, and a third region.
The first region is a circuit block (for example, CPU, signal line driver circuit, etc.) that particularly requires high-speed operation, and is a region in which a semiconductor film crystallization method using a continuous wave laser is performed in the present invention. The second area indicates other circuit blocks (for example, a scanning line driver circuit), and the third area indicates a pixel area.
[0176]
3 and 4, N-channel TFTs and P-channel TFTs are represented as circuit blocks, N-channel TFTs (pixel TFTs) and storage capacitors are represented as pixel areas.
[0177]
As the substrate 5000, a quartz substrate, a silicon substrate, a metal, a substrate, or a stainless steel substrate with an insulating film formed thereon is used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process may be used. In this embodiment, a substrate 5000 made of glass such as barium borosilicate glass or alumino borosilicate glass was used.
[0178]
Next, a base film 5001 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 5000. Although the base film 5001 in this embodiment is formed with a two-layer structure, a single-layer structure of the insulating film or a structure in which two or more insulating films are stacked may be used.
[0179]
In this embodiment, as the first layer of the base film 5001, a plasma CVD method is used to form SiH. _Four , NH _Three And N ₂ A silicon nitride oxide film 5001a formed using O as a reactive gas is formed to a thickness of 10 to 200 [nm] (preferably 50 to 100 [nm]). In this embodiment, the silicon nitride oxide film 5001a is formed to a thickness of 50 [nm]. Next, as a second layer of the base film 5001, a plasma CVD method is used to form SiH. _Four And N ₂ A silicon oxynitride film 5001b formed using O as a reaction gas is formed to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). In this embodiment, the silicon oxynitride film 5001b is formed to a thickness of 100 [nm].
[0180]
Subsequently, semiconductor layers 5002 to 5006, 6002, and 6003 are formed over the base film 5001. The semiconductor layers 5002 to 5005, 6002, and 6003 are formed into a semiconductor film with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]) by a known means (sputtering method, LPCVD method, plasma CVD method, etc.). Film. Note that as the semiconductor film, an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film, or the like may be used.
[0181]
Next, first crystallization is performed on the second region and the third region, or the semiconductor film over the entire substrate. As the first crystallization method, a known crystallization method (laser crystallization method, thermal crystallization method using an RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, or the like) is used. Can do.
[0182]
In this embodiment, an amorphous silicon film having a film thickness of 55 [nm] is formed by plasma CVD. Then, as a first crystallization method, a solution containing nickel is held on the amorphous silicon film, the amorphous silicon film is dehydrogenated (500 [° C.], 1 hour), and then heated. Crystallization (550 [° C.], 4 hours) was performed to form a first crystalline silicon film.
[0183]
Note that in the case of manufacturing the first crystalline semiconductor film by a laser crystallization method, only the second region and the third region may be selectively performed, or a crystal may be formed on the semiconductor film over the entire substrate. May also be performed. As the laser, a pulsed gas laser or solid-state laser may be used. As the former gas laser, excimer laser, YAG laser, YVO _Four Laser, YLF laser, YAlO _Three A laser, a glass laser, a ruby laser, a Ti: sapphire laser, or the like can be used. The latter solid-state laser includes YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm. _Four , YLF, YAlO _Three A laser using a crystal such as can be used. The fundamental wave of the laser differs depending on the material to be doped, and a laser beam having a fundamental wave around 1 [μm] can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.
[0184]
Crystallization conditions are set as appropriate, but when an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 700 [mJ / cm. ² ] (Typically 200-300 [mJ / cm ² ]) When a YAG laser is used, the second harmonic is used to set a pulse oscillation frequency of 1 to 300 [Hz] and a laser energy density of 300 to 1000 [mJ / cm. ² ] (Typically 350-500 [mJ / cm ² ]) Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm] (preferably a width of 400 [μm]) is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time is irradiated. May be set as 50 to 98 [%].
[0185]
Next, second crystallization is performed on the semiconductor film in the first region. In the second crystallization method, crystallization using a continuous wave laser is performed. As a crystallization method using a continuous wave laser, the methods shown in Examples 2 and 3 can be used. Thus, second crystalline silicon is obtained.
[0186]
By such a crystallization process of the semiconductor film, the first crystalline silicon film is formed in the first region including the circuit logic required to operate at high speed, and the second crystalline silicon film is formed in the other region. , Each formed.
[0187]
Since the first crystalline silicon film extends in the relative scanning direction of the laser beam and has large crystal grains, a TFT having the first crystalline silicon film as an active layer is formed. , Have high electrical characteristics.
In particular, when the channel direction is formed substantially parallel to the relative scanning direction of the laser beam, the number of carriers crossing the crystal grain boundary can be extremely reduced, so that the channel direction is formed on single crystal silicon. It is also possible to achieve the same electrical characteristics as a transistor.
[0188]
On the other hand, since the continuous wave laser has a narrow beam width (50 to 500 μm), it is disadvantageous from the viewpoint of throughput to apply this crystallization process to a wide region. In the present invention, throughput is improved by limiting crystallization using a continuous wave laser to a limited region on the substrate.
[0189]
Next, semiconductor layers 5002 to 5005, 6002 and 6003 were formed by patterning using a photolithography method.
[0190]
In this embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 [nm] is formed on the crystalline silicon film and subjected to heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.), and the amorphous silicon film The metal element is diffused therein, and the amorphous silicon film is removed by etching after heat treatment. As a result, the content of the metal element in the first crystalline silicon film can be reduced or removed.
[0191]
Note that after forming the semiconductor layers 5002 to 5005, 6002, and 6003, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0192]
Next, a gate insulating film 5006 is formed to cover the semiconductor layers 5002 to 5005, 6002, and 6003. The gate insulating film 5006 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film having a thickness of 110 [nm] is formed as the gate insulating film 5006 by a plasma CVD method. Needless to say, the gate insulating film 5006 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0193]
Note that in the case where a silicon oxide film is used as the gate insulating film 5006, TEOS (Tetraethyl Orthosilicate) and O ₂ And a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], a high frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm]. ² ] May be formed by discharging. The silicon oxide film manufactured by the above process can obtain favorable characteristics as the gate insulating film 5006 by subsequent thermal annealing at 400 to 500 [° C.].
[0194]
Next, a first conductive film 5007 with a thickness of 20 to 100 [nm] and a second conductive film 5008 with a thickness of 100 to 400 [n] m are stacked over the gate insulating film 5006. In this example, a first conductive film 5007 made of a TaN film with a thickness of 30 [nm] and a second conductive film 5008 made of a W film with a thickness of 370 [nm] were stacked.
[0195]
In this embodiment, the TaN film which is the first conductive film 5007 is formed by a sputtering method, and is formed by a sputtering method in an atmosphere containing nitrogen using a Ta target. The W film as the second conductive film 5008 was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It is also possible to form it by a thermal CVD method using).
[0196]
Note that in this embodiment, the first conductive film 5007 is a TaN film, and the second conductive film 5008 is a W film; however, materials for forming the first conductive film 5007 and the second conductive film 5008 are not particularly limited. . The first conductive film 5007 and the second conductive film 5008 are an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. It may be formed. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used.
[0197]
Next, a resist mask 5009 is formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. (Fig. 3 (B))
[0198]
In this embodiment, ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio is 25:25:10 [sccm], and 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1.0 [Pa]. The plasma was generated to perform etching. 150 [W] RF (13.56 [MHz]) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Then, the W film was etched under the first etching conditions so that the end portion of the first conductive layer 5007 was tapered.
[0199]
Subsequently, the mask 5009 made of resist is changed to the second etching condition without being removed, and the etching gas is changed to CF _Four And Cl ₂ The gas flow ratio is 30:30 [sccm], and 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1.0 [Pa]. Then, plasma was generated and etching was performed for about 15 seconds. 20 [W] RF (13.56 [MHz]) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Under the second etching condition, the first conductive layer 5007 and the second conductive layer 5008 were etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film 5006, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0200]
In the first etching process described above, the shape of the resist mask is made suitable, so that the end portions of the first conductive layer 5007 and the second conductive layer 5008 can be obtained by the effect of the bias voltage applied to the substrate side. Becomes a tapered shape. In this manner, first shape conductive layers 5010 to 5014, 6010, and 6011 including the first conductive layer 5007 and the second conductive layer 5008 were formed by the first etching treatment. In the gate insulating film 5006, a region not covered with the first shape conductive layers 5010 to 5014, 6010, and 6011 was etched by about 20 to 50 nm, so that a region with a thin film thickness was formed.
[0201]
Next, a second etching process is performed without removing the resist mask 5009. (FIG. 3C) In the second etching process, SF is used as an etching gas. ₆ And Cl ₂ And O ₂ Each gas flow ratio is 24:12:24 (sccm), 700 W RF (13.56 MHz) power is applied to the coil side power at a pressure of 1.3 Pa, and plasma is generated for about 25 seconds. Etching was performed. 10 W of RF (13.56 MHz) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Thus, the W film was selectively etched to form second shape conductive layers 5015 to 5019, 6015, and 6016. At this time, the first conductive layers 5015a to 5018a, 6015a, and 6016a are hardly etched.
[0202]
Then, a first doping process is performed without removing the resist mask 5009, and an impurity element imparting N-type conductivity is added to the semiconductor layers 5002 to 5005, 6002, and 6003 at a low concentration. The first doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ [atoms / cm ² The acceleration voltage is 40 to 80 [keV]. In this embodiment, the dose amount is 5.0 × 10. ¹³ [atoms / cm ² The acceleration voltage was 50 [keV]. As an impurity element imparting N-type, an element belonging to Group 15 may be used. Typically, phosphorus (P) or arsenic (As) is used, but phosphorus (P) is used in this embodiment. In this case, the second shape conductive layers 5015 to 5019, 6015, and 6016 serve as a mask for the impurity element imparting N-type, and self-aligned first impurity regions (N−− regions) 5020 to 5023, 6020 and 6021 were formed. In the first impurity regions 5020 to 5023, 6020, and 6021, 1 × 10 ¹⁸ ~ 1x10 ²⁰ [atoms / cm ^Three In the concentration range, an impurity element imparting N-type was added.
[0203]
Subsequently, after removing the resist mask 5009, a resist mask 5024 is newly formed, and a second doping process is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 3x10 ¹⁵ [atoms / cm ² The acceleration voltage is 60 to 120 [keV]. In this embodiment, the dose amount is 3.0 × 10. ¹⁵ [atoms / cm ² The acceleration voltage was 65 [keV]. In the second doping treatment, the second conductive layers 5015b to 5018b, 6015b, and 6016b are used as masks against the impurity element, and the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layers 5015a to 5018a, 6015a, and 6016a. Doping is performed as added. Subsequently, the third doping process is performed by lowering the acceleration voltage than the second doping process to obtain the state of FIG. The condition of the ion doping method is a dose of 1 × 10 ¹⁵ ~ 1x10 ¹⁷ [atoms / cm ² The acceleration voltage is 50-100 keV.
[0204]
As a result of performing the second doping process and the third doping process, the second impurity regions (N− region and Lov region) 5026 and 6026 overlapping with the first conductive layer have 1 × 10 6. ¹⁸ ~ 5x10 ¹⁹ [atoms / cm ^Three In the concentration range, an impurity element imparting N-type was added. The third impurity regions (N + regions) 5025, 5028, and 6025 have 1 × 10 ¹⁹ ~ 5x10 ^{twenty one} [atoms / cm ^Three In the concentration range, an impurity element imparting N-type was added. In addition, after the first and second doping treatments, regions where no impurity element was added or regions where a small amount of impurity element was added were formed in the semiconductor layers 5002 to 5005, 6002 and 6003. In this embodiment, a region to which no impurity element is added or a region to which a small amount of impurity element is added is referred to as channel regions 5027, 5030, and 6027. Further, among the first impurity regions (N−− regions) 5020 to 5023, 6020, and 6021 formed by the first doping process, there is a region covered with the resist 5024 in the second doping process. In the present embodiment, the first impurity region (N−− region, LDD region) 5029 is called subsequently.
[0205]
In this embodiment, the second impurity regions (N− regions) 5026 and 6026 and the third impurity regions (N + regions) 5025, 5028, and 6025 are formed only by the second doping process. However, the present invention is not limited to this. Not. It may be formed by a plurality of doping processes by appropriately changing the conditions for performing the doping process.
[0206]
Next, as shown in FIG. 4A, after removing the resist mask 5024, a resist mask 5031 is newly formed. Thereafter, a fourth doping process is performed. A fourth impurity region (P + region) in which an impurity element imparting a conductivity type opposite to the first conductivity type is added to the semiconductor layer serving as an active layer of the P-channel TFT by the fourth doping process. 5032, 5034, 6032 and fifth impurity regions (P− regions) 5033, 5035, 6033 are formed.
[0207]
In the fourth doping treatment, the second conductive layers 5016b and 5018b are used as masks for the impurity element. In this manner, the impurity element imparting P-type is added, and the fourth impurity regions (P + regions) 5032, 5034, and 6032 and the fifth impurity regions (P− regions) 5033, 5035, and 6033 are formed in a self-aligning manner. .
[0208]
In this embodiment, the fourth impurity regions 5032, 5034, 6032 and the fifth impurity regions 5033, 5035, 6033 are diborane (B ₂ H ₆ ) Using an ion doping method. As a condition of the ion doping method, the dose amount is 1 × 10 ¹⁶ [atoms / cm ² The acceleration voltage was 80 [keV].
[0209]
Note that in the fourth doping process, the semiconductor layer forming the N-channel TFT is covered with a mask 5031 made of a resist.
[0210]
Here, by the first and second doping processes, phosphorus is added to the fourth impurity regions (P + regions) 5032, 5034, and 6032 and the fifth impurity regions (P− regions) 5033, 5035, and 6033 at different concentrations. It has been added. However, in any of the fourth impurity regions (P + regions) 5032, 5034, and 6032 and the fifth impurity regions (P− regions) 5033, 5035, and 6033, the P-type is imparted by the fourth doping process. Concentration of impurity element to be 1 × 10 ¹⁹ ~ 5x10 ^{twenty one} [atoms / cm ^Three The doping process is performed so that Thus, the fourth impurity regions (P + regions) 5032, 5034, and 6032 and the fifth impurity regions (P− regions) 5033, 5035, and 6033 function as a source region and a drain region of the P-channel TFT without any problem.
[0211]
In this embodiment, the fourth impurity regions (P + regions) 5032, 5034, and 6032 and the fifth impurity regions (P− regions) 5033, 5035, and 6033 are formed only by the fourth doping process. It is not limited to. It may be formed by a plurality of doping processes by appropriately changing the conditions for performing the doping process.
[0212]
Next, as shown in FIG. 4B, the resist mask 5031 is removed, and a first interlayer insulating film 5036 is formed. The first interlayer insulating film 5036 is formed of an insulating film containing silicon with a thickness of 100 to 200 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 100 [nm] is formed by plasma CVD. Needless to say, the first interlayer insulating film 5036 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0213]
Next, as shown in FIG. 4C, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and to activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 [° C.] in a nitrogen atmosphere with an oxygen concentration of 1 [ppm] or less, preferably 0.1 [ppm] or less. In this embodiment, 410 [° C.], 1 Activation treatment was performed by heat treatment for a period of time. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0214]
Further, heat treatment may be performed before the first interlayer insulating film 5036 is formed. However, when the materials forming the first conductive layers 5015a to 5019a, 6015a, and 6016a and the second conductive layers 5015b to 5019b, 6015b, and 6016b are vulnerable to heat, the wiring and the like are protected as in this embodiment. Therefore, heat treatment is preferably performed after the first interlayer insulating film 5036 (an insulating film containing silicon as a main component, for example, a silicon nitride film) is formed.
[0215]
As described above, after the first interlayer insulating film 5036 (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed, the semiconductor layer is hydrogenated simultaneously with the activation process by heat treatment. Can do. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5036.
[0216]
Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment.
[0217]
Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5036. As other means for hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation) or in an atmosphere containing 3 to 100% hydrogen at 300 to 450 [° C.] for 1 to 12 hours A means for performing heat treatment may be used.
[0218]
Next, a second interlayer insulating film 5037 is formed over the first interlayer insulating film 5036. As the second interlayer insulating film 5037, an inorganic insulating film can be used. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. An organic insulating film can be used as the second interlayer insulating film 5037. For example, a film made of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxynitride film may be used.
[0219]
In this embodiment, an acrylic film having a thickness of 1.6 [μm] is formed. With the second interlayer insulating film 5037, unevenness caused by the TFT formed on the substrate 5000 can be reduced and planarized. In particular, since the second interlayer insulating film 5037 has a strong meaning of planarization, a film having excellent planarity is preferable.
[0220]
Next, the second interlayer insulating film 5037, the first interlayer insulating film 5036, and the gate insulating film 5006 are etched using dry etching or wet etching, so that third impurity regions 5025, 5028, and 6025 fourth impurity regions are etched. Contact holes reaching 5032, 5034, and 6032 are formed.
[0221]
Subsequently, wirings 5038 to 5041, 6038, and 6039 and a pixel electrode 5042 that are electrically connected to the respective impurity regions are formed. These wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 [nm] and an alloy film (Al and Ti alloy film) having a thickness of 500 [nm]. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti. For example, an Al film or Cu film may be formed on the TaN film, and a laminated film formed with a Ti film may be patterned to form a wiring. However, it is desirable to use a material having excellent reflectivity.
[0222]
Subsequently, an alignment film 5043 is formed over a portion including at least the pixel electrode 5042 and a rubbing process is performed. In this embodiment, before the alignment film 5043 is formed, a columnar spacer 5045 for maintaining the substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0223]
Next, a counter substrate 5046 is prepared. Color layers (color filters) 5047 to 5049 and a planarization film 5050 are formed over the counter substrate 5046. At this time, the first colored layer 5047 and the second colored layer 5048 are overlapped to form a light shielding portion. Alternatively, the first colored layer 5047 and the third colored layer 5049 may be partially overlapped to form a light shielding portion, or the second colored layer 5048 and the third colored layer 5049 may be partially overlapped. Thus, a light shielding portion may be formed.
[0224]
In this way, the number of processes can be reduced by shielding the gaps between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a new light shielding layer.
[0225]
Next, a counter electrode 5051 made of a transparent conductive film was formed over the planarization film 5050 in at least the pixel region, an alignment film 5052 was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0226]
Then, the active matrix substrate on which the pixel region and the driver circuit are formed and the counter substrate are attached to each other with a sealant 5044. Filler is mixed in the sealing material 5044, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 5053 is injected between both the substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 5053. In this way, the liquid crystal display device shown in FIG. 4D is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate and an FPC (not shown) were attached.
[0227]
In this manner, a semiconductor device having high-speed operation as a whole device can be manufactured in a high-throughput manufacturing process by changing the activation process of the semiconductor film between a region requiring high-speed operation and a region not requiring high-speed operation. Is possible.
[0228]
In particular, the first region (the region having a circuit block that requires high-speed operation) includes a semiconductor film in which large crystal grains are formed by crystallization using a continuous wave laser. A TFT is fabricated to realize a circuit block capable of high-speed operation.
[0229]
Note that the TFT manufactured in this embodiment may have a bottom gate structure or a dual gate structure.
[Example 7]
In this embodiment, a manufacturing process of a substrate in which a circuit block including thin film transistors and an EL display portion are formed over the same substrate will be described.
[0230]
The steps up to FIG. 5A are the same as the steps shown in FIGS. 3A to 3D and FIG.
[0231]
3 and 4 are denoted by the same reference numerals, and description thereof is omitted.
[0232]
As shown in FIG. 5A, a first interlayer insulating film 5101 is formed. The first interlayer insulating film 5101 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 100 nm is formed by plasma CVD. Needless to say, the first interlayer insulating film 5101 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0233]
Next, as shown in FIG. 5B, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and to activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, it may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, activation treatment was performed by heat treatment at 410 ° C. for 1 hour. . In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0234]
Further, heat treatment may be performed before the first interlayer insulating film 5101 is formed. However, when the first conductive layers 5015a to 5019a and the second conductive layers 5015b to 5019b are vulnerable to heat, the first interlayer insulating film 5101 (silicon is used to protect the wiring and the like as in this embodiment. It is preferable to perform heat treatment after an insulating film containing a main component (eg, a silicon nitride film) is formed.
[0235]
As described above, after the first interlayer insulating film 5101 (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed, the semiconductor layer is hydrogenated simultaneously with the activation process by heat treatment. Can do. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5001.
[0236]
Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment.
[0237]
Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5101. As other means for hydrogenation, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in a means using plasma excited hydrogen (plasma hydrogenation) or in an atmosphere containing 3 to 100% hydrogen. Means may be used.
[0238]
Through the above steps, a CMOS circuit including an N-channel TFT and a P-channel TFT can be formed in the lower region of the pixel.
[0239]
Next, a second interlayer insulating film 5102 is formed over the first interlayer insulating film 5101. An inorganic insulating film can be used as the second interlayer insulating film 5102. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. Further, an organic insulating film can be used as the second interlayer insulating film 5102. For example, a film made of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.
[0240]
Next, dry etching or wet etching is used to etch the first interlayer insulating film 5101, the second interlayer insulating film 5102, and the gate insulating film 5006, so that impurity regions (third impurity regions) of the TFTs constituting the circuit block are etched. Contact holes reaching (N +) and the fourth impurity region (P +) are formed.
[0241]
Next, wirings 5103 to 5109, 6103, and 6104 that are electrically connected to the impurity regions are formed. In this embodiment, the wirings 5103 to 5109, 6103, and 6104 are formed by continuously forming a laminated film of a 100 nm thick Ti film, a 350 nm thick Al film, and a 100 nm thick Ti film by a sputtering method. It is formed by patterning into a desired shape.
[0242]
Of course, not only a three-layer structure but also a single-layer structure, a two-layer structure, or a stacked structure of four or more layers may be used. The wiring material is not limited to Al and Ti, and other conductive films may be used. For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed.
[0243]
Next, as shown in FIG. 5C, a third interlayer insulating film 5110 is formed. As the third interlayer insulating film 5110, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.
[0244]
With the third interlayer insulating film 5110, unevenness due to the TFT formed on the substrate 5000 can be reduced and planarized. In particular, since the third interlayer insulating film 5110 has a strong meaning of planarization, a film having excellent planarity is preferable.
[0245]
Next, a contact hole reaching the wiring 5108 is formed in the third interlayer insulating film 5110 by using dry etching or wet etching.
[0246]
Next, the pixel electrode 5111 is formed by patterning the conductive film. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. The pixel electrode 5111 corresponds to the cathode of the EL element. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements can be used freely.
[0247]
The pixel electrode 5111 is electrically connected to the wiring 5108 through a contact hole formed in the third interlayer insulating film 5110. Thus, the pixel electrode 5111 is electrically connected to one of the source region and the drain region of the TFT constituting the driver circuit.
[0248]
Next, as shown in FIG. 5D, a bank 5112 is formed in order to separate the EL layers between the pixels. The bank 5112 is formed using an inorganic insulating film or an organic insulating film. As the inorganic insulating film, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film.
[0249]
Here, when the bank 5112 is formed, a tapered side wall can be easily formed by using a wet etching method. Care must be taken because the deterioration of the EL layer due to the level difference becomes a significant problem unless the side wall of the bank 5112 is sufficiently gentle.
[0250]
Examples of combinations of the third interlayer insulating film 5110 and the bank 5112 are given below.
[0251]
A laminated film of acrylic and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used as the third interlayer insulating film 5110, and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used as the bank 5112. There are combinations that use. There is a combination in which a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5110 and a silicon oxide film formed by the plasma CVD method is also used as the bank 5112. Further, there is a combination in which a silicon oxide film formed by an SOG method is used as the third interlayer insulating film 5110 and a silicon oxide film formed by the SOG method is also used as the bank 5112. The third interlayer insulating film 5110 includes a combination of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method, and a bank 5112 using a silicon oxide film formed by a plasma CVD method. is there. Further, there is a combination in which acrylic is used for the third interlayer insulating film 5110 and acrylic is also used for the bank 5112. As the third interlayer insulating film 5110, there is a combination in which a stacked film of acrylic and a silicon oxide film formed by a plasma CVD method is used, and a silicon oxide film formed by a plasma CVD method is used as the bank 5112. Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5110 and acrylic is used as the bank 5112.
[0252]
Carbon particles or metal particles may be added to the bank 5112 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1x10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1x10 ^Ten The added amount of carbon particles and metal particles may be adjusted so as to be Ωm).
[0253]
Next, an EL layer 5113 is formed over the exposed pixel electrode 5038 surrounded by the bank 5112.
[0254]
As the EL layer 5113, a known organic light emitting material or inorganic light emitting material can be used.
[0255]
As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, and a medium molecular weight organic material can be freely used. In the present specification, the medium molecular organic light-emitting material refers to an organic light-emitting material that does not have sublimability and has a molecule number of 20 or less or a chained molecule length of 10 μm or less. To do.
[0256]
The EL layer 5113 usually has a stacked structure. A typical example is a “hole transport layer / light emitting layer / electron transport layer” stacked structure proposed by Tang et al. Of Kodak Eastman Company. In addition, the electron transport layer / the light emitting layer / the hole transport layer / the hole injection layer, or the electron injection layer / the electron transport layer / the light emitting layer / the hole transport layer / the hole injection layer are stacked in this order on the cathode. It may be a structure. You may dope a fluorescent pigment | dye etc. with respect to a light emitting layer. However, the charge excitation state before light emission may be a triplet or a singlet.
[0257]
In this specification, a light-emitting element means light emission (fluorescence) at the time of transition from a singlet exciton to a ground state and light emission (phosphorescence at the time of transition from a triplet exciton to a ground state). ) Indicates both.
[0258]
In this embodiment, the EL layer 5113 is formed by a vapor deposition method using a low molecular weight organic light emitting material. Specifically, as the light emitting layer, a tris-8-quinolinolato aluminum complex (Alq _Three ) Film is provided, and a 20 nm thick copper phthalocyanine (CuPc) film is provided thereon as a hole injection layer. Alq _Three The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1.
[0259]
Note that although only one pixel is illustrated in FIG. 5D, the EL layer 5113 corresponding to each of a plurality of colors, for example, R (red), G (green), and B (blue) is separately formed. can do.
[0260]
As an example of using a polymer organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided by a spin coating method as a hole injection layer, and a polyphenylene vinylene (PPV) or PPV film having a thickness of about 100 nm is formed thereon as a light emitting layer. The EL layer 5113 may be formed using a stacked structure provided with a derivative film. Note that when a PPV or PPV derivative that is a π-conjugated polymer is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer or the electron injection layer.
[0261]
Note that the EL layer 5113 is not limited to a layer in which a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like are clearly distinguished. That is, the EL layer 5113 may have a structure in which a material that forms a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, or the like is mixed.
[0262]
For example, a mixed layer composed of a material constituting an electron transport layer (hereinafter referred to as an electron transport material) and a material constituting a light emitting layer (hereinafter referred to as a light emitting material) The EL layer 5113 may be provided between the layers.
[0263]
Next, a pixel electrode 5114 made of a transparent conductive film is formed over the EL layer 5113. As the transparent conductive film, a compound of indium oxide and tin oxide (ITO), a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, indium oxide, or the like can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 5114 corresponds to the anode of the EL element.
[0264]
When the pixel electrode 5114 is formed, the EL element is completed. Note that an EL element refers to a diode formed by a pixel electrode (cathode) 5111, an EL layer 5113, and a pixel electrode (anode) 5114.
[0265]
It is effective to provide a protective film (passivation film) 5115 so as to completely cover the EL element. The protective film 5115 is formed using an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film can be used as a single layer or a combination of stacked layers.
[0266]
Note that when light emitted from the EL element is emitted from the pixel electrode 5114 side as in this embodiment, a film that transmits light needs to be used as the protective film 5115.
[0267]
Note that it is effective to continuously process the steps from the formation of the bank 5112 to the formation of the protective film 5115 using a multi-chamber type (or in-line type) film formation apparatus without opening to the atmosphere. .
[0268]
Actually, when the state shown in FIG. 5D is completed, a sealing material such as a protective film (laminate film, ultraviolet curable resin film, etc.) having high hermeticity and low degassing is used so as not to be exposed to the outside air. It is preferable to package (enclose). At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the EL element is improved.
[0269]
In addition, when airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or circuit formed on the substrate 5000 and an external signal terminal is attached. Completed as a product.
[0270]
Note that the TFT manufactured in this embodiment may have a bottom gate structure or a dual gate structure having two gate electrodes arranged above and below a channel region with an insulating film interposed therebetween.
[0271]
[Example 8]
In this embodiment, an example of a semiconductor device of the present invention will be described with reference to FIGS.
[0272]
In FIG. 16, the semiconductor device is formed by integrally forming a pixel region 1600, a scanning line driver circuit 1601, a signal line driver circuit 1602, a VRAM 1603, a CPU 1604, a memory 1605, and an interface circuit 1606 on a substrate having an insulating surface.
[0273]
An operation of the semiconductor device illustrated in FIG. 16 will be described. Image data and control signals for the external device are communicated between the CPU 1604 and the external device via the interface circuit 1606 and the system bus 1607. Examples of the external device include a keyboard and a ROM. The CPU 1604 temporarily stores the image data being processed and the control signal of the logic circuit in the memory 1605, and the processed image data is stored in the VRAM 1603. Image data stored in the VRAM 1603 is displayed in the pixel region 1600 by the signal line driver circuit 1602 and the scanning line driver circuit 1601.
[0274]
The VRAM is a memory for storing image data, and is configured by a volatile memory such as SRAM or DRAM. The memory 1605 is also a volatile memory such as SRAM or DRAM. The interface circuit is a circuit that temporarily stores a signal input from an external device, converts it into a format used internally, or performs other control.
[0275]
In this embodiment, since the circuit block included in the region 1 is particularly required to operate at high speed, for example, high movement using a semiconductor film crystallization process using a continuous wave laser as shown in Embodiments 3 to 6 is performed. Apply the TFT fabrication process.
[0276]
By applying a high mobility TFT manufacturing process to the region 1, the circuit block included in the region 1 realizes high-speed operation.
[0277]
When SRAM is used as the memory, 200 nsec is realized as a read cycle, and when DRAM is used, 1 μsec or less is realized as a read cycle.
[0278]
In addition, the operating frequency of the CPU is 5 MHz or more.
[0279]
In this embodiment, the high mobility TFT manufacturing process is applied to the region 1, but the present invention is not limited to this. The practitioner may apply a high mobility TFT manufacturing process to an arbitrary region in accordance with the use of the semiconductor device.
[0280]
Note that in that case, the ratio of the area to which the high mobility TFT manufacturing process is applied to the total area of the substrate 1608 is preferably 50% or less (preferably 30% or less). In addition, the region 1 is preferably formed with as few (preferably 10 or less) rectangular regions as possible.
[0281]
This embodiment can be used in combination with Embodiments 1 to 7.
[0282]
[Example 9]
In this embodiment, an example of a semiconductor device of the present invention will be described with reference to FIG.
[0283]
In FIG. 17, a semiconductor device includes a pixel region 1700, a scanning line driver circuit 1701, a signal line driver circuit 1702, a frame memory 1703, a timing generation circuit 1705, and a format converter 1704 which are integrally formed on a substrate having an insulating surface. .
[0284]
The configuration of this embodiment will be described below.
[0285]
A timing generation circuit 1705 generates a clock signal that determines operation timing of the scan line driver circuit 1701 and the signal line driver circuit 1702. The format conversion unit 1704 performs image processing such as decompression decoding of a compression-coded signal input from an external apparatus via the FPC 1706, image interpolation, and resizing. The format-converted image data is stored in the frame memory 1703. The image data stored in the frame memory 1703 is displayed on the pixel 1700 by the scanning line driver circuit 1701 and the signal line driver circuit 1702.
[0286]
In this embodiment, since the circuit block included in the region 1 is particularly required to operate at high speed, for example, high movement using a semiconductor film crystallization process using a continuous wave laser as shown in Embodiments 3 to 6 is performed. Apply the TFT fabrication process.
[0287]
When SRAM is used as the frame memory, 200 nsec is realized as a read cycle, and when DRAM is used, 1 μsec or less is realized as a read cycle.
[0288]
In this embodiment, the driving frequency of the logic circuit included in the region 1 is 5 MHz or more.
[0289]
In this embodiment, the high mobility TFT manufacturing process is applied to the region 1, but the present invention is not limited to this. The practitioner may apply a high mobility TFT manufacturing process to an arbitrary region in accordance with the use of the semiconductor device.
[0290]
Note that in that case, the ratio of the area to which the high mobility TFT manufacturing process is applied to the total area of the substrate 1608 is preferably 50% or less (preferably 30% or less). In addition, the region 2 is preferably formed of as few (preferably 10 or less) rectangular regions as possible.
[0291]
This embodiment can be used in combination with Embodiments 1 to 7.
[0292]
[Example 10]
In this embodiment, an example of a semiconductor device of the present invention will be described with reference to FIG.
[0293]
In FIG. 18, a semiconductor device includes a pixel region 1800, a scanning line driver circuit 1801, a signal line driver circuit 1802, a VRAM 1803, a mask ROM 1804, an arithmetic processing circuit 1805, an image processing circuit 1806, a memory 1807, and an interface circuit 1808. The substrate is integrally formed on the substrate.
[0294]
The configuration of this example is shown below.
[0295]
Control signals are communicated with external devices via the interface circuit 1808 and the system bus 1809. An example of the external device is a keyboard. The mask ROM 1804 stores program data and image data. Data stored in the mask ROM is processed by the CPU 1805 while reading from and writing to the memory 1807 as needed. The image data is subjected to processing such as resizing by the image processing circuit 1806 and stored in the VRAM 1803. Data stored in the VRAM 1803 is displayed in the pixel region 1800 by the scan line driver circuit 1801 and the signal line driver circuit 1802.
[0296]
SRAM and DRAM are used as the memory and VRAM.
[0297]
In this embodiment, the operating frequency of the image processing circuit is 5 MHz or more. The operating frequency of the CPU is 5 MHz or more.
[0298]
In this embodiment, since the circuit block included in the region 1 is particularly required to operate at high speed, for example, high movement using a semiconductor film crystallization process using a continuous wave laser as shown in Embodiments 3 to 6 is performed. Apply the TFT fabrication process.
[0299]
In this embodiment, the high mobility TFT manufacturing process is applied to the region 1, but the present invention is not limited to this. The practitioner may apply a high mobility TFT manufacturing process to an arbitrary region in accordance with the use of the semiconductor device.
[0300]
Note that in that case, the ratio of the area to which the high mobility TFT manufacturing process is applied to the total area of the substrate 1608 is preferably 50% or less (preferably 30% or less). In addition, the region 2 is preferably formed of as few (preferably 10 or less) rectangular regions as possible.
[0301]
This embodiment can be used in combination with Embodiments 1 to 7.
[0302]
[Example 11]
As an electronic device using the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, a portable information terminal (Mobile computer, mobile phone, portable game machine, electronic book, or the like), an image playback apparatus equipped with a recording medium (specifically, a recording medium such as a digital versatile disc (DVD) can be played back and the image displayed. And a device equipped with a display). Specific examples of these electronic devices are shown in FIGS.
[0303]
FIG. 19A illustrates a display device, which includes a housing 1401, a support base 1402, and a display portion 1403. The present invention can be applied to a display device having the display portion 1403.
[0304]
FIG. 19B illustrates a video camera, which includes a main body 1411, a display portion 1412, an audio input 1413, operation switches 1414, a battery 1415, an image receiving portion 1416, and the like. The present invention can be applied to a display device having the display portion 1412.
[0305]
FIG. 19C illustrates a laptop personal computer, which includes a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The present invention can be applied to a display device having the display portion 1423.
[0306]
FIG. 19D illustrates a portable information terminal which includes a main body 1431, a stylus 1432, a display portion 1433, operation buttons 1434, an external interface 1435, and the like. The present invention can be applied to a display device having the display portion 1433.
[0307]
FIG. 19E illustrates a sound reproducing device, specifically, an in-vehicle audio device, which includes a main body 1441, a display portion 1442, operation switches 1443 and 1444, and the like. The present invention can be applied to a display device having the display portion 1442. In this example, the on-vehicle audio device is taken as an example, but it may be used for a portable or home audio device.
[0308]
FIG. 19F illustrates a digital camera, which includes a main body 1451, a display portion (A) 1452, an eyepiece portion 1453, operation switches 1454, a display portion (B) 1455, a battery 1456, and the like. The present invention can be applied to a display device having the display portion (A) 1452 and the display portion (B) 1455.
[0309]
FIG. 19G illustrates a cellular phone, which includes a main body 1461, an audio output portion 1462, an audio input portion 1463, a display portion 1464, operation switches 1465, an antenna 1466, and the like. The present invention can be applied to a display device having the display portion 1464.
[0310]
Display devices used in these electronic devices can use not only glass substrates but also heat-resistant plastic substrates. As a result, the weight can be further reduced.
[0311]
It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.
[0312]
This embodiment can be implemented by being freely combined with the embodiment mode and Embodiments 1 to 7.
[0313]
【The invention's effect】
In the present invention, a semiconductor display portion and other circuit blocks are integrally formed on a substrate having an insulating surface by using a TFT manufacturing process that realizes high mobility. As a TFT manufacturing process realizing high mobility, a crystallization process of a semiconductor active layer using a continuous wave laser is used.
[0314]
As a result, there is provided a semiconductor device having a display unit that is small and has improved reliability associated with mounting of a substrate such as an IC chip.
A semiconductor device that realizes a high operating frequency is provided by reducing wiring capacitance and improving circuit characteristics by integration.
[0315]
Furthermore, the present invention is characterized in that the crystallization process using a continuous wave laser is selectively performed only on circuit blocks that require high-speed operation. As a result, the throughput of the crystallization process is significantly improved without reducing the operation speed of the semiconductor device. In addition, a semiconductor device having a low-cost display portion is provided due to a significant reduction in the number of substrates to be mounted such as an IC chip and the effect of high throughput.
[Brief description of the drawings]
FIG. 1 is a top view of a semiconductor device of the present invention.
FIG. 2 is a top view of the semiconductor device of the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing process of a TFT constituting a semiconductor device of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of a TFT constituting a semiconductor device of the present invention.
FIG. 5 is a cross-sectional view showing a manufacturing process of a TFT constituting a semiconductor device of the present invention.
FIG. 6 is a schematic diagram of an optical system used when irradiating laser light.
FIG. 7 is an SEM image of the surface of a crystalline semiconductor film.
FIG. 8 is an SEM image of the surface of a crystalline semiconductor film.
FIG. 9 Raman scattering spectrum of semiconductor film
10 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 11 is a graph showing the electrical characteristics of a TFT.
FIG. 12 is a cross-sectional view showing a semiconductor crystallization process.
FIG. 13 is a graph showing the electrical characteristics of a TFT.
FIG. 14 is a graph showing the electrical characteristics of a TFT.
FIG. 15 is a graph showing the electrical characteristics of a TFT.
FIG. 16 is a block diagram of a semiconductor device of the present invention.
FIG. 17 is a block diagram of a semiconductor device of the present invention.
FIG. 18 is a block diagram of a semiconductor device of the present invention.
FIG. 19 is an electronic device using the semiconductor display portion of the present invention.
FIG. 20 is a diagram showing a method of irradiating laser light.
FIG. 21 is a block diagram of a conventional semiconductor device.
FIG. 22 is a top view of the semiconductor device of the present invention.

Claims (17)

A semiconductor device in which a pixel region, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate ,
A first TFT having a first active layer; and a second TFT having a second active layer. The first active layer irradiates a semiconductor film with a continuous wave laser to form a melt zone. The second active layer is formed by crystallization by irradiating the semiconductor film with a pulsed laser, and is formed by continuous crystallization in the channel length direction.
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the second TFT,
2. The semiconductor device according to claim 1, wherein the signal line driver circuit includes the first TFT. A semiconductor device in which a pixel region, a scanning line driving circuit, and a signal line driving circuit are provided on the same substrate ,
A first TFT having a first active layer; and a second TFT having a second active layer. The first active layer irradiates a semiconductor film with a continuous wave laser to form a melt zone. The second active layer is formed by crystallization by irradiating the semiconductor film with a pulsed laser, and is formed by continuous crystallization in the channel length direction.
The pixel region is composed of the second TFT,
The scanning line driving circuit includes the first TFT,
2. The semiconductor device according to claim 1, wherein the signal line driver circuit includes the first TFT. Oite to claim 1 or claim 2,
The driving frequency of the scanning line driving circuit is 10 kHz to 1 MHz,
A driving frequency of the signal line driver circuit is 100 kHz to 100 MHz. Any one to Oite of claims 1 to 3, the memory is provided on the same substrate as the pixel region,
The semiconductor device, wherein the memory comprises the first TFT. 5. The semiconductor device according to claim 4 , wherein the memory is an SRAM, and a read cycle time of the SRAM is 200 nsec or less. 5. The semiconductor device according to claim 4 , wherein the memory is a DRAM, and a read cycle time of the DRAM is 1 μsec or less. Any one to Oite of claims 1 to 6, C PU is provided on the same substrate as the pixel region,
The semiconductor device according to claim 1, wherein the CPU comprises the first TFT. 8. The semiconductor device according to claim 7 , wherein an operating frequency of the CPU is 5 MHz or more. Any one to Oite of claims 1 to 8, images processing circuit is provided on the same substrate with the pixel area,
The semiconductor device according to claim 1, wherein the image processing circuit includes the first TFT. 10. The semiconductor device according to claim 9 , wherein an operating frequency of the image processing circuit is 5 MHz or more. Any one to Oite of claims 1 to 10, D SP are provided on the same substrate as the pixel region,
The DSP is composed of the first TFT. A semiconductor device, wherein: Any one to Oite of claims 1 to 11, timing generating circuit is provided on the same substrate with the pixel area,
2. The semiconductor device according to claim 1, wherein the timing generation circuit includes the first TFT. Any one to Oite of claims 1 to 12, and the substrate, wherein a plastic substrate, a one of a glass substrate or a quartz substrate. Any one to Oite of claims 1 to 13, the area of the circuit composed of the first 1TFT is wherein a is 50% or less of the area of the substrate. Any one to Oite of claims 1 to 14, a semiconductor device wherein the semiconductor device is a liquid crystal display device. Any one to Oite of claims 1 to 14, a semiconductor device wherein the semiconductor device is a light emitting device. One any one to Oite of claims 1 to 14, wherein the semiconductor device, a game machine, a video camera, a head-mounted display, DVD player, personal computer, cellular phone, selected from the car audio A semiconductor device characterized by the above.

Images