JP2004186215A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device with which a plurality of TFTs having different characteristics can be formed by separating them on the same substrate. <P>SOLUTION: A gate metal is formed, the gate metal is partially etched at every TFT different in the required characteristics, and a gate electrode is formed. Namely, resist is exposed and a resist mask is formed at every TFT different in the required characteristics. The gate metal is etched at every TFT different in the required characteristics by using the resist mask. The gate metal covering a semiconductor active layer in TFT except the TFT where the gate electrode is patterned is covered with a resist as it is. A gate electrode forming process of respective TFT is performed under an optimized condition by adjusting it to the required characteristics. An impurity element is doped to a source region, a drain region, a Lov region and a Loff region as required. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device including a thin film transistor. In particular, the present invention relates to a method for manufacturing a semiconductor device having a plurality of circuits and driven by different power supply voltages. Further, the present invention relates to an electronic device using the semiconductor device.
[Prior art]
2. Description of the Related Art In recent years, a semiconductor device including a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film formed over a substrate having an insulating surface and having a circuit formed by the TFT has been developed. As typical examples of a semiconductor device having a circuit formed by a TFT, an active matrix type liquid crystal display device, an active matrix type OLED (Organic Light Emitting Diode) display device, and the like are known.
[0002]
Here, an example of a method for manufacturing a TFT will be described. FIG. 9 is used for the description.
[0003]
As shown in FIG. 9A, a polycrystalline semiconductor film manufactured by a method such as crystallization of an amorphous semiconductor film is patterned on a substrate 1101 having an insulating surface to form a semiconductor active layer 1102c. And 1102d are formed. An insulating film 1103, a conductive film 1104, and a resist 1186 are formed over the semiconductor active layers 1102c and 1102d. Since the gate electrode of the TFT is formed by the conductive film 1104, the conductive film 1104 is also referred to as a gate metal. Note that FIG. 9 illustrates an example in which the gate metal is formed to have a single-layer structure of the conductive film 1104.
[0004]
After forming the resist 1186, a resist mask for patterning the gate metal is prepared. The pattern is exposed on the resist 1186 to expose the resist 1186. Thereafter, by performing development, masks (resist masks) 1123 and 1124 made of a resist as shown in FIG. 9B are formed. The conductive film 1104 is etched using the resist masks 1123 and 1124. Thus, a gate electrode 1121 and a gate electrode 1122 are manufactured. Thereafter, an impurity element imparting N-type is doped (doping 1). Thus, N-type impurity regions 1125a, 1125b, 1126a, and 1126b are formed in the semiconductor active layers 1102c and 1102d.
[0005]
Next, as shown in FIG. 9C, the resist masks 1123 and 1124 are removed, and a new resist mask 1128 is formed. Thereafter, an impurity element imparting a P-type is doped (doping 2). Thus, impurity regions 1129a and 1129b are formed in semiconductor active layer 1102d. Here, an N-type impurity element is added to the impurity regions 1129a and 1129b in Doping 1. However, by adding a P-type impurity element at a high concentration in Doping 2, the impurity regions 1129a and 1129b function as a source region and a drain region of the P-channel TFT without any problem.
[0006]
Thus, an N-channel TFT and a P-channel TFT can be formed.
[0007]
[Problems to be solved by the invention]
In recent years, characteristics such as field-effect mobility of TFTs (hereinafter, referred to as polycrystalline TFTs) using a crystalline semiconductor film (typically, a polycrystalline film) as an active layer have been improved. Therefore, it is becoming possible to form circuits having various functions using the TFT. Therefore, it has been expected that a circuit conventionally formed on a single crystal substrate will be formed on a substrate having an insulating surface, such as a glass substrate, by using a TFT, and attempts have been made. For example, it is expected that an arithmetic processing circuit, a memory element, and the like are formed using TFTs on the same substrate as a substrate on which pixels and the like of a display device such as a liquid crystal display device are formed.
[0008]
Here, in the case where various circuits are formed using TFTs on the same substrate having an insulating surface, characteristics required for the TFTs forming the circuits differ depending on the functions of the respective circuits. Therefore, it is necessary to separately produce TFTs having different characteristics. Hereinafter, differences in characteristics required for the TFTs forming the circuit according to the function of the circuit will be described with reference to specific examples.
[0009]
For example, a case in which an active matrix liquid crystal display device and an arithmetic processing circuit are to be formed over the same substrate using TFTs is described as an example. An active matrix liquid crystal display device includes a pixel portion including a plurality of pixels arranged in a matrix and a driving circuit portion (hereinafter, referred to as a pixel driving circuit portion) for inputting a video signal to the pixel portion. Have.
[0010]
FIG. 12 illustrates an example of a structure of a pixel portion of an active matrix liquid crystal display device. In the pixel portion, a plurality of signal lines S1 to Sx and scanning lines G1 to Gy are arranged. Pixels are arranged at intersections of the signal lines S1 to Sx and the scanning lines G1 to Gy. Each pixel has a switching element. The switching element selects the input of the video signal input to the signal lines S1 to Sx to each pixel according to the signal input to the scanning lines G1 to Gy. In FIG. 12, a TFT (hereinafter, referred to as a pixel TFT) 3002 is shown as the switching element. Further, a storage capacitor 3001 for holding a signal input to the pixel from the signal lines S1 to Sx, and a liquid crystal element 3003 whose transmittance changes according to a video signal input via the pixel TFT 3002 are provided.
[0011]
In each pixel, the gate electrode of the pixel TFT 3002 is connected to one of the scanning lines G1 to Gy. One of a source region and a drain region of the pixel TFT 3002 is connected to one of the signal lines S1 to Sx, and the other is connected to one electrode of the storage capacitor 3001 and one electrode of the liquid crystal element 3003.
[0012]
The pixel TFT 3002 included in the pixel is required to have low off-state current. This is to prevent a change in voltage applied between the electrodes of the liquid crystal element 3003 arranged in each pixel due to a leakage current, a change in transmittance, and a disturbance in an image. Further, in a liquid crystal display device of a type in which an image is visually recognized through the pixel TFT 3002 (hereinafter, referred to as a transmission type), it is required that the pixel TFT 3002 be miniaturized in order to increase an aperture ratio. Further, a voltage of about 16 V is normally applied between the electrodes of the liquid crystal element 3003. Therefore, the pixel TFT 3002 and the like are required to have a withstand voltage of about 16 V. Therefore, a TFT having a structure including a low-concentration impurity region overlapping with the gate electrode (hereinafter, referred to as a Lov region) and a low-concentration impurity region not overlapping with the gate electrode (hereinafter, referred to as a Loff region) is preferable.
[0013]
On the other hand, a TFT included in a pixel driving circuit portion (hereinafter, referred to as a pixel driving circuit TFT) does not require a reduction in off-current or a reduction in size as much as a pixel TFT. However, since it operates with a power supply voltage of about 16 V, a withstand voltage is required.
[0014]
The arithmetic processing circuit requires a high driving frequency. For this reason, TFTs included in an arithmetic circuit are required to have improved carrier mobility and smaller size. On the other hand, an arithmetic circuit manufactured using a miniaturized TFT can operate with a power supply voltage of about 3 to 5 V, and the withstand voltage of the TFT is not required as high as that of a pixel TFT or a TFT for a pixel driving circuit.
[0015]
It is necessary to make different TFTs according to the above-mentioned required characteristics.
[0016]
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a plurality of TFTs each having different characteristics or having different design rules can be separately formed on the same substrate.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention takes the following measures.
[0018]
A method for manufacturing a gate electrode by forming a gate metal and partially etching the gate metal for each TFT having different required characteristics. That is, the resist is exposed to each of the TFTs having different required characteristics to form a resist mask. Using the resist mask, the gate metal is etched for each TFT having different required characteristics. Here, the gate metal covering the semiconductor active layer of the TFT other than the TFT whose gate electrode is being patterned is covered with a resist mask. The step of manufacturing a gate electrode of each TFT may be performed under conditions optimized according to required characteristics.
[0019]
Here, the gate metal to be formed may have a single-layer structure, a stacked structure of two layers, or a multilayer structure of two or more layers.
[0020]
Note that steps up to gate metal film formation can be the same for TFTs formed on the same substrate. In addition, it is possible to use the same process after forming the gate electrode in all the TFTs formed on the same substrate. Note that it is not always necessary to use the same steps for all the TFTs formed on the same substrate except for the gate electrode formation. Some of the steps may be common. Thus, a plurality of TFTs having different characteristics can be separately formed with a smaller number of masks.
[0021]
It is possible to change the shape of the gate electrode to be manufactured by changing the method of etching the gate metal for each TFT having different required characteristics. For example, a TFT having a gate electrode having a tapered end and a TFT having a gate electrode having a substantially vertical end can be separately formed. In a TFT including a gate electrode having a tapered end, a low-concentration impurity region can be formed in a self-aligned manner by doping an impurity element through the tapered portion. Therefore, a TFT having a configuration excellent in pressure resistance can be obtained. Here, it is difficult to reduce the gate length and gate width of a TFT having a gate electrode having a tapered end. That is, it is not suitable for miniaturization. On the other hand, a TFT provided with a gate electrode having a substantially vertical end has a shape suitable for miniaturization. Thus, the shape of the TFT gate electrode can be changed according to the required characteristics.
[0022]
The wiring can be formed by etching the gate metal at the same time as forming the gate electrode having a tapered end. The shape of this wiring has a tapered end. In the case of a wiring having a tapered end portion, disconnection of a film formed over the wiring can be prevented, and defects can be reduced.
[0023]
The wiring can be formed by etching the gate metal at the same time as forming the gate electrode having a substantially vertical end. The shape of this wiring has a substantially vertical end. A wiring having a substantially vertical end can reduce the ratio L / S between the wiring width (L) and the wiring interval (S) as compared with a wiring having a tapered end having the same cross-sectional area. is there. Therefore, a wiring having a vertical end has a shape suitable for integration. Thus, the shape of the wiring can be changed according to the portion of the semiconductor device.
[0024]
In addition, the exposure means of the resist used when patterning the gate electrode is changed for each TFT having different required characteristics. Thus, the resolution of the patterning of the gate electrode can be changed. Note that the exposure means indicates exposure conditions and an exposure apparatus. The exposure apparatus has a radiant energy source (optical power source, electron beam source, or X-ray source) for exposing the resist, and exposes the pattern on the original (reticle or mask) to the resist using the radiant energy source. Device. Examples of the exposure apparatus that can be used include, but are not limited to, a reduction projection exposure apparatus (commonly called a stepper) and a mirror projection type exposure apparatus (hereinafter, referred to as MPA) that is a 1: 1 projection exposure apparatus. . A known exposure apparatus can be used freely. The exposure conditions include the wavelength of the radiant energy source used for the exposure, the magnification when exposing the original (reticle or mask) to the resist, the material of the resist, the exposure time, and the like.
[0025]
Further, in order to form a source region, a drain region, a Lov region, a Loff region, and the like of each TFT, doping with an impurity element is performed as necessary.
[0026]
An example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. FIG. 1A illustrates a typical example of a method for manufacturing a semiconductor device of the present invention. In FIG. 1A, a process for manufacturing a first TFT and a second TFT, which have different required characteristics, on the same substrate will be described.
[0027]
On each semiconductor active layer of the first TFT and the second TFT, a gate insulating film, a gate metal, and a resist are sequentially formed in common (film formation of the gate metal and the resist). After that, a first exposure is performed to form a resist mask for manufacturing a gate electrode of the first TFT. After that, the gate metal is etched using the resist mask to form a gate electrode of the first TFT (preparing a gate electrode of the first TFT). After that, doping with an impurity element is performed. For the first TFT, during the steps of the first exposure, the preparation of the gate electrode, the doping, and the like, the gate metal on the semiconductor active layer corresponding to the second TFT is covered with a resist mask so as not to be etched. .
[0028]
Next, after removing the resist mask, a new resist film is formed so as to cover regions where the first TFT and the second TFT are to be formed (resist film formation). After that, a second exposure is performed to form a resist mask for manufacturing a gate electrode of the second TFT. After that, the gate metal is etched using the resist mask to form a gate electrode of the second TFT (preparing a gate electrode of the second TFT). After that, doping with an impurity element is performed. For the second TFT, while performing the second exposure, the production of the gate electrode, the doping, and the like, the gate metal on the semiconductor active layer corresponding to the first TFT is covered with a resist mask so as not to be etched. .
[0029]
Thus, the first TFT and the second TFT are separately formed.
[0030]
Note that in the step of forming the gate electrode of each of the TFTs (the first TFT and the second TFT), the etching of the gate metal may be performed stepwise, and a doping step of an impurity element may be performed during the step.
[0031]
FIG. 1D illustrates an example in which a gate metal of a first TFT or a second TFT is formed in a step of etching a gate metal in a step and a step of doping an impurity element during the step. Note that in FIG. 1D, only the manufacturing process of one of the first TFT and the second TFT is described.
[0032]
As shown in FIG. 1D, after the first gate metal etching (gate metal etching 1), doping with an impurity element is performed. Next, after the second gate metal etching (gate metal etching 2), doping with an impurity element is performed. Further, a gate electrode is formed by the third gate metal etching (gate metal etching 3).
[0033]
Here, in the above two dopings, the shape of the gate metal serving as a mask in the doping of the impurity element is changed. Thus, it is possible to form, in the semiconductor active layer, a region to which the impurity element is added by both of the two dopings and a region to which the impurity element is added only by the doping step after the gate metal etching 2 is performed. it can. Thus, a region where the impurity element is added at a high concentration and a region where the impurity element is added at a low concentration are formed in the semiconductor active layer.
[0034]
The step illustrated in FIG. 1D may be performed in the step of manufacturing the gate electrode in FIG. 1A (the step of manufacturing the gate electrode of the first TFT and the step of manufacturing the gate electrode of the second TFT). .
[0035]
In the case of a TFT in which a gate manufacturing process is performed as illustrated in FIG. 1D, a subsequent impurity element doping process is not necessarily required.
[0036]
FIG. 1B illustrates an example of a method for manufacturing a semiconductor device of the present invention which is different from FIG. 1A. In the step shown in FIG. 1A, after the gate electrodes of the respective TFTs (the first TFT and the second TFT) are formed, doping with an impurity element is performed. However, in the manufacturing method illustrated in FIG. 1B, after the gate electrode of the first TFT is manufactured, the gate electrode of the second TFT is manufactured without doping an impurity element. Finally, the first TFT and the second TFT are manufactured by performing the impurity element doping step commonly on the first TFT and the second TFT. In the step illustrated in FIG. 1B, the number of times of doping is smaller than that in FIG. 1A, and the number of manufacturing steps can be reduced.
[0037]
FIG. 1C is an example of a method for manufacturing a semiconductor device of the present invention which is different from FIGS. 1A and 1B. The manufacturing method illustrated in FIG. 1C is a combination of the manufacturing method illustrated in FIG. 1A and the manufacturing method illustrated in FIG. That is, this is a manufacturing method in which part of the doping step in manufacturing the first TFT and part of the doping step in manufacturing the second TFT are performed simultaneously. Since part of the doping steps of the first TFT manufacturing step and the second TFT manufacturing step is performed at the same time, the manufacturing steps can be simplified as compared with the manufacturing method in FIG. On the other hand, a doping step is also performed in each of the manufacturing steps of the first TFT and the second TFT, so that the conditions for doping an impurity element in the manufacturing method of FIG. And the second TFT.
[0038]
Note that in the step of forming the gate electrode of each of the TFTs (the first TFT and the second TFT), the etching of the gate metal may be performed stepwise, and a doping step of an impurity element may be performed during the step. For example, a step illustrated in FIG. 1D is performed in a step of manufacturing a gate electrode in FIG. 1C (a step of manufacturing a gate electrode of a first TFT and a step of forming a gate electrode of a second TFT). Is also good. In the case of a TFT in which a gate manufacturing process is performed as illustrated in FIG. 1D, a subsequent impurity element doping process is not necessarily required.
[0039]
Note that in each of the manufacturing methods illustrated in FIGS. 1A to 1C, the exposure unit used in the first exposure step and the exposure unit used in the second exposure step are the same. You can do it or you can make it different. An example in which the exposure unit used in the first exposure step and the exposure unit used in the second exposure step are different will be described below.
[0040]
For example, when the second TFT is required to be finer than the first TFT, the wavelength of light used in the second exposure process is compared with the wavelength of light used in the first exposure process. Be short. Further, for example, in the case where the second TFT is required to be finer than the first TFT, in the first exposure step, exposure is performed using MPA, and in the second exposure step, a stepper is used. Exposure is performed using.
[0041]
A method of changing exposure means in manufacturing a resist mask for forming gate electrodes of the first TFT and the second TFT will be described with reference to FIGS.
[0042]
As shown in FIG. 11A, a region (first region) having a TFT (first TFT) on which a gate electrode is patterned by a resist mask obtained in a first exposure step is provided over a substrate. A region (second region) having a TFT (second TFT) in which a gate electrode is patterned can be separately formed by the resist mask obtained in the second exposure process.
[0043]
Here, in the production of the gate electrode of the first TFT and the production of the gate electrode of the second TFT, it is desirable that the production of the gate electrode of the TFT for which miniaturization is required is performed later. Thus, a wiring formed by etching the gate metal in the step of forming the gate electrode of the first TFT, and a wiring formed by etching the gate metal in the step of forming the gate electrode of the second TFT And can be connected smoothly.
[0044]
Further, each of the first exposure step and the second exposure step may be performed using a plurality of exposure means. For example, as shown in FIG. 11B, a region (first region) where the gate electrode is patterned by the resist mask obtained in the first exposure step is formed by first exposure means and first exposure. It is possible to perform patterning using a resist mask formed using both the second exposure means different from the means. That is, after forming a resist that can be used in common by the first exposure unit and the second exposure unit, exposure is performed in the first region by the first exposure unit. Subsequently, exposure is performed by the second exposure means. Finally, development may be performed to form a resist mask.
[0045]
In each of the first TFT manufacturing process and the second TFT manufacturing process in FIG. 1, a resist mask is newly formed in addition to a resist mask necessary for etching a gate metal, and impurities are selectively formed in a specific region. Elements may be added. In this manner, an impurity region which is not formed in a self-aligned manner by the gate electrode can be formed.
[0046]
Further, a sidewall may be formed on a side surface of the gate electrode with an insulator. Further, an LDD region may be formed by adding an impurity element using the sidewall as a mask. In particular, when an LDD region or the like is formed in a TFT requiring miniaturization, the above-described method using the sidewall can more accurately align the mask than forming the LDD region using a resist mask. Therefore, it is preferable.
[0047]
Note that in the step of manufacturing the gate electrode of the first TFT in FIG. 1, gate electrodes corresponding to two TFTs having different polarities may be manufactured at the same time. Further, in the manufacturing process of the gate electrode of the second TFT in FIG. 1, gate electrodes corresponding to two TFTs having different polarities may be manufactured at the same time. At this time, in the manufacturing process of the first TFT and the manufacturing process of the second TFT, it is necessary to change the doping condition of the impurity element according to the TFT of each polarity. Therefore, a resist mask may be newly formed in addition to a resist mask necessary for etching the gate metal, and an impurity element may be selectively added to a specific region.
[0048]
The semiconductor films forming the semiconductor active layers of the first TFT and the second TFT may be crystallized by laser annealing using continuous wave laser light.
[0049]
Note that FIG. 1 shows the step of separately forming the gate electrode of the TFT by performing the two exposure steps (first exposure and second exposure); however, the present invention is not limited to this. INDUSTRIAL APPLICABILITY The present invention includes a plurality of exposure steps, and can be applied to a step of separately forming a gate electrode of a TFT for each exposure step.
[0050]
Thus, it is possible to provide a method for manufacturing a semiconductor device in which a plurality of TFTs each having different characteristics or having different design rules can be separately formed over the same substrate.
[0051]
According to the present invention, circuits having various functions can be manufactured over one substrate. In this way, a circuit that has been conventionally externally mounted with an IC chip or the like can be manufactured on the same substrate, and the device can be reduced in size and weight. In addition, since a plurality of TFTs having different characteristics can be separately formed with a smaller number of masks, the increase in the number of steps can be reduced, and the cost can be reduced.
[0052]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. Note that the example of the manufacturing process described in Embodiment 1 is equivalent to the example illustrated in FIG. 1C in means for solving the problem. In particular, in the example of manufacturing the gate electrode of the first TFT in FIG. 1C, the process of the pattern shown in FIG. 1D is used, and doping immediately after manufacturing the gate electrode of the first TFT is omitted. Equivalent to.
[0053]
In FIG. 2A, as a substrate 101, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate over which an insulating film is formed is used. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature in this manufacturing step may be used. In this embodiment mode, a substrate 101 made of glass such as barium borosilicate glass or aluminoborosilicate glass is used.
[0054]
Next, a base film (not shown) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 101. The base film may have a single-layer structure of the insulating film or a structure in which two or more insulating films are stacked.
[0055]
In this embodiment mode, the first layer of the base film is made of SiH using a plasma CVD method. ₄ , NH ₃ , And N ₂ A silicon nitride oxide film formed with O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, the silicon nitride oxide film is formed to a thickness of 50 nm. Next, as the second layer of the base film, SiH ₄ And N ₂ A silicon oxynitride film is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using O as a reaction gas. In this embodiment, the silicon oxynitride film is formed to a thickness of 100 nm.
[0056]
Subsequently, a semiconductor film is formed over the base film. The semiconductor film is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (sputtering, LPCVD, plasma CVD, or the like). Next, the semiconductor film is crystallized using a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, or the like). Note that a thermal crystallization method using a metal element that promotes crystallization and a laser crystallization method may be combined. For example, after performing a thermal crystallization method using a metal element that promotes crystallization, a laser crystallization method may be performed.
[0057]
Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers (semiconductor active layers) 102a to 102d. Note that as the semiconductor layer, an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film, or the like can be used.
[0058]
In this embodiment mode, an amorphous silicon film with a thickness of 55 nm is formed by a plasma CVD method. Then, a solution containing nickel is held on the amorphous silicon film, and after the amorphous silicon film is dehydrogenated (500 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours) is performed. Line to form a crystalline silicon film. Thereafter, island-shaped semiconductor layers 102a to 102d are formed by a patterning process using a photolithography method.
[0059]
Note that when a crystalline semiconductor film is formed by a laser crystallization method, a continuous wave or pulsed gas laser or a solid laser may be used. As the former gas laser, excimer laser, YAG laser, YVO ₄ Laser, YLF laser, YAlO ₃ Laser, glass laser, ruby laser, Ti: sapphire laser, or the like can be used. The latter solid-state laser includes YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti or Tm. ₄ , YLF, YAlO ₃ A laser using a crystal such as the above can be used. The fundamental wave of the laser depends on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. Harmonics with respect to the fundamental wave can be obtained by using a nonlinear optical element. Note that in order to obtain a crystal with a large grain size during crystallization of the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and apply the second to fourth harmonics of a fundamental wave. . Typically, Nd: YVO ₄ A second harmonic (532 nm) or a third harmonic (355 nm) of a laser (a fundamental wave of 1064 nm) is applied.
[0060]
In addition, a continuous oscillation YVO with an output of 10 W ₄ Laser light emitted from the laser is converted into harmonics by a nonlinear optical element. Furthermore, YVO is placed in the resonator. ₄ There is also a method of emitting a harmonic by putting a crystal and a nonlinear optical element. Then, the laser light is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser beam is irradiated on the object to be processed. The energy density at this time is 0.01 to 100 MW / cm ² Degree (preferably 0.1 to 10 MW / cm ² )is necessary. Then, irradiation is performed by moving the semiconductor film relatively to the laser light at a speed of about 10 to 2000 cm / s.
[0061]
In the case of using the above laser, it is preferable that a laser beam emitted from a laser oscillator be linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are set as appropriate. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 700 mJ / cm. ² (Typically 200 to 300 mJ / cm ² ). When a YAG laser is used, the second harmonic is used to set the pulse oscillation frequency to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ / cm. ² (Typically 350-500 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm (preferably 400 μm) is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 50 to 98% Is also good.
[0062]
However, in the present embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and heat treatment (such as RTA method or thermal annealing using a furnace annealing furnace) is performed. After the metal element is diffused, the amorphous silicon film is removed by etching after the heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed.
[0063]
Note that after forming the island-shaped semiconductor layers 102a to 102d, doping of a trace amount of an impurity element (boron or phosphorus) may be performed. In this manner, the threshold value of the TFT can be controlled by adding a small amount of an impurity element to a region to be a channel region.
[0064]
Next, a gate insulating film 103 which covers the semiconductor layers 102a to 102d is formed. The gate insulating film 103 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed to a thickness of 115 nm by a plasma CVD method as the gate insulating film 103. Needless to say, the gate insulating film 103 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. Note that in the case where a silicon oxide film is used as the gate insulating film 103, TEOS (Tetraethyl Orthosilicate) and O ₂ At a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., a high frequency (13.56 MHz), and a power density of 0.5 to 0.8 W / cm. ² And may be formed by discharging. Good characteristics as the gate insulating film 103 can be obtained from the silicon oxide film formed by the above-described steps by subsequent thermal annealing at 400 to 500 ° C.
[0065]
Here, a specific region of the semiconductor layers 102a to 102d may be doped with an impurity element before forming the gate electrode. By forming a gate electrode so as to overlap with the impurity region formed at this time, a Lov region or the like can be formed. Note that when the semiconductor layers 102a to 102d are doped with an impurity element, an insulating film (denoted as a doping insulating film) other than the gate insulating film 103 may be formed. In this case, after the doping process is completed, the doping insulating film is removed.
[0066]
Next, the first conductive film 104a is formed of TaN to a thickness of 20 to 100 nm, and the second conductive film 104b is formed of W to a thickness of 100 to 400 nm. Thus, a gate metal having a two-layer structure is formed. In this embodiment mode, a first conductive film 104a made of a TaN film with a thickness of 30 nm and a second conductive film 104b made of a W film with a thickness of 370 nm are stacked.
[0067]
In this embodiment mode, the TaN film serving as the first conductive film 104a is formed by a sputtering method in a nitrogen-containing atmosphere using a Ta target. The W film serving as the second conductive film 104b is formed by a sputtering method using a W target. In addition, tungsten hexafluoride (WF ₆ ) Can be formed by a thermal CVD method. In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains a large amount of impurity elements such as oxygen, crystallization is inhibited and the resistance is increased. Therefore, in this embodiment mode, the W film is formed by a sputtering method using a high-purity W (purity: 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. To realize a resistivity of 9 to 20 μΩcm.
[0068]
Note that in this embodiment mode, the first conductive film 104a is a TaN film and the second conductive film 104b is a W film; however, the materials forming the first conductive film 104a and the second conductive film 104b are not particularly limited. Not done. The first conductive film 104a and the second conductive film 104b are made of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. It may be formed. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used.
[0069]
Next, a resist 105 is formed. As a method for forming the resist 105, a coating method can be used. Note that a spin coater or a roll coater may be used for the coating method. The resist 105 can be either a positive type or a negative type, and can be selected according to a light source used at the time of exposure.
[0070]
Next, as shown in FIG. 2B, the resist 105 is exposed (first exposure) to form resist masks 108, 109, and 185, and a first etching process (gate metal) for manufacturing a gate electrode is performed. Perform etching 1). In this embodiment mode, an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method is used as an etching method of the first etching process, and CF is used as an etching gas. ₄ And Cl ₂ And a plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa. A 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF ₄ And Cl ₂ Is mixed, the W film and the Ta film are etched to the same extent.
[0071]
Note that the portions of the first conductive film 104a and the second conductive film 104b formed over the semiconductor layers 102c and 102d are not etched because they are covered with the resist mask 185.
[0072]
Under the above etching conditions, the shape of the resist mask is made appropriate, so that the ends of the first conductive layers 106a and 107a and the second conductive layers 106b and 107b are tapered due to the effect of the bias voltage applied to the substrate side. Shape. Here, the angle (taper angle) of the portion having a tapered shape (tapered portion) is defined as the angle formed between the surface (horizontal plane) of the substrate 101 and the inclined portion of the tapered portion. By appropriately selecting the etching conditions, the angles of the tapered portions of the first conductive layer and the second conductive layer can be set to 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film 103, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 106 and 107 (the first conductive layers 106a and 107a and the second conductive layers 106b and 107b) including the first conductive layer and the second conductive layer by the first etching process. To form At this time, in the gate insulating film 103, the exposed region is etched by about 20 to 50 nm, and a thinned region is formed.
[0073]
Then, a first doping process (doping 1) is performed to add an impurity element imparting N-type. The doping may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are as follows: ^Thirteen ~ 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 60 to 100 kV. An element belonging to Group XV, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting the N-type. Here, phosphorus (P) is used. In this case, the first shape conductive layers 106 and 107 (the first conductive layers 106a and 107a and the second conductive layers 106b and 107b) are used as a mask for an impurity element imparting N-type conductivity in a self-aligned manner. Impurity regions 110a, 110b, 111a, and 111b are formed. The first impurity regions 110a, 110b, 111a, and 111b have 1 × 10 ²⁰ ~ 1 × 10 ²¹ atoms / cm ³ Is added within the concentration range of.
[0074]
Next, as shown in FIG. 2C, a second etching process (gate metal etching 2) is performed without removing the resist mask. CF for etching gas ₄ And Cl ₂ And O ₂ Is used to selectively etch the W film. Thus, the second shape conductive layers 412 and 413 (the first conductive layers 412a and 413a and the second conductive layers 412b and 413b) are formed by the second etching treatment. At this time, in the gate insulating film 103, the exposed region is further etched by about 20 to 50 nm and becomes thin.
[0075]
CF of W film and Ta film ₄ And Cl ₂ The etching reaction by the mixed gas of (1) and (2) can be inferred from the generated radical or ionic species and the vapor pressure of the reaction product. Comparing the vapor pressures of fluorides of W and Ta and chlorides, WF, which is a fluoride of W, ₆ Is extremely high and other WCl ₅ , TaF ₅ , TaCl ₅ Are comparable. Therefore, CF ₄ And Cl ₂ With the mixed gas, both the W film and the Ta film are etched. However, an appropriate amount of O ₂ To add CF ₄ And O ₂ Reacts to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even when the F increases. Also, since Ta is more easily oxidized than W, O ₂ Is added to oxidize the surface of Ta. Since the oxide of Ta does not react with fluorine or chlorine, the etching rate of the Ta film is further reduced. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and it is possible to make the etching rate of the W film higher than that of the Ta film.
[0076]
Then, a second doping process (doping 2) is performed. In this case, the dose is lower than that in the first doping process, and an impurity element imparting N-type is doped under a condition of a high acceleration voltage. For example, the acceleration voltage is set to 70 to 120 kV and 1 × 10 ^Thirteen atoms / cm ² 2B, a new impurity region is formed inside the first impurity regions 110a, 110b, 111a, and 111b formed in the island-shaped semiconductor layer in FIG. 2B. The doping is performed using the second conductive layers 412b and 413b as a mask for the impurity element, and is performed so that the impurity element is also added to the semiconductor layer in a region below the first conductive layers 412a and 413a. Thus, second impurity regions 416a, 416b, 418a, and 418b are formed. The concentration of phosphorus (P) added to second impurity regions 416a, 416b, 418a, and 418b has a gentle concentration gradient according to the thickness of the tapered portions of first conductive layers 412a and 413a. Note that in the semiconductor layer overlapping with the tapered portions of the first conductive layers 412a and 413a, although the impurity concentration slightly decreases inward from the ends of the tapered portions of the first conductive layers 412a and 413a, almost It is about the same concentration.
[0077]
Subsequently, a third etching process (gate metal etching 3) is performed as shown in FIG. CHF for etching gas ₆ Using a reactive ion etching method (RIE method). By the third etching treatment, the tapered portions of the first conductive layers 412a and 413a are partially etched, so that a region where the first conductive layer overlaps with the semiconductor layer is reduced. By the third etching treatment, third shape conductive layers 112 and 113 (first conductive layers 112a and 113a and second conductive layers 112b and 113b) are formed. At this time, in the gate insulating film 103, the exposed region is further etched by about 20 to 50 nm and becomes thin. By the third etching treatment, the second impurity regions 416a, 416b, 418a, and 418b are formed so that the second impurity regions 117a, 117b, 119a, and 119b overlap with the first conductive layers 112a and 113a and the first impurity regions. Third impurity regions 116a, 116b, 118a, and 118b are formed between the first impurity region and the second impurity region.
[0078]
Next, as shown in FIG. 2E, after removing the resist masks 108, 109, and 185, a new resist 186 is formed. As a method for forming the resist 186, a coating method can be used. Note that a spin coater or a roll coater may be used for the coating method. The resist 186 can be either a positive type or a negative type, and can be selected according to a light source used at the time of exposure. Note that the resist 186 may be the same material as the resist 105 used for the first exposure, or may be different.
[0079]
Next, the resist 186 is exposed (second exposure) to form resist masks 123, 124, and 187 (FIG. 2F). Note that the exposure means in the second exposure may be the same as or different from the first exposure. Next, a fourth etching process (gate metal etching 4) is performed. Thus, fourth-shaped conductive layers 121 and 122 (first conductive layers 121a and 122a, and second conductive layers 121b and 122b) having substantially perpendicular ends are formed. Note that portions of the third shape conductive layers 112 and 113 (first conductive layers 112a and 113a and second conductive layers 112b and 113b) formed over the semiconductor layers 102a and 102b are covered with a resist mask 187. Is not etched.
[0080]
After that, a third doping process (doping 3) is performed. In the third doping treatment, an impurity element imparting N-type is added. The doping may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are as follows: ^Thirteen ~ 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 60 to 100 kV. An element belonging to Group XV, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting the N-type. Here, phosphorus (P) is used. In this case, the fourth impurity regions 125a, 125b, 126a, and 126b are formed using the resist masks 123, 124, and 187 as masks for the impurity element imparting N-type. The fourth impurity regions 125a, 125b, 126a, and 126b have 1 × 10 ²⁰ ~ 1 × 10 ²¹ atoms / cm ³ Is added in the concentration range of N. Note that since the semiconductor layers 102a and 102b are covered with the resist mask 187, no impurity element is added in the third doping treatment.
[0081]
Note that in this embodiment mode, the conditions of the doping of the impurity element into the fourth impurity regions 125a, 125b, 126a, and 126b (the third doping process) are set to the first impurity regions 110a, 110b, 111a, and 111b. (The first doping process). However, it is not limited to this. Conditions may be different between the first doping process and the third doping process.
[0082]
Next, as shown in FIG. 2G, after removing the resist masks 187, 123, and 124, new resist masks 127 and 128 are formed, and a fourth doping process (doping 4) is performed. In the fourth doping process, an impurity element imparting P-type is added. The doping may be performed by an ion doping method or an ion implantation method. Fourth impurity regions 190a, 190b, 191a, 191b, 129a, 129b to which a P-type impurity element is added are formed in the island-shaped semiconductor layers 102b and 102d forming the P-channel TFT. At this time, the third shape conductive layer 113b and the fourth shape conductive layer 122 are used as masks for impurity elements, and impurity regions are formed in a self-aligned manner. Note that the entire surface of the island-shaped semiconductor layers 102a and 102c forming the N-channel TFT is covered with resist masks 127 and 128.
[0083]
Note that phosphorus is added to the fourth impurity regions 190a, 190b, 191a, 191b, 129a, and 129b at different concentrations by the first doping process, the second doping process, and the third doping process. However, diborane (B ₂ H ₆ ), An impurity element imparting P-type is added to any of the regions. At this time, the concentration of the impurity element imparting P-type in the fourth impurity regions 190a, 190b, 191a, 191b is 2 × 10 4 ²⁰ ~ 2 × 10 ²¹ atoms / cm ³ So that Thus, the fourth impurity regions 190a, 190b, 191a, and 191b function without any problem as a source region and a drain region of the P-channel TFT. In addition, the fourth impurity regions 129a and 129b function as a Lov region of the P-channel TFT without any problem.
[0084]
Through the above steps, impurity regions are formed in the respective semiconductor layers 102a to 102d. The third shape conductive layers 112 and 113 and the fourth shape conductive layers 121 and 122 which overlap with the island-shaped semiconductor layer function as gate electrodes.
[0085]
Thus, as shown in FIG. 2H, an N-channel TFT 71, a P-channel TFT 72, an N-channel TFT 73, and a P-channel TFT 74 are formed.
[0086]
The N-channel TFT 71 includes high-concentration impurity regions 110a and 110b corresponding to the channel region 192, the source region and the drain region, low-concentration impurity regions (Lov regions) 117a and 117b overlapping the gate electrode, and low-concentration impurities not overlapping the gate electrode. It has regions (Loff regions) 116a and 116b. On the other hand, the P-channel TFT 72 has a channel region 193, high-concentration impurity regions 190a and 190b corresponding to the source and drain regions, and low-concentration impurity regions (Lov regions) 129a and 129b overlapping the gate electrode. Note that the structure has no Loff region. The gate electrodes of the N-channel TFT 71 and the P-channel TFT 72 have tapered ends. Therefore, in order to reduce the size of the gate electrode, the TFT has an inappropriate shape. However, since the Lov region and the Loff region can be manufactured in a self-aligned manner in the manufacturing process of the gate electrode, the number of steps in manufacturing the TFT can be reduced. Thus, a TFT with high withstand voltage can be formed by reducing the number of steps.
[0087]
The N-channel TFT 73 has a channel region 194 and high-concentration impurity regions 125a and 125b corresponding to a source region and a drain region. The P-channel TFT 74 has a channel region 195 and high-concentration impurity regions 191a and 191b corresponding to a source region and a drain region. The N-channel TFT 73 and the P-channel TFT 74 have a single drain structure. When the N-channel TFT 73 and the P-channel TFT 74 are TFTs having a Lov region or a Loff region, a new mask is required and the number of steps increases. However, since the end of the gate electrode is etched vertically, miniaturization is possible.
[0088]
For example, a circuit requiring high withstand voltage can be manufactured using the N-channel TFT 71 and the P-channel TFT 72, and a circuit requiring miniaturization can be manufactured using the N-channel TFT 73 and the P-channel TFT 74.
[0089]
Note that the exposure unit used in the first exposure step and the exposure unit used in the second exposure step can be the same or different. Here, in general, the shorter the wavelength of the radiant energy source used for exposure, the higher the resolution at the time of exposure. Therefore, for example, when the N-channel TFT 73 and the P-channel TFT 74 are required to be finer than the N-channel TFT 71 and the P-channel TFT 72, the wavelength of the light used in the first exposure process is The wavelength of light used in the second exposure step is short.
[0090]
Further, the exposure apparatus used for the first exposure step and the exposure apparatus used for the second exposure step can be the same or different.
[0091]
For example, in a case where the N-channel TFT 73 and the P-channel TFT 74 are required to be finer than the N-channel TFT 71 and the P-channel TFT 72, in the first exposure step, exposure is performed using MPA, In step 2 of exposure, exposure is performed using a stepper. Here, in general, MPA can expose a large area at a time, which is advantageous in the productivity of semiconductor devices. On the other hand, in the stepper, the pattern on the reticle is projected by an optical system, and the pattern is exposed on the resist by operating and stopping (step and repeat) the substrate-side stage. Although it is not possible to expose a large area at a time as compared with MPA, it is possible to increase the line-and-space (L & S) resolution (hereinafter the resolution refers to the L & S resolution).
[0092]
As another example, when the N-channel TFT 73 and the P-channel TFT 74 are required to be finer than the N-channel TFT 71 and the P-channel TFT 72, the pattern on the reticle is formed in the first exposure step. In the second exposure step, exposure is performed using a stepper having a large reduction ratio when projecting the pattern on the reticle onto the resist with the optical system. Do. The reduction ratio of the stepper indicates N when the pattern on the reticle is projected on the resist by multiplying by 1 / N (N is an integer). Here, in general, a stepper having a large reduction ratio when projecting a pattern on a reticle onto a resist by an optical system has a small resolution but a high resolution at a time. On the other hand, a stepper having a small reduction ratio when projecting a pattern on a reticle onto a resist by an optical system has a wide range that can be exposed at a time, but has a low resolution.
[0093]
As described above, by changing the exposure means in the first exposure step and the second exposure step, it is possible to manufacture a semiconductor device having high productivity and a TFT having good characteristics. is there. Note that the exposure means (exposure conditions and exposure apparatus) used in the first exposure and the second exposure step are not limited to the above. Known exposure means can be used freely. In addition, each of the first exposure step and the second exposure step may be performed using a plurality of exposure units.
[0094]
Note that in this embodiment, a manufacturing process of a single-gate TFT is described; however, a double-gate structure or a multi-gate structure having more gates may be used.
[0095]
Note that in this embodiment mode, a top-gate TFT is described and a manufacturing process thereof is described. However, the method for manufacturing a semiconductor device of the present invention can be applied to a dual-gate TFT. Note that a dual-gate TFT is a TFT that has a gate electrode that overlaps over a channel region with an insulating film interposed therebetween and a gate electrode that overlaps under the channel region with an insulating film interposed therebetween.
[0096]
Further, with the use of the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom of shapes of electrodes, wirings, and the like of elements other than TFTs formed using a gate metal.
[0097]
(Embodiment 2)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention which is different from that in Embodiment 1 will be described with reference to FIGS. Note that the example of the manufacturing process described in Embodiment 2 is equivalent to the example illustrated in FIG. 1C in means for solving the problem.
[0098]
In FIG. 3A, as a substrate 201, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate over which an insulating film is formed is used. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature in this manufacturing step may be used. In this embodiment mode, a substrate 201 made of glass such as barium borosilicate glass or aluminoborosilicate glass is used. Next, a base film (not shown) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 201. The base film may have a single-layer structure of the insulating film or a structure in which two or more insulating films are stacked. In this embodiment mode, as a first layer of a base film, a SiH ₄ , NH ₃ , And N ₂ A silicon nitride oxide film formed with O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, the silicon nitride oxide film is formed to a thickness of 50 nm. Next, as a second layer of the base film, SiH ₄ And N ₂ A silicon oxynitride film is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using O as a reaction gas. In this embodiment, the silicon oxynitride film is formed to a thickness of 100 nm.
[0099]
Subsequently, a semiconductor film is formed over the base film. The semiconductor film is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (sputtering, LPCVD, plasma CVD, or the like). Next, the semiconductor film is crystallized using a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization, or the like). Note that a thermal crystallization method using a metal element that promotes crystallization and a laser crystallization method may be combined. For example, after performing a thermal crystallization method using a metal element that promotes crystallization, a laser crystallization method may be performed.
[0100]
Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers (semiconductor active layers) 202a to 202e. Note that as the semiconductor layer, an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film, or the like can be used. In this embodiment mode, an amorphous silicon film with a thickness of 55 nm is formed by a plasma CVD method. Then, a solution containing nickel is held on the amorphous silicon film, and after the amorphous silicon film is dehydrogenated (500 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours) is performed. Line to form a crystalline silicon film. Thereafter, island-shaped semiconductor layers 202a to 202e are formed by a patterning process using a photolithography method.
[0101]
Note that when a crystalline semiconductor film is formed by a laser crystallization method, a continuous wave or pulsed gas laser or a solid laser may be used. As the former gas laser, excimer laser, YAG laser, YVO ₄ Laser, YLF laser, YAlO ₃ Laser, glass laser, ruby laser, Ti: sapphire laser, or the like can be used. The latter solid-state laser includes YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti or Tm. ₄ , YLF, YAlO ₃ A laser using a crystal such as the above can be used. The fundamental wave of the laser depends on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. Harmonics with respect to the fundamental wave can be obtained by using a nonlinear optical element. Note that in order to obtain a crystal with a large grain size during crystallization of the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and apply the second to fourth harmonics of a fundamental wave. . Typically, Nd: YVO ₄ A second harmonic (532 nm) or a third harmonic (355 nm) of a laser (a fundamental wave of 1064 nm) is applied.
[0102]
In addition, a continuous oscillation YVO with an output of 10 W ₄ Laser light emitted from the laser is converted into harmonics by a nonlinear optical element. Furthermore, YVO is placed in the resonator. ₄ There is also a method of emitting a harmonic by putting a crystal and a nonlinear optical element. Then, the laser light is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser beam is irradiated on the object to be processed. The energy density at this time is 0.01 to 100 MW / cm ² Degree (preferably 0.1 to 10 MW / cm ² )is necessary. Then, irradiation is performed by moving the semiconductor film relatively to the laser light at a speed of about 10 to 2000 cm / s.
[0103]
In the case of using the above laser, it is preferable that a laser beam emitted from a laser oscillator be linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are set as appropriate. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 700 mJ / cm. ² (Typically 200 to 300 mJ / cm ² ). When a YAG laser is used, the second harmonic is used to set the pulse oscillation frequency to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ / cm. ² (Typically 350-500 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm (preferably 400 μm) is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 50 to 98% Is also good.
[0104]
However, in the present embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and heat treatment (such as RTA method or thermal annealing using a furnace annealing furnace) is performed. After the metal element is diffused, the amorphous silicon film is removed by etching after the heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed.
[0105]
After the island-shaped semiconductor layers 202a to 202e are formed, a small amount of impurity element (boron or phosphorus) may be doped. In this manner, the threshold value of the TFT can be controlled by adding a small amount of an impurity element to a region to be a channel region.
[0106]
Next, a gate insulating film 203 which covers the semiconductor layers 202a to 202e is formed. The gate insulating film 203 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed to a thickness of 115 nm by a plasma CVD method as the gate insulating film 203. Needless to say, the gate insulating film 203 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. Note that in the case where a silicon oxide film is used as the gate insulating film 203, TEOS (Tetraethyl Orthosilicate) and O ₂ At a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm. ² And may be formed by discharging. Good characteristics as the gate insulating film 203 can be obtained by subsequently performing thermal annealing at 400 to 500 ° C. on the silicon oxide film formed by the above steps.
[0107]
Here, a specific region of the semiconductor layers 202a to 202e may be doped with an impurity element before manufacturing the gate electrode. A Lov region or the like can be formed by forming a gate electrode so as to overlap with the impurity region formed at this time. Note that when the semiconductor layers 202a to 202e are doped with an impurity element, an insulating film (denoted as a doping insulating film) other than the gate insulating film 203 may be formed. In this case, after the doping process is completed, the insulating film for doping is removed.
[0108]
Next, a first conductive film 204a is formed of TaN to a thickness of 20 to 100 nm, and a second conductive film 204b is formed of W to a thickness of 100 to 400 nm. In this embodiment mode, a first conductive film 204a made of a TaN film with a thickness of 30 nm and a second conductive film 204b made of a W film with a thickness of 370 nm are stacked. In this embodiment, the TaN film serving as the first conductive film 204a is formed by a sputtering method in a nitrogen-containing atmosphere using a Ta target. The W film serving as the second conductive film 204b is formed by a sputtering method using a W target. In addition, tungsten hexafluoride (WF ₆ ) Can be formed by a thermal CVD method. In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains a large amount of impurity elements such as oxygen, crystallization is inhibited and the resistance is increased. Therefore, in this embodiment mode, the W film is formed by a sputtering method using a high-purity W (purity: 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.
[0109]
Note that in this embodiment mode, the first conductive film 204a is a TaN film and the second conductive film 204b is a W film; however, the materials forming the first conductive film 204a and the second conductive film 204b are not particularly limited. Not done. The first conductive film 204a and the second conductive film 204b are made of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. It may be formed. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used.
[0110]
Next, a resist 205 is formed. As a method for forming the resist 205, a coating method can be used. Note that a spin coater or a roll coater may be used for the coating method. The resist 205 can be either a positive type or a negative type, and can be selected according to a light source used at the time of exposure.
[0111]
Next, the resist 205 is exposed (first exposure) to form resist masks 209, 210, 211, and 285, and a first etching process (gate metal etching 1) for manufacturing a gate electrode is performed (FIG. 3 (B)). The first etching process is performed under the first and second etching conditions. In this embodiment, as a first etching condition, an inductively coupled plasma (ICP) etching method is used, and CF is used as an etching gas. ₄ And Cl ₂ And O ₂ And a gas flow ratio of 25:25:10 (sccm), a 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.0 Pa to generate plasma, and etching is performed. I do. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Then, the W film is etched under the first etching condition to make the end of the second conductive layer 204b tapered. Subsequently, the etching conditions were changed to the second etching condition without removing the resist masks 209, 210, and 211, and CF gas was used as an etching gas. ₄ And Cl ₂ And a gas flow ratio of 30:30 (sccm), 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1.0 Pa to generate plasma for about 15 seconds. Is etched. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition, the first conductive layer 204a and the second conductive layer 204b are etched to the same degree. Note that in order to perform etching without leaving a residue on the gate insulating film 203, the etching time may be increased by about 10 to 20%. In the above first etching treatment, the end of the first conductive layer 204a and the end of the second conductive layer 204b are formed by adjusting the shape of the resist mask to an appropriate value, by the effect of the bias voltage applied to the substrate side. It has a tapered shape. Thus, the first shape conductive layers 206, 207, and 208 (the first conductive layers 206a, 207a, and 208a, and the second conductive layers 206b, 207b, and 208b) are formed by the first etching process. In the gate insulating film 203, the exposed region is etched by about 20 to 50 nm and becomes thin.
[0112]
Next, as shown in FIG. 3C, a second etching process (gate metal etching 2) is performed without removing the resist masks 209, 210, 211, 285. In the second etching process, SF is used as the etching gas. ₆ And Cl ₂ And O ₂ And the gas flow ratio was set to 24:12:24 (sccm), and RF (13.56 MHz) power of 700 W was applied to the coil side power at a pressure of 1.3 Pa to generate plasma for 25 seconds. Etching is performed to a degree. A 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. Thus, the W film is selectively etched to form second shape conductive layers 212 to 214 (first conductive layers 212a to 214a, second conductive layers 212b to 214b). At this time, the first conductive layers 206a to 208a are hardly etched. Further, since the portions of the first conductive film 204a and the second conductive film 204b formed over the semiconductor layers 202d and 202e are covered with the resist mask 285, the first etching process and the second etching process are performed. Through and not etched.
[0113]
Then, a first doping process (doping 1) is performed without removing the resist masks 209, 210, and 211, and an N-type impurity element is added to the semiconductor layers 202a to 202c at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are as follows: ^Thirteen ~ 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 40 to 80 kV. In this embodiment, the dose is 5.0 × 10 ^Thirteen atoms / cm ² And the acceleration voltage is set to 50 kV. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically, phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used. In this case, the first impurity regions 218a, 218b, 219a, 219b, 220a, and 220b are formed in a self-aligned manner using the second shape conductive layers 212 to 214 as a mask for an impurity element imparting N-type. The first impurity regions 218a, 218b, 219a, 219b, 220a, and 220b have 1 × 10 ¹⁸ ~ 1 × 10 ²⁰ atoms / cm ³ Is added in the concentration range of N.
[0114]
Subsequently, as shown in FIG. 3D, after removing the resist masks 209, 210, 211, 285, new resist masks 221, 239, 240 are formed. The second doping process (doping 2) is performed at an acceleration voltage higher than that of the first doping process. The conditions of the ion doping method are as follows: ^Thirteen ~ 3 × 10 ^Fifteen atoms / cm ² And an acceleration voltage of 60 to 120 kV. In the present embodiment, the dose is 3.0 × 10 ^Fifteen atoms / cm ² And the acceleration voltage is set to 65 kV. In the second doping treatment, the second conductive layer 213b is used as a mask for an impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. Here, at the time of the second doping process, a resist mask 239 is formed so as to cover the semiconductor layer 202c to be a P-channel TFT. Note that the resist mask 240 is not always necessary.
[0115]
As a result of performing the above-described second doping process, the second impurity regions (Lov regions) 225a and 225b overlapping with the first conductive layer 213a have 1 × 10 ¹⁸ ~ 5 × 10 ¹⁹ atoms / cm ³ Is added in the concentration range of. The third impurity regions 222a, 222b, 224a, and 224b have 1 × 10 ¹⁹ ~ 5 × 10 ²¹ atoms / cm ³ Is added in the concentration range of. Among the first impurity regions 218a and 218b formed by the first doping process, the regions 223a and 223b covered with the resist 221 in the second doping process exist. Call it.
[0116]
Note that in this embodiment, the second impurity regions 225a and 225b and the third impurity regions 222a, 222b, 224a, and 224b are formed only by the second doping treatment; however, the present invention is not limited to this. The doping process may be performed by appropriately changing the conditions for the doping process, and may be performed by a plurality of doping processes.
[0117]
Next, as shown in FIG. 3E, after removing the resist masks 221, 239, and 240, a new resist 286 is formed. As a method for forming the resist 286, a coating method can be used. Note that a spin coater or a roll coater may be used for the coating method. The resist 286 can be either a positive type or a negative type, and can be selected according to the light source used at the time of exposure. Note that the resist 286 may be the same material as the resist 205 used in the first exposure, or may be different.
[0118]
Next, the resist 286 is exposed (second exposure) to form resist masks 230, 231, and 287 (FIG. 3F). Note that the exposure means in the second exposure may be the same as or different from the first exposure. Thus, a third etching process (gate metal etching 3) is performed. In this way, third shape conductive layers 228 and 229 (first conductive layers 228a and 229a and second conductive layers 228b and 229b) having substantially vertical ends are formed. Note that the second shape conductive layers 212, 213, and 214 (first conductive layers 212a, 213a, 214a, and second conductive layers 212b, 213b, and 214b) formed over the semiconductor layers 202a, 202b, and 202c are formed. The portion is not etched because it is covered with the resist mask 287.
[0119]
After that, a third doping process (doping 3) is performed. In the third doping treatment, an impurity element imparting N-type is added. The doping may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are as follows: ^Thirteen ~ 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 60 to 100 kV. An element belonging to Group XV, typically phosphorus (P) or arsenic (As) is used as the impurity element imparting the N-type. Here, phosphorus (P) is used. In this case, the fourth impurity regions 232a, 232b, 233a, and 233b are formed using the resist masks 230, 231, and 287 as masks for the impurity element imparting N-type. The fourth impurity regions 232a, 232b, 233a, and 233b have 1 × 10 ²⁰ ~ 1 × 10 ²¹ atoms / cm ³ Is added within the concentration range of. Note that since the semiconductor layers 202a to 202c are covered with the resist mask 287, no impurity element is added in the third doping treatment.
[0120]
Next, as shown in FIG. 3G, a fourth doping process (doping 4) is performed. In the fourth doping process, an impurity element imparting P-type is added. The doping may be performed by an ion doping method or an ion implantation method. Fifth impurity regions 235a, 235b, 238a, 238b and sixth impurity regions 236a, 236b to which a P-type impurity element is added are formed in the island-shaped semiconductor layers 202c and 202e forming a P-channel TFT. At this time, the second shape conductive layer 214b and the third shape conductive layer 229 are used as masks for impurity elements, and impurity regions are formed in a self-aligned manner. In this embodiment, diborane (B ₂ H ₆ ) Is used. The conditions of the ion doping method are as follows: ¹⁶ atoms / cm ² And the acceleration voltage is 80 kV. In this manner, the P-type impurity element can be added to the regions 236a and 236b of the semiconductor active layer that overlap with the second shape conductive layer 214a via the second shape conductive layer 214a. Here, the concentration of the P-type impurity element added to the sixth impurity regions 236a and 236b may be lower than the concentration of the P-type impurity element added to the fifth impurity regions 235a and 235b. it can. At the time of the fourth doping process, the entire surface of the island-shaped semiconductor layers 202a, 202b, and 202d forming the N-channel TFT is covered with resist masks 234 and 237. Note that phosphorus is added at different concentrations to the fifth impurity regions 235a, 235b, 238a, and 238b by the first doping process, the second doping process, and the third doping process. By applying the element to be applied at a high concentration, the fifth impurity regions 235a, 235b, 238a, and 238b function as a source region and a drain region of the P-channel TFT without any problem.
[0121]
Through the above steps, impurity regions are formed in the respective semiconductor layers 202a to 202e. The second shape conductive layers 212, 213, and 214 overlapping the island-shaped semiconductor layer and the third shape conductive layers 228 and 229 function as gate electrodes.
[0122]
Thus, as shown in FIG. 3H, an N-channel TFT 61, an N-channel TFT 62, a P-channel TFT 63, an N-channel TFT 64, and a P-channel TFT 65 are formed.
[0123]
The N-channel TFT 61 includes a channel region 292, high-concentration impurity regions 222a and 222b corresponding to a source region and a drain region, and low-concentration impurity regions (Loff regions) 223a and 223b which do not overlap with a gate electrode. The N-channel TFT 62 includes a channel region 293, high-concentration impurity regions 224a and 224b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 225a and 225b overlapping with a gate electrode. On the other hand, the P-channel TFT 63 has a channel region 294, high-concentration impurity regions 235a and 235b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 236a and 236b overlapping with the gate electrode. The gate electrodes of the N-channel TFT 61, the N-channel TFT 62, and the P-channel TFT 63 have tapered ends. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode. However, since the Lov region and the Loff region can be manufactured in a self-aligned manner in the manufacturing process of the gate electrode, the number of steps in manufacturing the TFT can be reduced. Thus, a TFT with high withstand voltage can be formed by reducing the number of steps.
[0124]
The N-channel TFT 64 has a channel region 295, and high-concentration impurity regions 232a and 232b corresponding to a source region and a drain region. The P-channel TFT 65 has a channel region 296 and high-concentration impurity regions 238a and 238b corresponding to a source region and a drain region. The N-channel TFT 64 and the P-channel TFT 65 have a single drain structure. When the N-channel TFT 64 and the P-channel TFT 65 are TFTs having a Lov region or a Loff region, a new mask is required and the number of steps increases. However, since the end of the gate electrode is etched vertically, miniaturization is possible.
[0125]
Note that the exposure means in manufacturing the gate electrodes of the N-channel TFT 61, the N-channel TFT 62, the P-channel TFT 63, the N-channel TFT 64, and the P-channel TFT 65 is the same as that in Embodiment 1, Description is omitted.
[0126]
For example, a circuit that requires a withstand voltage is manufactured by using an N-channel TFT 61, an N-channel TFT 62, and a P-channel TFT 63, and a circuit that requires miniaturization is manufactured by using an N-channel TFT 64 and a P-channel TFT 65. be able to. At this time, the exposure means in manufacturing the gate electrode of each TFT can be the same as that in Embodiment 1.
[0127]
Note that in this embodiment, a manufacturing process of a single-gate TFT is described; however, a double-gate structure or a multi-gate structure having more gates may be used. In this embodiment mode, a top gate type TFT is described, and a manufacturing process thereof is described. However, the method for manufacturing a semiconductor device of the present invention can be applied to a dual-gate TFT.
[0128]
Further, with the use of the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom of shapes of electrodes, wirings, and the like of elements other than TFTs formed using a gate metal.
(Embodiment 3)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention which is different from Embodiments 1 and 2 will be described with reference to FIGS. Note that the example of the manufacturing process described in Embodiment 3 corresponds to the example illustrated in FIG. 1B for solving the problem. Steps up to gate metal etching 2 are the same as those described with reference to FIG. 3 in the second embodiment, and thus the same portions are denoted by the same reference numerals and description thereof will be omitted.
[0129]
In accordance with the steps of Embodiment Mode 2, the structure up to FIG. Next, as shown in FIG. 4D, the resist masks 209 to 211 and 285 are removed, a new resist film is formed and exposed (second exposure), and resist masks 330, 331, and 388 are formed. Note that the exposure means in the second exposure may be the same as or different from the first exposure. Thus, a third etching process (gate metal etching 3) is performed. Thus, third-shaped conductive layers 328 and 329 (first conductive layers 328a and 329a and second conductive layers 328b and 329b) having substantially vertical ends are formed. Note that the second shape conductive layers 212, 213, and 214 (first conductive layers 212a, 213a, 214a, and second conductive layers 212b, 213b, and 214b) formed over the semiconductor layers 202a, 202b, and 202c are formed. Since the portion is covered with the resist mask 388, it is not etched.
[0130]
After that, as shown in FIG. 4E, after removing the resist masks 330, 331, and 388, a first doping process (doping 1) is performed, and the semiconductor layers 202a to 202e are doped with an impurity element imparting N-type. Add to low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are as follows: ^Thirteen ~ 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 40 to 80 kV. In this embodiment, the dose is 5.0 × 10 ^Thirteen atoms / cm ² And the acceleration voltage is set to 50 kV. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically, phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used. In this case, the second shape conductive layers 212 to 214 and the third shape conductive layers 328 and 329 are used as masks for an impurity element imparting N-type, and the first impurity regions 318a, 318b, and 319a are self-aligned. , 319b, 320a, 320b, 1220a, 1220b, 1221a, and 1221b. The first impurity regions 318a, 318b, 319a, 319b, 320a, 320b, 1220a, 1220b, 1221a, and 1221b have 1 × 10 ¹⁸ ~ 1 × 10 ²⁰ atoms / cm ³ Is added in the concentration range of N.
[0131]
Subsequently, as shown in FIG. 4F, new resist masks 321, 327, and 333 are formed. The second doping process (doping 2) is performed at an acceleration voltage higher than that of the first doping process. The conditions of the ion doping method are as follows: ^Thirteen ~ 3 × 10 ^Fifteen atoms / cm ² And an acceleration voltage of 60 to 120 kV. In the present embodiment, the dose is 3.0 × 10 ^Fifteen atoms / cm ² And an acceleration voltage of 65 kV. In the second doping treatment, the second shape conductive layer 213b and the third shape conductive layer 328 are used as masks for the impurity element, and the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. Doping to be performed. Note that at the time of the second doping process, resist masks 327 and 333 are formed so as to cover the semiconductor layers 202c and 202e to be P-channel TFTs.
[0132]
As a result of performing the above-described second doping process, the second impurity regions 325a and 325b overlapping with the first conductive layer 213a have 1 × 10 ¹⁸ ~ 5 × 10 ¹⁹ atoms / cm ³ Is added in the concentration range of. The third impurity regions 322a, 322b, 324a, 324b, 332a, and 332b have 1 × 10 ¹⁹ ~ 5 × 10 ²¹ atoms / cm ³ Is added in the concentration range of. Among the first impurity regions 318a and 318b formed by the first doping process, the regions 323a and 323b covered with the resist 321 in the second doping process exist. Call it.
[0133]
In this embodiment mode, the second impurity regions 325a and 325b and the third impurity regions 322a, 322b, 324a, 324b, 332a, and 332b are formed only by the second doping process; however, the present invention is not limited to this. The doping process may be performed by appropriately changing the conditions for the doping process, and may be performed by a plurality of doping processes.
[0134]
Next, as shown in FIG. 4G, after removing the resist masks 321, 327, and 333, new resist masks 334 and 337 are formed. Next, a third doping process (doping 3) is performed. In the third doping treatment, an impurity element imparting a P-type is added. The doping may be performed by an ion doping method or an ion implantation method. Fourth impurity regions 335a, 335b, 338a, 338b and fifth impurity regions 336a, 336b to which P-type impurity elements are added are formed in the island-shaped semiconductor layers 202c and 202e forming the P-channel TFT. At this time, the second shape conductive layer 214b and the third shape conductive layer 329 are used as masks for impurity elements, and impurity regions are formed in a self-aligned manner. In this embodiment, diborane (B ₂ H ₆ ) Is used. The conditions of the ion doping method are as follows: ¹⁶ atoms / cm ² And the acceleration voltage is 80 kV. Thus, the P-type impurity element can also be added to the regions 336a and 336b of the semiconductor active layer overlapping the second shape conductive layer 214a via the second shape conductive layer 214a. Here, the concentration of the P-type impurity element added to the fifth impurity regions 336a and 336b may be lower than the concentration of the P-type impurity element added to the fourth impurity regions 335a and 335b. it can. At the time of the third doping process, the entire surface of the island-shaped semiconductor layers 202a, 202b, and 202d forming the N-channel TFT is covered with resist masks 334 and 337. Note that phosphorus is added to the fourth impurity regions 335a, 335b, 338a, and 338b by the first doping process, the second doping process, and the third doping process. By applying the impurity at a high concentration, the fourth impurity regions 335a, 335b, 338a, and 338b function as a source region and a drain region of the P-channel TFT without any problem.
[0135]
Through the above steps, impurity regions are formed in the respective semiconductor layers 202a to 202e. The second-shaped conductive layers 212, 213, and 214 overlapping the island-shaped semiconductor layer and the third-shaped conductive layers 328 and 329 function as gate electrodes.
[0136]
Thus, as shown in FIG. 4H, an N-channel TFT 361, an N-channel TFT 362, a P-channel TFT 363, an N-channel TFT 364, and a P-channel TFT 365 are formed.
[0137]
The N-channel TFT 361 includes a channel region 392, high-concentration impurity regions 322a and 322b corresponding to a source region and a drain region, and low-concentration impurity regions (Loff regions) 323a and 323b which do not overlap with a gate electrode. The N-channel TFT 362 includes a channel region 393, high-concentration impurity regions 324a and 324b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 325a and 325b overlapping with a gate electrode. On the other hand, the P-channel TFT 363 has a channel region 394, high-concentration impurity regions 335a and 335b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 336a and 336b overlapping with the gate electrode. The gate electrodes of the N-channel TFT 361, the N-channel TFT 362, and the P-channel TFT 363 have tapered ends. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode. However, since the Lov region and the Loff region can be manufactured in a self-aligned manner in the manufacturing process of the gate electrode, the number of steps in manufacturing the TFT can be reduced. Thus, a TFT with high withstand voltage can be formed by reducing the number of steps.
[0138]
Further, the N-channel TFT 364 has a channel region 395 and high-concentration impurity regions 332a and 332b corresponding to a source region and a drain region. The P-channel TFT 365 has a channel region 396 and high-concentration impurity regions 338a and 338b corresponding to a source region and a drain region. The N-channel TFT 364 and the P-channel TFT 365 have a single drain structure. The N-channel TFT 364 and the P-channel TFT 365 have a problem that a new mask is required when forming a Lov region or a Loff region, and the number of steps increases. However, since the gate electrode is manufactured using a process in which an end portion of the gate electrode may be vertically etched, miniaturization is possible.
[0139]
In the third embodiment, in the step shown in FIG. 4F, a resist mask covering only the third shape conductive layer 328 and a peripheral portion of the third shape conductive layer 328 is replaced with the resist mask 321. , 327, and 333, it is also possible to form a Loff region in the N-channel TFT 364 without increasing the number of steps.
[0140]
Note that the exposure means in manufacturing the gate electrodes of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 is the same as that in Embodiment 1; Description is omitted.
[0141]
For example, a circuit requiring high withstand voltage is manufactured using the N-channel TFT 361, the N-channel TFT 362, and the P-channel TFT 363, and a circuit requiring miniaturization is manufactured using the N-channel TFT 364 and the P-channel TFT 365. be able to. At this time, the exposure means in manufacturing the gate electrode of each TFT can be the same as that in Embodiment 1.
[0142]
Note that in this embodiment, a manufacturing process of a single-gate TFT is described; however, a double-gate structure or a multi-gate structure having more gates may be used. In this embodiment mode, a top gate type TFT is described, and a manufacturing process thereof is described. However, the method for manufacturing a semiconductor device of the present invention can be applied to a dual-gate TFT.
[0143]
Further, with the use of the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom of shapes of electrodes, wirings, and the like of elements other than TFTs formed using a gate metal.
[0144]
(Embodiment 4)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention which is different from Embodiments 1 to 3 will be described with reference to FIGS. Note that the example of the manufacturing process described in Embodiment 4 corresponds to the example shown in FIG. 1B for solving the problem. The steps up to gate metal etching 3 are the same as those described with reference to FIG. 4 in the third embodiment, and a description thereof will not be repeated.
[0145]
According to the steps of Embodiment Mode 3, the structure up to FIG. Next, as shown in FIG. 25E, the resist masks 330, 331, and 388 are removed, and a new resist mask 8000 is formed. The semiconductor layer 202e to be a P-channel TFT is covered with the resist mask 8000. A first doping process (doping 1) is performed to add an N-type impurity element to the semiconductor layers 202a to 202d at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically, phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used. In this case, the first conductive regions 8318a, 8318b, 8319a, 8319b, 8320a, and 8320b are used as masks for the second-shaped conductive layers 212 to 214 and the third-shaped conductive layer 328 for an impurity element imparting N-type conductivity. , 8220a and 8220b. To the first impurity regions 8318a, 8318b, 8319a, 8319b, 8320a, 8320b, 8220a, and 8220b, an impurity element imparting N-type is added.
[0146]
Subsequently, as shown in FIG. 25F, after removing the resist mask 8000, new resist masks 9101 and 9102 are formed. A second doping process (doping 2) is performed, and a low-concentration impurity element imparting p-type is added to the semiconductor layer 202e. The second doping treatment may be performed by an ion doping method or an ion implantation method. In this embodiment, diborane (B ₂ H ₆ ) Is used. In this manner, the second impurity regions 8221a and 8221b are formed as a mask in which the third shape conductive layer 329 gives a P-type. A P-type impurity element is added to the second impurity regions 8221a and 8221b.
[0147]
Next, as shown in FIG. 25G, after removing the resist masks 9101 and 9102, resist masks 9321, 9327, 9003, and 9333 are formed. After that, a third doping process (doping 3) for adding an impurity element imparting N-type is performed. The third doping process (doping 3) is performed at a higher acceleration voltage than the first doping process. In the third doping treatment, the second shape conductive layer 213b is used as a mask for an impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. Note that at the time of the third doping process, resist masks 9327 and 9333 are formed so as to cover the semiconductor layers 202c and 202e to be P-channel TFTs. Further, a resist mask 9321 is formed so as to cover part of the first impurity regions 8318a and 8318b and the conductive layer 212 in the second shape. A resist mask 9003 is formed so as to cover part of the first impurity regions 8220a and 8220b and the third shape conductive layer 328. An N-type impurity element is added to the first impurity regions 8318a and 8318b which are not covered with the resist mask 9321 and the first impurity regions 8220a and 8220b which are not covered with the resist mask 9003 by a third doping step. . Note that among the first impurity regions 8318a, 8318b, 8220a, and 8220b, regions 9323a, 9323b, 9004a, and 9004b that were covered with the resists 9321 and 9003 in the third doping treatment exist. It is called an area. The conditions (acceleration voltage) of the third doping process are set so that an impurity element imparting N-type is also added to a lower portion of the second shape conductive layer 213a which does not overlap with the second shape conductive layer 213b. Etc.). The concentration of the impurity element added via the second shape conductive layer 213a can be lower than the concentration of the impurity element added without passing through the second shape conductive layer 213a. Thus, the third impurity regions 9322a, 9322b, 9324a, 9324b, 9332a, and 9332b to which the impurity element imparting the N-type is added at a high concentration, and 9323a to which the impurity element imparting the N-type at a low concentration is added, 9323b, 9325a, 9325b, 9004a, and 9004b are formed.
[0148]
Next, as shown in FIG. 25H, after removing the resist masks 9321, 9327, 9003, and 9333, resist masks 9334, 9337, and 9005 are formed. After that, a fourth doping process (doping 4) for adding an impurity element imparting a P-type is performed. The fourth doping process (doping 4) is performed at a higher acceleration voltage than the second doping process. In the fourth doping treatment, the second shape conductive layer 214b is used as a mask for an impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 214a. Note that at the time of the fourth doping process, resist masks 9334 and 9337 are formed so as to cover the semiconductor layers 202a, 202b, and 202d to be N-channel TFTs. Further, a resist mask 9005 is formed so as to cover part of the second impurity regions 8221a and 8221b and the third-shaped conductive layer 329. A P-type impurity element is added to the second impurity regions 8221a and 8221b which are not covered with the resist mask 9005 by a fourth doping step. Note that among the second impurity regions 8221a and 8221b, there are regions 9006a and 9006b which have been covered with the resist 9005 in the fourth doping process, which are referred to as second impurity regions. The conditions (acceleration voltage) of the fourth doping process are such that an impurity element imparting P-type is also added to a lower portion of the second shape conductive layer 214a which does not overlap with the second shape conductive layer 214b. Etc.). The concentration of the impurity element added through the second shape conductive layer 214a can be lower than the concentration of the impurity element added without passing through the second shape conductive layer 214a. Thus, the fourth impurity regions 9335a, 9335b, 9338a, and 9338b to which the impurity element imparting the P-type is added at a high concentration, and the 9336a, 9336b, and 9006a to which the impurity element imparting the P-type at a low concentration are added. Form 9006b.
[0149]
Note that although phosphorus is added to the fourth impurity regions 9335a and 9335b by the first doping process, the fourth impurity regions 9335a and 9335b can be formed by adding a P-type element at a high concentration. Functions as a source region and a drain region of a P-channel TFT without any problem.
[0150]
Through the above steps, impurity regions are formed in the respective semiconductor layers 202a to 202e. The second-shaped conductive layers 212, 213, and 214 overlapping the island-shaped semiconductor layer and the third-shaped conductive layers 328 and 329 function as gate electrodes.
[0151]
Thus, as shown in FIG. 25I, an N-channel TFT 9361, an N-channel TFT 9362, a P-channel TFT 9363, an N-channel TFT 9364, and a P-channel TFT 9365 are formed.
[0152]
The N-channel TFT 9361 includes a channel region 9392, high-concentration impurity regions 9322a and 9322b corresponding to source and drain regions, and low-concentration impurity regions (Loff regions) 9323a and 9323b which do not overlap with a gate electrode. The N-channel TFT 9362 includes a channel region 9393, high-concentration impurity regions 9324a and 9324b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 9325a and 9325b overlapping with the gate electrode. On the other hand, the P-channel TFT 9363 includes a channel region 9394, high-concentration impurity regions 9335a and 9335b corresponding to a source region and a drain region, and low-concentration impurity regions (Lov regions) 9336a and 9336b overlapping with the gate electrode. The gate electrodes of the N-channel TFT 9361, the N-channel TFT 9362, and the P-channel TFT 9363 have tapered ends. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode.
[0153]
The N-channel TFT 9364 includes a channel region 9395 and high-concentration impurity regions 9332a and 9332b corresponding to a source region and a drain region. Further, low concentration impurity regions (Loff regions) 9004a and 9004b which do not overlap with the gate electrode are provided. The P-channel TFT 9365 has a channel region 9396 and high-concentration impurity regions 9338a and 9338b corresponding to a source region and a drain region. In addition, low concentration impurity regions (Loff regions) 9006a and 9006b which do not overlap with the gate electrode are provided. In this embodiment mode, a process of forming a Loff region also in the N-channel TFT 9364 and the P-channel TFT 9365 is described.
[0154]
Exposure means for manufacturing the gate electrodes of the N-channel TFT 9361, the N-channel TFT 9362, the P-channel TFT 9363, the N-channel TFT 9364, and the P-channel TFT 9365 are the same as those in Embodiment Mode 1, and therefore will not be described here. Omitted.
[0155]
Note that in this embodiment, a manufacturing process of a single-gate TFT is described; however, a double-gate structure or a multi-gate structure having more gates may be used. In this embodiment mode, a top gate type TFT is described, and a manufacturing process thereof is described. However, the method for manufacturing a semiconductor device of the present invention can be applied to a dual-gate TFT.
[0156]
Further, with the use of the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom of shapes of electrodes, wirings, and the like of elements other than TFTs formed using a gate metal.
[0157]
(Embodiment 5)
In this embodiment, an example of a method for manufacturing a semiconductor device of the present invention which is different from Embodiments 1 to 4 will be described with reference to FIGS. Note that the example of the manufacturing process described in Embodiment 5 is equivalent to the example illustrated in FIG. 1B for solving the problem. Steps up to gate metal etching 3 are the same as those described with reference to FIG. 25 in the fourth embodiment, and a description thereof will not be repeated.
[0158]
According to the steps of Embodiment Mode 4, the structure up to FIG. Next, as shown in FIG. 26E, the resist masks 330, 331, and 388 are removed, and a new resist mask 8000 is formed. The semiconductor layer 202e to be a P-channel TFT is covered with the resist mask 8000. A first doping process (doping 1) is performed to add an N-type impurity element to the semiconductor layers 202a to 202d at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically, phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used. In this case, the first conductive regions 8318a, 8318b, 8319a, 8319b, 8320a, and 8320b are used as masks for the second-shaped conductive layers 212 to 214 and the third-shaped conductive layer 328 for an impurity element imparting N-type conductivity. , 8220a and 8220b.
[0159]
Next, as shown in FIG. 26F, the resist mask 8000 is removed, and new resist masks 8001 and 8002 are formed. The semiconductor layer 202c to be a P-channel TFT, the semiconductor layer 202d to be an N-channel TFT, and the semiconductor layer 202e to be a P-channel TFT are covered with a resist mask 8002. In addition, the resist mask 8001 covers portions 8323a and 8323b of the first impurity regions 8318a and 8318b. A second doping process (doping 2) is performed, and an N-type impurity element is added to the semiconductor layers 202a and 202b at a low concentration. The second doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically, phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used. In this case, second impurity regions 8322a, 8322b, 8324a, and 8324b are formed using the second shape conductive layer 213b as a mask for an impurity element imparting N-type. Note that although the regions 8323a and 8323b covered with the resist mask 8001 exist in the second doping process, they are referred to as first impurity regions. In addition, the conditions (acceleration voltage) of the second doping process are set so that an impurity element imparting N-type is also added to a lower portion of the second shape conductive layer 213a which does not overlap with the second shape conductive layer 213b. Etc.). Note that the concentration of the impurity element added through the second shape conductive layer 213a can be lower than the concentration of the impurity element added without passing through the second shape conductive layer 213a. Thus, the second impurity regions 8322a, 8322b, 8324a, and 8324b to which an impurity element that imparts N-type is added at a high concentration and the first impurity region 8323a to which impurity elements that impart N-type are added at a low concentration are added. , 8323b and third impurity regions 8325a, 8325b are formed.
[0160]
Next, as shown in FIG. 26G, the resist masks 8001 and 8002 are removed, and new resist masks 8003 and 8004 are formed. A semiconductor layer 202a to be an N-channel TFT and a semiconductor layer 202b to be an N-channel TFT are covered with a resist mask 8003, and a semiconductor layer 202d to be an N-channel TFT is covered with a resist mask 8004. A third doping process (doping 3) is performed, and an impurity element imparting p-type is added to the semiconductor layers 202c and 202e. The second doping treatment may be performed by an ion doping method or an ion implantation method. In this embodiment, diborane (B ₂ H ₆ ) Is used. Thus, fourth impurity regions 8335a, 8335b, 8332a, and 8332b to which the impurity element imparting P-type is added are formed. Note that an impurity element imparting N-type is added to the fourth impurity regions 8335a and 8335b by the first doping process, but the amount of the impurity element imparting P-type in the third doping process is added. Can function as a P-type impurity region without any problem. Note that a resist mask which covers the semiconductor layer 202c in the first doping treatment can be provided so that an N-type impurity element is not added to a region to be the fourth impurity regions 8335a and 8335b.
[0161]
Next, as shown in FIG. 26H, the resist masks 8003 and 8004 are removed, and an insulating film 8005 is formed. As the insulating film 8005, a film with excellent coverage is preferably used. For example, silicon oxide can be used.
[0162]
Next, as shown in FIG. 26I, the insulating film 8003 is anisotropically etched to form sidewalls 8006a, 8006b, 8007a, 8007b, 8008a, 8008b, 8009a, 8009b, 8010a, and 8010b.
[0163]
Next, as shown in FIG. 26J, resist masks 8011 and 8012 are formed. The entire surfaces of the semiconductor layers 202a to 202c and 202e are covered with resist masks 8011 and 8012. After that, a fourth doping process for adding an impurity element imparting N-type is performed. The fourth doping treatment is performed using the third shape conductive layer 328 and the sidewalls 8009a and 8009b as a mask for an impurity element. An N-type impurity element is added to the first impurity regions 8220a and 8220b which are not covered with the resist masks 8011 and 8012 by a fourth doping step. Note that among the first impurity regions 8220a and 8220b, there are regions 8014a and 8014b which have been covered with the sidewalls 8009a and 8009b in the fourth doping treatment, which are referred to as first impurity regions. Thus, fifth impurity regions 8013a and 8013b to which an impurity element imparting N-type is added at a high concentration, and first impurity regions 8014a and 8014b to which impurity elements imparting N-type at a low concentration are added are formed. .
[0164]
Through the above steps, impurity regions are formed in the respective semiconductor layers 202a to 202e. The second-shaped conductive layers 212, 213, and 214 overlapping the island-shaped semiconductor layer and the third-shaped conductive layers 328 and 329 function as gate electrodes.
[0165]
Thus, as shown in FIG. 26K, an N-channel TFT 8361, an N-channel TFT 8362, a P-channel TFT 8363, an N-channel TFT 8364, and a P-channel TFT 8365 are formed.
[0166]
The N-channel TFT 8361 includes a channel region 8392, high-concentration impurity regions 8322a and 8322b corresponding to source and drain regions, and low-concentration impurity regions (Loff regions) 8323a and 8323b which do not overlap with a gate electrode. The N-channel TFT 8362 includes a channel region 8393, high-concentration impurity regions 8324a and 8324b corresponding to source and drain regions, and low-concentration impurity regions (Lov regions) 8325a and 8325b overlapping with the gate electrode. On the other hand, the P-channel TFT 8363 has a channel region 8394, and high-concentration impurity regions 8335a and 8335b corresponding to a source region and a drain region. The gate electrodes of the N-channel TFT 8361, the N-channel TFT 8362, and the P-channel TFT 8363 have tapered ends. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode.
[0167]
The N-channel TFT 8364 includes a channel region 8395, and high-concentration impurity regions 8013a and 8013b corresponding to a source region and a drain region. Further, the semiconductor device includes low-concentration impurity regions (Loff regions) 8014a and 8014b which do not overlap with the gate electrode. The P-channel TFT 8365 has a channel region 8396, and high-concentration impurity regions 8010a and 8010b corresponding to a source region and a drain region. In this embodiment mode, a step of forming a Loff region also in the N-channel TFT 8364 is described.
[0168]
Exposure means for manufacturing gate electrodes of the N-channel TFT 8361, the N-channel TFT 8362, the P-channel TFT 8363, the N-channel TFT 8364, and the P-channel TFT 8365 are the same as those in Embodiment Mode 1; Omitted.
[0169]
Note that in this embodiment, a manufacturing process of a single-gate TFT is described; however, a double-gate structure or a multi-gate structure having more gates may be used. In this embodiment mode, a top gate type TFT is described, and a manufacturing process thereof is described. However, the method for manufacturing a semiconductor device of the present invention can be applied to a dual-gate TFT.
[0170]
Further, with the use of the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom of shapes of electrodes, wirings, and the like of elements other than TFTs formed using a gate metal.
[0171]
(Embodiment 6)
In this embodiment, an example of a wiring formed using a gate metal in the manufacturing method described in Embodiments 1 to 5 will be described. 10 and 24 are used for the description.
[0172]
A step of etching the gate metal using the resist mask formed by the first exposure in the manufacturing method of Embodiments 1 to 5, and a step of etching the gate metal using the resist mask formed by the second exposure Focusing on the steps of etching, a method of smoothly connecting wirings formed in each step will be described. FIG. 10 is used for the description.
[0173]
FIG. 10A is a top view showing a resist mask 401 formed over the gate metal 400 by the first exposure. FIG. 10B illustrates a state in which the gate metal 400 is etched using the resist mask 401 in FIG. Note that FIG. 10B shows a state in which the gate metal is etched vertically along the edge of the resist mask 401. However, in the case of using the manufacturing method described in Embodiment Modes 1 to 5, the end portion of the wiring is tapered. The wiring 402 having the width L1 is formed by an etching process using the resist mask 401.
[0174]
Next, the resist mask 401 is removed, and a resist mask 403 is formed by second exposure. FIG. 10C is a top view illustrating a resist mask 403 formed by the second exposure. FIG. 10D illustrates a state where the gate metal 400 is etched using the resist mask 403 in FIG. The wiring 404 having a width L2 is formed by an etching process using the resist mask 401.
[0175]
Here, by increasing the resolution of the patterning of the second exposure higher than the resolution of the patterning of the first exposure, the wiring 402 and the wiring 404 are smoothly connected at the connection portion 405 as shown in FIG. can do. That is, the TFT in which the gate electrode is manufactured using the resist mask formed by the second exposure is made smaller than the TFT in which the gate electrode is manufactured using the resist mask formed by the first exposure. Shall be required. Thus, the wiring 402 and the wiring 404 can be connected smoothly as illustrated in FIG.
[0176]
Next, a cross-sectional view of a wiring formed using a gate metal in the manufacturing method described in Embodiments 1 to 5 is shown.
[0177]
FIG. 24A is a cross-sectional view of a wiring formed by etching a gate metal using a resist mask formed by the first exposure in the manufacturing methods of Embodiments 1 to 5. FIG. 24B is a cross-sectional view of a wiring formed by etching a gate metal using a resist mask formed by the second exposure in the manufacturing methods of Embodiments 1 to 5. Show. Each of the wirings 441a and 441b shown in FIG. 24A has a shape having a tapered end portion having a wiring width L1. The wires 441a and 441b are arranged at a wire interval S1. In addition, each of the wirings 442a and 442b illustrated in FIG. 24B has a shape having a substantially vertical end portion of the wiring width L2. They are arranged at the wiring interval S1. Here, for comparison, it is assumed that the cross-sectional area of each of the wirings 442a and 442b is equal to the cross-sectional area of each of the wirings 441a and 441b.
[0178]
The ratio L2 / S1 of the wiring width L2 of the wirings 442a and 442b and the wiring distance S1 can be smaller than the ratio L1 / S1 of the wiring width L1 of the wirings 441a and 441b and the wiring distance S1. That is, the wirings 442a and 442b have a shape suitable for integration.
[0179]
Thus, in the semiconductor device, the shape of the wiring formed by the gate metal can be appropriately selected. This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 5.
[0180]
【Example】
(Example 1)
Example 1 In this example, an example of manufacturing a semiconductor device including an arithmetic processing circuit (CPU), a memory circuit, and the like formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention will be described.
[0181]
FIG. 5 is a top view of a semiconductor device manufactured using the method for manufacturing a semiconductor device of the present invention. In FIG. 5, the semiconductor device includes a display device 551 and a CPU portion 552 which are formed using TFTs formed over a substrate 500 having an insulating surface. The display device 551 includes a pixel portion 501, a scan line driver circuit 502, and a signal line driver circuit 503. The CPU section 552 includes a CPU 507 and an SRAM (storage circuit) 504. In the display device 551, the pixel portion 501 displays an image. The scanning line driver circuit 502 and the signal line driver circuit 503 control input of a video signal to each pixel in the pixel portion. The SRAM (storage circuit) 504 is configured by a plurality of storage cells (not shown) arranged in a matrix. Each storage cell has a function of storing a signal input and output in the CPU 507 and the like. In addition, the CPU 507 has a function of outputting a control signal to the scan line driver circuit 502 and the signal line driver circuit 503, and the like.
[0182]
Note that the CPU unit 552 may include a GPU (video signal processing circuit) 557. This configuration is shown in FIG. The same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. A signal input from the outside of the substrate 500 is converted into a signal to be input to the display device 551 by a GPU (video signal processing circuit) 557.
[0183]
5 and 27 show an example in which a liquid crystal display device is used as the display device 551. As the pixel portion 501 of the liquid crystal display device 551, the structure shown in FIG. 12 can be used for a problem to be solved by the invention.
[0184]
In FIG. 12, a TFT 3002 included in a pixel is required to have low off-state current. This is to prevent a change in the voltage applied between the electrodes of the liquid crystal element 3003 arranged in each pixel due to the leakage current, a change in transmittance, and a disturbance in an image. Further, in a liquid crystal display device of a type (transmission type) in which an image is visually recognized through the pixel TFT 3002, the pixel TFT 3002 needs to be miniaturized in order to increase the aperture ratio. Further, a voltage of about 16 V is normally applied between the electrodes of the liquid crystal element 3003. Therefore, the pixel TFT 3002 and the like are required to have a withstand voltage of about 16 V. Therefore, the TFT needs to have a structure having a Lov region or a Loff region.
[0185]
On the other hand, in FIGS. 5 and 27, the TFTs (TFTs for the pixel driving circuit) included in the pixel driving circuit portion (the scanning line driving circuit 502 and the signal line driving circuit 503) have a smaller off-current and a smaller size than the pixel TFT. Is not required. However, since it operates with a power supply voltage of about 16 V, a withstand voltage is required.
[0186]
The arithmetic processing circuit (CPU unit) 552 requires a high driving frequency. Therefore, for the TFT included in the CPU portion 552 (hereinafter, referred to as an arithmetic circuit TFT), improvement in carrier mobility and miniaturization are required. On the other hand, since the arithmetic processing circuit (CPU unit) 552 manufactured using the miniaturized TFT operates with a power supply voltage of about 3 to 5 V, the withstand voltage of the TFT is not required to be as high as that of a pixel TFT or a TFT for a pixel driving circuit. .
[0187]
Therefore, in Embodiment 3, the manufacturing method illustrated in FIG. 4 is used in order to separately manufacture TFTs included in the circuits illustrated in FIGS. The N-channel TFT 361 shown in FIG. 4 is used as a pixel TFT. The N-channel TFT 361 has a structure having a Loff region and a high effect of suppressing off current. Further, the N-channel TFT 362 and the P-channel TFT 363 shown in FIG. 4 are used as TFTs for a pixel driving circuit. Each of the N-channel TFT 362 and the P-channel TFT 363 has a high withstand voltage structure having a Lov region having a high effect of suppressing deterioration due to hot carriers. Further, the N-channel TFT 364 and the P-channel TFT 365 shown in FIG. 4 are used as arithmetic circuit TFTs. Each of the N-channel TFT 364 and the P-channel TFT 365 has a shape that can be miniaturized. That is, the portion of the liquid crystal display device 551 which operates at a power supply voltage of about 16 V is manufactured by the gate electrode manufacturing process following the first exposure in FIG. 4, and the gate electrode manufacturing process subsequent to the second exposure in FIG. Thus, the CPU unit 552 that operates at a power supply voltage of about 3 to 5 V is manufactured.
[0188]
Thus, a semiconductor device including an arithmetic processing circuit (CPU), a memory circuit, and the like formed over the same substrate as a display device can be manufactured using a TFT suitable for each circuit.
[0189]
Note that the present invention can be implemented by freely combining with Embodiment Modes 1 to 6.
[0190]
(Example 2)
Example 1 In this example, a semiconductor device including a CPU portion (an arithmetic processing circuit (CPU), a memory circuit, and the like) formed over the same substrate as a display device is manufactured using a method for manufacturing a semiconductor device of the present invention. Here is an example. Note that the configurations of the display device and the CPU portion, and the TFTs used for those circuits can be the same as those in the first embodiment.
[0191]
FIG. 6 is a cross-sectional view of a semiconductor device manufactured using the present invention. As a pixel TFT constituting the pixel portion, an N-channel TFT 361 is shown as a representative. In addition, an N-channel TFT 362 and a P-channel TFT 363 are representatively shown as elements constituting the pixel driving circuit portion. As elements constituting the CPU portion, an N-channel TFT 364 and a P-channel TFT 365 are shown as representatives. The manufacturing method of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 is the same as the manufacturing method shown in FIG. Description is omitted. The same parts as those in FIG. 4 are described using the same reference numerals.
[0192]
As shown in FIG. 6A, a first interlayer insulating film 6036 is formed. The first interlayer insulating film 6036 is formed using a plasma-enhanced CVD method or a sputtering method to have a thickness of 100 to 200 nm, and is formed using an insulating film containing silicon. In this embodiment, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 6036 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0193]
Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed at 410 ° C. for one hour. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Further, heat treatment may be performed before forming the first interlayer insulating film 6036. However, when the gate electrodes of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 are vulnerable to heat, the wiring and the like are protected as in this embodiment. It is preferable to perform heat treatment after forming one interlayer insulating film 6036 (an insulating film containing silicon as a main component, for example, a silicon nitride film).
[0194]
As described above, by performing heat treatment after forming the first interlayer insulating film 6036 (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer can be performed simultaneously with the activation process. it can. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 6036. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 6036. As other means for hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen is performed. Means may be used.
[0195]
Next, as shown in FIG. 6B, a second interlayer insulating film 6037 is formed over the first interlayer insulating film 6036. As the second interlayer insulating film 6037, an inorganic insulating film can be used. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. As the second interlayer insulating film 6037, an organic insulating film can be used. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Further, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used. In this embodiment, an acrylic film having a thickness of 1.6 μm is formed. With the second interlayer insulating film 6037, unevenness due to TFTs (N-channel TFT 361, N-channel TFT 362, P-channel TFT 363, N-channel TFT 364, and P-channel TFT 365) can be reduced and planarized. In particular, since the second interlayer insulating film 6037 has a strong meaning of flattening, a film excellent in flatness is preferable.
[0196]
Next, the second interlayer insulating film 6037, the first interlayer insulating film 6036, and the gate insulating film 203 are etched using dry etching or wet etching, and an N-channel TFT 361, an N-channel TFT 362, a P-channel TFT 363, A contact hole reaching the source region and the drain region of each of the channel TFT 364 and the P-channel TFT 365 is formed. Next, wirings 6040 to 6046 and a pixel electrode 6039 electrically connected to the source region and the drain region of each TFT are formed. Note that in this embodiment, the wirings 6040 to 6046 and the pixel electrode 6039 are formed by continuously forming a stacked film of a 50-nm-thick Ti film and a 500-nm-thick Al / Ti alloy film by a sputtering method to have a desired shape. It is formed by patterning. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a three- or more-layer structure. The material of the wiring is not limited to Al and Ti, and other conductive films may be used. For example, a wiring may be formed by forming an Al film or a Cu film on a TaN film and then patterning a laminated film in which a Ti film is formed. However, it is preferable to use a material having excellent reflectivity.
[0197]
Subsequently, as shown in FIG. 6C, an alignment film 6047 is formed over a portion including at least the pixel electrode 6039, and rubbing treatment is performed. In this embodiment, a columnar spacer 6048 for maintaining a substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film before forming the alignment film 6047. In addition, not only the columnar spacer but also a spherical spacer may be scattered over the entire surface of the substrate.
[0198]
Next, a counter substrate 7000 is prepared. Coloring layers (color filters) 7001 to 7003 and a planarizing film 7004 are formed over the counter substrate 7000. At this time, the first coloring layer 7001 and the second coloring layer 7002 are overlapped to form a light-blocking portion, and the second coloring layer 7002 and a part of the third coloring layer 7003 are overlapped to form a light-blocking portion. . Further, a part of the first coloring layer 7001 and part of the third coloring layer 7003 may be overlapped to form a light-blocking portion. As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion formed of the colored layer without forming a new light-shielding layer.
[0199]
Next, a counter electrode 7005 made of a transparent conductive film is formed over the flattening film 7004 at least in a portion corresponding to a pixel portion. After that, an alignment film 7006 is formed over the entire surface of the counter substrate 7005, and rubbing treatment is performed.
[0200]
Then, the substrate 201 on which the pixel portion, the driver circuit portion, and the CPU portion are formed and the counter substrate 7000 are attached to each other with a sealant 7007. A filler (not shown) is mixed in the sealant 7007, and the substrate 201 and the counter substrate 7000 are bonded to each other at a uniform interval by the filler and the columnar spacer 6048. After that, a liquid crystal material 7008 is injected between the two substrates (201 and 7000) and completely sealed with a sealing material (not shown). As the liquid crystal material 7008, a known material may be used. Thus, a liquid crystal display device is completed.
[0201]
Then, a polarizing plate and an FPC (not shown) are attached. By the FPC, a terminal led from an element or a circuit formed over the substrate 201 is connected to an external signal terminal. Thus, the product is completed.
[0202]
In this embodiment, a reflective liquid crystal display device in which the pixel electrode 6039 is formed of a metal film having excellent reflectivity and the counter electrode 7005 is formed of a light-transmitting material is described as an example. Not limited. For example, the present invention can be applied to a transmissive liquid crystal display device in which the pixel electrode 6039 is formed using a light-transmitting material and the counter electrode 7005 is formed using a reflective material. The present invention can be applied to a transflective liquid crystal display device.
[0203]
This embodiment can be implemented by being freely combined with Embodiment Modes 1 to 6 and Embodiment 1.
[0204]
(Example 3)
In this embodiment, an example of manufacturing a semiconductor device including a CPU portion (an arithmetic processing circuit (CPU), a storage circuit, and the like) formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. Is shown. Note that the configurations of the display device and the CPU portion, and the TFTs used for those circuits can be the same as those in the first embodiment.
[0205]
However, in this embodiment, it is assumed that the display device is an OLED display device in which an OLED element is arranged in each pixel. The OLED element has a configuration including an anode, a cathode, and an organic compound layer interposed between the anode and the cathode. The OLED element emits light by applying a voltage between the anode and the cathode. The organic compound layer can have a laminated structure. A typical example is a laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by Tang et al. Of Kodak Eastman Company. In addition, a hole injection layer / a hole transport layer / a light emitting layer / an electron transport layer, or a hole injection layer / a hole transport layer / a light emitting layer / an electron transport layer / an electron injection layer are stacked in this order on the anode. The structure may be sufficient. The light emitting layer may be doped with a fluorescent dye or the like. All the layers provided between the cathode and the anode of the OLED element are collectively called an organic compound layer. Therefore, the above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer, and the like are all included in the organic compound layer. When a predetermined voltage is applied to the organic compound layer having the above structure from a pair of electrodes (anode and cathode), recombination of carriers occurs in the light-emitting layer to emit light. The OLED element may use either light emission (fluorescence) from a singlet exciton or light emission (phosphorescence) from a triplet exciton. An OLED display device has advantages such as excellent responsiveness, operation at a low voltage, and a wide viewing angle, and thus has attracted attention as a next-generation flat panel display.
[0206]
FIG. 7 shows a cross-sectional view of a semiconductor device manufactured using the present invention. As a TFT constituting a pixel portion, a TFT connected in series with an OLED element is typically shown as an N-channel TFT 361. In addition, an N-channel TFT 362 and a P-channel TFT 363 are representatively shown as elements constituting the pixel driving circuit portion. As elements constituting the CPU portion, an N-channel TFT 364 and a P-channel TFT 365 are shown as representatives. The method for manufacturing the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 is the same as the manufacturing method shown in FIGS. Is omitted. The same parts as those in FIG. 4 are described using the same reference numerals.
[0207]
According to Embodiment 3, the structure is manufactured up to the state illustrated in FIG. In FIG. 7B, a first interlayer insulating film 5036 is formed. This first interlayer insulating film 5036 is formed using a plasma CVD method or a sputtering method with an insulating film containing silicon with a thickness of 100 to 200 nm. In this embodiment, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 5036 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed at 410 ° C. for one hour. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Further, heat treatment may be performed before forming the first interlayer insulating film 5036. However, when the gate electrodes of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 are vulnerable to heat, the wiring and the like are protected as in this embodiment. It is preferable to perform heat treatment after forming one interlayer insulating film 5036 (an insulating film containing silicon as a main component, for example, a silicon nitride film).
[0208]
As described above, by performing heat treatment after forming the first interlayer insulating film 5036 (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer is performed simultaneously with the activation process. Can be. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5036. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5036. As other means for hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen is performed. Means may be used.
[0209]
Next, a second interlayer insulating film 5037 is formed over the first interlayer insulating film 5036. As the second interlayer insulating film 5037, an inorganic insulating film can be used. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. Further, an organic insulating film can be used as the second interlayer insulating film 5037. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Further, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used. In this embodiment, an acrylic film having a thickness of 1.6 μm is formed. With the second interlayer insulating film 5037, unevenness due to the TFT formed over the substrate 201 can be reduced and planarized. In particular, since the second interlayer insulating film 5037 has a strong meaning of flattening, a film excellent in flatness is preferable.
[0210]
Next, the second interlayer insulating film 5037, the first interlayer insulating film 5036, and the gate insulating film 203 are etched using dry etching or wet etching, and an N-channel TFT 361, an N-channel TFT 362, a P-channel TFT 363, A contact hole reaching the source region and the drain region of each of the channel TFT 364 and the P-channel TFT 365 is formed.
[0211]
Next, a pixel electrode 5038 made of a transparent conductive film is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (ITO), a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, indium oxide, and the like can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 5038 corresponds to the anode of the OLED element. In this embodiment, ITO is formed to a thickness of 110 nm and is patterned to form a pixel electrode 5038.
[0212]
Next, wirings 5039 to 5046 electrically connected to the source region and the drain region of each of the TFTs (N-channel TFT 361, N-channel TFT 362, P-channel TFT 363, N-channel TFT 364, and P-channel TFT 365) are formed. Form. Note that in this embodiment, the wirings 5039 to 5046 are formed by continuously forming a stacked film of a 100-nm-thick Ti film, a 350-nm-thick Al film, and a 100-nm-thick Ti film by a sputtering method to have a desired shape. It is formed by patterning. Of course, the present invention is not limited to the three-layer structure, and may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. The material of the wiring is not limited to Al and Ti, and other conductive films may be used. For example, a wiring may be formed by forming Al or Cu on a TaN film and then patterning a laminated film in which a Ti film is formed. Thus, one of the source region and the drain region of the N-channel TFT 361 in the pixel portion is electrically connected to the pixel electrode 5038 by the wiring 5039. Here, the wiring 5039 and the pixel electrode 5038 are electrically connected to each other by forming part of the wiring 5039 to overlap with part of the pixel electrode 5038.
[0213]
Next, as shown in FIG. 7D, a third interlayer insulating film 5047 is formed. As the third interlayer insulating film 5047, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method, or the like is used. Can be. An acrylic resin film or the like can be used as the organic insulating film.
[0214]
An example of a combination of the second interlayer insulating film 5037 and the third interlayer insulating film 5047 is described below. As the second interlayer insulating film 5037, a stacked film of acrylic and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used. As the third interlayer insulating film 5047, a silicon nitride film formed by a sputtering method Alternatively, there is a combination using a silicon nitride oxide film. There is a combination in which a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037, and a silicon oxide film formed by a plasma CVD method is also used as the third interlayer insulating film 5047. Further, there is a combination in which a silicon oxide film formed by an SOG method is used as the second interlayer insulating film 5037 and a silicon oxide film formed by an SOG method is used as the third interlayer insulating film 5047. Further, a stacked film of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037, and an oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5047. There is a combination using a silicon film. In addition, there is a combination in which acrylic is used for the second interlayer insulating film 5037 and acrylic is used for the third interlayer insulating film 5047. Further, there is a combination in which a stacked film of acrylic and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037, and a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5047. . Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037 and acrylic is used as the third interlayer insulating film 5047.
[0215]
An opening is formed in the third interlayer insulating film 5047 at a position corresponding to the pixel electrode 5038. The third interlayer insulating film 5047 functions as a bank. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. Care must be taken because if the side wall of the opening is not sufficiently smooth, the deterioration of the organic compound layer due to the step will become a significant problem. Carbon particles or metal particles may be added to the third interlayer insulating film 5047 to lower the resistivity and suppress generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1 × 10 ¹⁰ Ωm) may be adjusted by adjusting the amount of carbon particles or metal particles added.
[0216]
Next, an organic compound layer 5048 is formed over the pixel electrode 5038 exposed in the opening of the third interlayer insulating film 5047. As the organic compound layer 5048, a known organic light-emitting material can be used. Note that both an organic light emitting material and an inorganic light emitting material may be used, or an inorganic light emitting material may be used instead of the organic light emitting material.
[0219]
As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, and a medium molecular weight organic light emitting material can be freely used. Note that the medium molecular organic light-emitting material refers to an organic light-emitting material having no sublimability and having a degree of polymerization of about 20 or less.
[0218]
In this embodiment, the organic compound layer 5048 is formed using a low molecular weight organic light emitting material by an evaporation method. Specifically, a 20 nm thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) It has a laminated structure provided with a film. Alq ₃ The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to the dye.
[0219]
As an example of using a high molecular weight organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided as a hole injection layer by spin coating, and a 100 nm paraphenylene vinylene (PPV) film is provided thereon as a light emitting layer. The organic compound layer 5048 may have a stacked structure. When a π-conjugated polymer of PPV is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer and the electron injection layer.
[0220]
Note that the organic compound layer 5048 is not limited to a layer in which a hole-injecting layer, a hole-transporting layer, a light-emitting layer, an electron-transporting layer, an electron-injecting layer, and the like have a distinctly stacked structure. That is, the organic compound layer 5048 may have a structure in which a material for forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, or the like is mixed. For example, a mixed layer composed of a material constituting the electron transport layer (hereinafter, referred to as an electron transport material) and a material constituting the light emitting layer (hereinafter, referred to as a light emitting material) is formed by combining the electron transport layer with the light emitting material. An organic compound layer 5048 having a structure between the layer and the organic compound layer may be used.
[0221]
Next, a counter electrode 5049 made of a conductive film is provided over the organic compound layer 5048. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Note that an MgAg film (an alloy film of magnesium and silver) may be used. In this embodiment, the counter electrode 5049 corresponds to the cathode of the OLED element. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added can be freely used.
[0222]
The OLED element is completed when the counter electrode 5049 is formed. Note that an OLED element refers to a diode formed using a pixel electrode (anode) 5038, an organic compound layer 5048, and a counter electrode (cathode) 5049.
[0223]
It is effective to provide the passivation film 5050 so as to completely cover the OLED element. As the passivation film 5050, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film can be used as a single layer or a stacked layer. It is preferable to use a film having good coverage as the passivation film 5050, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or less, it can be easily formed over the organic compound layer 5048 having low heat resistance. Further, the DLC film has a high blocking effect against oxygen, and can suppress oxidation of the organic compound layer 5048.
[0224]
Note that the steps from the formation of the third interlayer insulating film 5047 to the formation of the passivation film 5050 are continuously performed without opening to the atmosphere using a multi-chamber (or in-line) film forming apparatus. That is valid.
[0225]
In fact, when the state shown in FIG. 7 (D) is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) with high airtightness and low degassing, or a light-transmitting It is preferable to package (enclose) with a sealing material. At this time, the reliability of the OLED element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.
[0226]
If the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or a circuit formed on the substrate 201 to an external signal terminal is attached. To complete the product.
[0227]
This embodiment can be implemented by being freely combined with Embodiment Modes 1 to 6 and Embodiment 1.
[0228]
(Example 4)
In this embodiment, an example of manufacturing a semiconductor device including a CPU portion (an arithmetic processing circuit (CPU), a storage circuit, and the like) formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. Is shown. Note that the configurations of the display device and the CPU portion, and the TFTs used for those circuits can be the same as those in the first embodiment. However, in the present embodiment, it is assumed that the display device is an OLED display device in which an OLED element is arranged in each pixel.
[0229]
FIG. 8 is a cross-sectional view of a semiconductor device manufactured using the present invention. As a TFT constituting a pixel portion, a TFT connected in series with an OLED element is typically shown as an N-channel TFT 361. In addition, an N-channel TFT 362 and a P-channel TFT 363 are representatively shown as elements constituting the pixel driving circuit portion. As elements constituting the CPU portion, an N-channel TFT 364 and a P-channel TFT 365 are shown as representatives.
[0230]
The method for manufacturing the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 is the same as the manufacturing method shown in FIGS. Is omitted. The same parts as those in FIG. 4 are described using the same reference numerals.
[0231]
According to the third embodiment, the semiconductor device is manufactured up to the state shown in FIG. As shown in FIG. 8B, a first interlayer insulating film 5101 is formed. The first interlayer insulating film 5101 is formed using a plasma CVD method or a sputtering method with a thickness of 100 to 200 nm and an insulating film containing silicon. In this embodiment, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 5101 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0232]
Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed at 410 ° C. for one hour. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Further, heat treatment may be performed before the first interlayer insulating film 5101 is formed. However, when the gate electrodes of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 are vulnerable to heat, the wiring and the like are protected as in this embodiment. It is preferable to perform heat treatment after forming one interlayer insulating film 5101 (an insulating film containing silicon as a main component, for example, a silicon nitride film).
[0233]
As described above, by performing heat treatment after forming the first interlayer insulating film 5101 (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer is performed simultaneously with the activation process. Can be. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5101. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5101. As other means for hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen is performed. Means may be used.
[0234]
Next, a second interlayer insulating film 5102 is formed over the first interlayer insulating film 5101. As the second interlayer insulating film 5102, an inorganic insulating film can be used. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. Further, as the second interlayer insulating film 5102, an organic insulating film can be used. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Further, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.
[0235]
Next, the first interlayer insulating film 5101, the second interlayer insulating film 5102, and the gate insulating film 203 are etched using dry etching or wet etching, and each TFT (N-channel TFT 361, N-channel TFT 362, P-channel TFT A contact hole reaching the source region and the drain region of the TFT 363, the N-channel TFT 364, and the P-channel TFT 365) is formed.
[0236]
Next, wirings 5103 to 5110 electrically connected to the source region and the drain region of each of the TFTs (N-channel TFT 361, N-channel TFT 362, P-channel TFT 363, N-channel TFT 364, and P-channel TFT 365) are formed. I do. In this embodiment, the wirings 5103 to 5110 are formed by continuously forming a laminated film of a 100-nm-thick Ti film, a 350-nm-thick Al film, and a 100-nm-thick Ti film by a sputtering method to have a desired shape. It is formed by patterning. Of course, the present invention is not limited to the three-layer structure, and may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. The material of the wiring is not limited to Al and Ti, and other conductive films may be used. For example, a wiring may be formed by forming Al or Cu on a TaN film and then patterning a laminated film in which a Ti film is formed.
[0237]
Next, as shown in FIG. 8D, a third interlayer insulating film 5111 is formed. As the third interlayer insulating film 5111, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used. With the third interlayer insulating film 5111, unevenness due to TFTs (N-channel TFT 361, N-channel TFT 362, P-channel TFT 363, N-channel TFT 364, and P-channel TFT 365) can be reduced and planarized. In particular, since the third interlayer insulating film 5111 has a strong meaning of flattening, a film excellent in flatness is preferable.
[0238]
Next, a contact hole reaching the wiring 5103 is formed in the third interlayer insulating film 5111 by dry etching or wet etching.
[0239]
Next, the pixel electrode 5112 is formed by patterning the conductive film. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Note that an MgAg film (an alloy film of magnesium and silver) may be used. The pixel electrode 5112 corresponds to a cathode of the OLED element. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added can be freely used.
[0240]
The pixel electrode 5112 is electrically connected to the wiring 5103 by a contact hole formed in the third interlayer insulating film 5111. Thus, the pixel electrode 5112 is electrically connected to one of the source region and the drain region of the N-channel TFT 361.
[0241]
Next, a bank 5113 is formed in order to separately apply the organic compound layer between the pixels. The bank 5113 is formed using an inorganic insulating film or an organic insulating film. As the inorganic insulating film, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film. Here, when the bank 5113 is formed, a tapered side wall can be easily formed by using a wet etching method. Attention must be paid to the fact that if the side wall of the bank 5113 is not sufficiently gentle, the deterioration of the organic compound layer due to the step becomes a significant problem. Note that when electrically connecting the pixel electrode 5112 and the wiring 5103, a bank 5113 is also formed in a contact hole portion formed in the third interlayer insulating film 5111. Thus, the unevenness of the pixel electrode due to the unevenness of the contact hole portion is filled with the bank 5113, thereby preventing the organic compound layer from being deteriorated due to the step.
[0242]
An example of a combination of the third interlayer insulating film 5111 and the bank 5113 is described below. As the third interlayer insulating film 5111, a stacked film of acrylic and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used, and as a bank 5113, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method There are combinations using. There is a combination in which a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5111, and a silicon oxide film formed by a plasma CVD method is used as the bank 5113. Further, there is a combination in which a silicon oxide film formed by an SOG method is used as the third interlayer insulating film 5111 and a silicon oxide film formed by an SOG method is used as the bank 5113. As the third interlayer insulating film 5111, a combination of a stacked film of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method, and a silicon oxide film formed by a plasma CVD method as a bank 5113 is used. is there. Further, there is a combination in which acrylic is used for the third interlayer insulating film 5111 and acrylic is used for the bank 5113. Further, there is a combination in which a stacked film of acrylic and a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5111, and a silicon oxide film formed by a plasma CVD method is used as a bank 5113. Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5111 and acrylic is used as the bank 5113. Note that carbon particles or metal particles may be added to the bank 5113 to lower the resistivity and suppress generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1 × 10 ¹⁰ Ωm) may be adjusted by adjusting the amount of carbon particles or metal particles added.
[0243]
Next, an organic compound layer 5114 is formed over the exposed pixel electrode 5112 surrounded by the bank 5113. As the organic compound layer 5114, a known organic light-emitting material can be used. Note that both an organic light emitting material and an inorganic light emitting material may be used, or an inorganic light emitting material may be used instead of the organic light emitting material. As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, and a medium molecular weight organic light emitting material can be freely used. Note that the medium molecular organic light-emitting material refers to an organic light-emitting material having no sublimability and having a degree of polymerization of about 20 or less.
[0244]
In this embodiment, the organic compound layer 5114 is formed using a low molecular weight organic light emitting material by an evaporation method. Specifically, a 70 nm-thick tris-8-quinolinolato aluminum complex (Alq ₃ ) A film is provided, and a 20 nm-thick copper phthalocyanine (CuPc) film is provided thereon as a hole injection layer. Alq ₃ The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to the dye.
[0245]
As an example of using a high molecular weight organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided as a hole injection layer by spin coating, and a 100 nm paraphenylene vinylene (PPV) film is formed thereon as a light emitting layer. The organic compound layer 5114 may be formed using the provided stacked structure. When a π-conjugated polymer of PPV is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer and the electron injection layer.
[0246]
Note that the organic compound layer 5114 is not limited to a layer in which a hole-injecting layer, a hole-transporting layer, a light-emitting layer, an electron-transporting layer, an electron-injecting layer, and the like have a clearly distinguished stacked structure. That is, the organic compound layer 5114 may have a structure in which materials forming the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like are mixed. For example, a mixed layer composed of a material constituting the electron transport layer (hereinafter, referred to as an electron transport material) and a material constituting the light emitting layer (hereinafter, referred to as a light emitting material) is formed by combining the electron transport layer with the light emitting material. An organic compound layer 5114 having a structure provided between the layers may be used.
[0247]
Next, a counter electrode 5115 made of a transparent conductive film is formed over the organic compound layer 5114. As the transparent conductive film, a compound of indium oxide and tin oxide (ITO), a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, indium oxide, and the like can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The counter electrode 5115 corresponds to the anode of the OLED element.
[0248]
The OLED element is completed when the counter electrode 5115 is formed. Note that an OLED element refers to a diode formed using a pixel electrode (cathode) 5112, an organic compound layer 5114, and a counter electrode (anode) 5115.
[0249]
In this embodiment, since the opposing electrode 5115 is formed of a transparent conductive film, light emitted from the OLED element is emitted toward the side opposite to the substrate 201. Further, the pixel electrode 5112 is formed in a layer different from the layer where the wirings 5103 to 5110 are formed by the third interlayer insulating film 5111. Therefore, the aperture ratio can be increased as compared with the configuration shown in the third embodiment.
[0250]
It is effective to provide a protective film (passivation film) 5116 so as to completely cover the OLED element. As the protective film 5116, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film can be used as a single layer or a stacked layer. Note that when light emitted from the OLED element is emitted from the counter electrode 5115 side as in this embodiment, it is necessary to use a film that transmits light as the protective film 5116.
[0251]
Note that it is effective to continuously process the steps from the formation of the bank 5113 to the formation of the protective film 5116 without release to the atmosphere using a multi-chamber (or in-line) film forming apparatus. .
[0252]
In fact, when the structure shown in FIG. 8D is completed, a sealing material such as a protective film (laminate film, ultraviolet curable resin film, etc.) having high airtightness and low degassing is used so as not to be further exposed to the outside air. Packaging (encapsulation) is preferred. At this time, the reliability of the OLED element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.
[0253]
If the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or a circuit formed on the substrate 201 to an external signal terminal is attached. To complete the product.
[0254]
This embodiment can be implemented by being freely combined with Embodiment Modes 1 to 6 and Embodiment 1.
[0255]
(Example 5)
Example 1 In this example, an example of a method of crystallizing a semiconductor film in manufacturing a semiconductor active layer of a TFT included in a semiconductor device of the present invention will be described.
[0256]
A silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) 400 nm was formed as a base film on a glass substrate by a plasma CVD method. Subsequently, an amorphous silicon film of 150 nm is formed as a semiconductor film on the base film by a plasma CVD method. After performing heat treatment at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film, crystallization of the semiconductor film is performed by a laser annealing method.
[0257]
The laser used in the laser annealing method is a continuous wave YVO. ₄ Use a laser. The conditions of the laser annealing method are as follows. ₄ The second harmonic (wavelength 532 nm) of the laser was used. The semiconductor film formed on the substrate surface was irradiated with laser light as a beam having a predetermined shape by an optical system.
[0258]
Note that the shape of the beam applied to the substrate can be changed depending on the type of laser or the optical system. Thus, the distribution of the aspect ratio and the energy density of the beam irradiated on the substrate can be changed. For example, the shape of the beam irradiated on the substrate can be various shapes such as a linear shape, a rectangular shape, and an elliptical shape. In this embodiment, YVO ₄ The second harmonic of the laser is made into an ellipse of 200 μm × 50 μm by an optical system, and is irradiated on the semiconductor film.
[0259]
Here, FIG. 14 is a schematic diagram of an optical system used when a semiconductor film formed over a substrate surface is irradiated with laser light. Laser light (YVO) emitted from laser 1101 ₄ The second harmonic of the laser) enters the convex lens 1103 via the mirror 1102. The laser light is made obliquely incident on the convex lens 1103. By doing so, the focal position shifts due to aberration such as astigmatism, and an elliptical beam 1106 can be formed on or near the irradiation surface. Then, while irradiating the elliptical beam 1106 thus formed, the glass substrate 1105 is moved in a direction indicated by 1107 or a direction indicated by 1108, for example. Thus, the semiconductor film 1104 formed over the glass substrate 1105 is irradiated with the elliptical beam 1106 while relatively moving. The relative scanning direction of the elliptical beam 1106 is a direction perpendicular to the major axis of the elliptical beam 1106. In this embodiment, an elliptical beam of 200 μm × 50 μm is formed by setting the incident angle φ of the laser beam to the convex lens 1103 to about 20 °, and irradiation is performed while moving the glass substrate 1105 at a speed of 50 cm / s. Perform crystallization.
[0260]
FIG. 15 shows the result obtained by subjecting the crystalline semiconductor film thus obtained to secco etching and observing the surface at 10,000 times by SEM. The Seco liquid used in the Seco etching is HF: H ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ It is manufactured using. FIG. 15 is obtained by relatively scanning a laser beam in a direction indicated by an arrow in the figure. It can be seen that large crystal grains are formed parallel to the scanning direction of the laser beam. That is, the crystal is grown so as to extend in the scanning direction of the laser light.
[0261]
As described above, large-sized crystal grains are formed in the semiconductor film crystallized using the method of this embodiment. Therefore, when a TFT is manufactured using the semiconductor film as a semiconductor active layer, the number of crystal grain boundaries included in a channel formation region of the TFT can be reduced. In addition, since the inside of each crystal grain has crystallinity substantially regarded as a single crystal, high mobility (field-effect mobility) equivalent to that of a transistor using a single crystal semiconductor can be obtained.
[0262]
Further, when the TFT is arranged such that the carrier movement direction is aligned with the direction in which the formed crystal grains extend, the number of times the carriers cross the crystal grain boundaries can be extremely reduced. Therefore, variations in the ON current value (the drain current value flowing when the TFT is in the ON state), the OFF current value (the drain current value flowing when the TFT is in the OFF state), the threshold voltage, the S value, and the field effect mobility. Can be reduced, and the electrical characteristics are significantly improved.
[0263]
Note that in order to irradiate the elliptical beam 1106 over a wide area of the semiconductor film, a plurality of operations of scanning the elliptical beam 1106 in a direction perpendicular to the major axis thereof and irradiating the semiconductor film (hereinafter, referred to as scanning) are performed. Going around. Here, for each scan, the position of the elliptical beam 1106 is shifted in a direction parallel to its long axis. The scanning direction is reversed between successive scans. Here, in two consecutive scans, one is referred to as a forward scan and the other is referred to as a backward scan.
[0264]
The size of shifting the position of the elliptical beam 1106 in a direction parallel to the major axis for each scan is expressed as a pitch d. In the forward scan, the length of the region where the crystal grains having the large grain size as shown in FIG. 15 are formed in the direction perpendicular to the scanning direction of the elliptical beam 1106 is denoted by D1. In the return scan, the length of the region where the crystal grains having the large grain size as shown in FIG. 15 are formed in the direction perpendicular to the scanning direction of the elliptical beam 1106 is denoted by D2. The average value of D1 and D2 is D. At this time, the overlap rate R _{O. L} [%] Is defined by Equation 1.
[0265]
[Formula 1] R _{O. L} = (1-d / D) × 100
[0266]
In this embodiment, the overlap rate R _{O. L} Is set to 0%.
[0267]
This embodiment can be implemented by freely combining with Embodiment Modes 1 to 6 and Embodiments 1 to 4.
[0268]
(Example 6)
In this embodiment, an example different from that in Embodiment 5 in a method of crystallizing a semiconductor film in manufacturing a semiconductor active layer of a TFT included in the semiconductor device of the present invention will be described.
[0269]
Steps until an amorphous silicon film is formed as a semiconductor film are the same as those in the fifth embodiment. Thereafter, using a method described in JP-A-7-183540, an aqueous nickel acetate solution (concentration in terms of weight: 5 ppm, volume: 10 ml) is applied onto the semiconductor film by a spin coating method, and the solution is placed in a nitrogen atmosphere at 500 ° C. Heat treatment is performed for 1 hour in a nitrogen atmosphere at 550 ° C. for 12 hours. Subsequently, the crystallinity of the semiconductor film is improved by a laser annealing method.
[0270]
The laser used in the laser annealing method is a continuous wave YVO. ₄ Use a laser. The conditions of the laser annealing method are as follows. ₄ An elliptical beam of 200 μm × 50 μm is formed using the second harmonic (wavelength 532 nm) of the laser and setting the incident angle φ of the laser beam to the convex lens 1103 in the optical system shown in FIG. The elliptical beam is irradiated while moving the glass substrate 1105 at a speed of 50 cm / s to improve the crystallinity of the semiconductor film. The relative scanning direction of the elliptical beam 1106 is a direction perpendicular to the major axis of the elliptical beam 1106.
[0271]
Seco etching was performed on the crystalline semiconductor film thus obtained, and the surface was observed at 10,000 times by SEM. FIG. 16 shows the result. FIG. 16 is obtained by relatively scanning a laser beam in a direction indicated by an arrow in the figure, and shows a state in which large crystal grains are formed extending in the scanning direction. Understand.
[0272]
As described above, since a semiconductor film crystallized by using the present invention has large crystal grains, when a TFT is manufactured using the semiconductor film, a crystal included in a channel formation region thereof is formed. The number of grain boundaries can be reduced. In addition, since individual crystal grains have substantially crystallinity that can be regarded as a single crystal, high mobility (field-effect mobility) equivalent to that of a transistor using a single crystal semiconductor can be obtained.
[0273]
Further, the formed crystal grains are aligned in one direction. Therefore, if the TFT is arranged such that the moving direction of the carrier is aligned with the direction in which the formed crystal grains extend, the number of times the carriers cross the crystal grain boundaries can be extremely reduced. Therefore, it is possible to reduce variations in the on-current value, the off-current value, the threshold voltage, the S value, and the field-effect mobility, and the electrical characteristics are significantly improved.
[0274]
Note that in order to irradiate the elliptical beam 1106 over a wide area of the semiconductor film, an operation (scanning) of scanning the elliptical beam 1106 in a direction perpendicular to the major axis thereof and irradiating the semiconductor film is performed a plurality of times. Here, for each scan, the position of the elliptical beam 1106 is shifted in a direction parallel to its long axis. The scanning direction is reversed between successive scans. Here, in two consecutive scans, one is referred to as a forward scan and the other is referred to as a backward scan.
[0275]
The size of shifting the position of the elliptical beam 1106 in the direction parallel to the long axis for each scan is expressed as a pitch d. In the forward scan, the length of the region where the crystal grains having a large grain size are formed as shown in FIG. 16 in the direction perpendicular to the scanning direction of the elliptical beam 1106 is denoted by D1. In the return scan, the length of the region where the crystal grains having the large grain size as shown in FIG. 16 are formed in the direction perpendicular to the scanning direction of the elliptical beam 1106 is denoted by D2. The average value of D1 and D2 is D.
[0276]
At this time, the overlap rate R _{O. L} Define [%]. In this embodiment, the overlap rate R _{O. L} Is set to 0%.
[0277]
In addition, the result of Raman scattering spectroscopy of the semiconductor film (indicated as “Improved CG-Silicon” in the figure) obtained by the above-described crystallization method is shown in FIG. Here, for comparison, the results of Raman scattering spectroscopy of single crystal silicon (in the figure, denoted as ref. (100) Si Wafer) are shown by thin lines. In addition, after forming an amorphous silicon film, a heat treatment is performed to release hydrogen contained in the semiconductor film, and then the semiconductor film is crystallized using a pulse oscillation excimer laser (in the figure, expressed as excimer laser annealing). 17) is shown by the dotted line in FIG. The Raman shift of the semiconductor film obtained by the method of this embodiment is 517.3 cm. ^-1 Having a peak of The half width is 4.96 cm. ^-1 It is. On the other hand, the Raman shift of single crystal silicon is 520.7 cm ^-1 Having a peak of The half width is 4.44 cm. ^-1 It is. The Raman shift of a semiconductor film crystallized using a pulsed excimer laser is 516.3 cm. ^-1 It is. The half width is 6.16 cm. ^-1 It is. According to the results of FIG. 17, the crystallinity of the semiconductor film obtained by the crystallization method described in this embodiment is smaller than that of the semiconductor film crystallized using a pulsed excimer laser. It turns out that it is close to silicon.
[0278]
This embodiment can be implemented by freely combining with Embodiment Modes 1 to 6 and Embodiments 1 to 4.
[0279]
(Example 7)
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method described in Embodiment 5 will be described with reference to FIGS.
[0280]
In this embodiment, a manufacturing method will be described, focusing on a TFT having a gate electrode manufactured by the same etching process. In this case, as in Embodiments 1 to 5, the description of the formation of the gate electrode corresponding to the TFT and the description of the doping process are omitted. Actually, this embodiment is implemented in combination with the method described in the first to fifth embodiments and the like.
[0281]
In this embodiment, a glass substrate is used as the substrate 20, and a silicon nitride oxide film (composition ratio: Si = 32%, O = 27%, N = 24%, H = (17%), 50 nm, and 100 nm of a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%). Next, an amorphous silicon film having a thickness of 150 nm is formed as a semiconductor film 22 on the base film 21 by a plasma CVD method. Then, heat treatment is performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film. (FIG. 18A)
[0282]
Then, the continuous oscillation YVO is used as laser light. ₄ An elliptical beam 1106 of 200 μm × 50 μm is formed by using the second harmonic (wavelength 532 nm, 5.5 W) of the laser and setting the incident angle φ of the laser beam to the convex lens 1103 in the optical system shown in FIG. . The semiconductor film 22 is irradiated with the elliptical beam 1106 by relatively scanning at a speed of 50 cm / s. Thus, the semiconductor film 23 is formed. (FIG. 18 (B))
[0283]
Then, a first doping process is performed. This is channel doping for controlling the threshold. B as material gas ₂ H ₆ Using a gas flow rate of 30 sccm, a current density of 0.05 μA, an acceleration voltage of 60 kV, and a dose of 1 × 10 ¹⁴ atoms / cm ² Do as. Thus, the semiconductor film 24 is formed. (FIG. 18 (C))
[0284]
Subsequently, patterning is performed to etch the semiconductor film 24 into a desired shape. After that, a 115-nm-thick silicon oxynitride film is formed by a plasma CVD method as a gate insulating film 27 which covers the etched semiconductor films 25 and 26. Next, a TaN film 28 having a thickness of 30 nm and a W film 29 having a thickness of 370 nm are stacked as conductive films on the gate insulating film 27. (FIG. 18D)
[0285]
A mask (not shown) made of a resist is formed by photolithography, and the W film, the TaN film, and the gate insulating film are etched. Thus, the conductive layers 30 (30a, 30b), 31 (31a, 31b) and the gate insulating film 32 (32a, 32b) are formed.
[0286]
Then, the mask made of the resist is removed, a new mask 33 is formed, a second doping process is performed, and an impurity element imparting N-type is introduced into the semiconductor film. In this case, the conductive layers 30a and 31a serve as a mask for the impurity element imparting N-type, and the impurity region 34 is formed in a self-aligned manner. In this embodiment, the second doping process is performed under two conditions because the thickness of the semiconductor film is as thick as 150 nm. In this embodiment, phosphine (PH) is used as a material gas. ₃ ) And the dose amount is 2 × 10 ^Thirteen atoms / cm ² After the acceleration voltage was set to 90 kV, the dose amount was set to 5 × 10 ¹⁴ atoms / cm ² And an acceleration voltage of 10 kV. (FIG. 18E)
[0287]
Next, after removing the resist mask 33, a new resist mask 35 is formed and a third doping process is performed. By the third doping process, an impurity region 36 to which an impurity element imparting P-type is added is formed in a semiconductor film to be an active layer of a P-channel TFT. Using the conductive layers 30b and 31b as a mask for the impurity element, an impurity element imparting P-type is added to form the impurity region 36 in a self-aligned manner. In this embodiment, the third doping process is also performed under two conditions because the thickness of the semiconductor film is as large as 150 nm. In the present embodiment, diborane (B ₂ H ₆ ) And the dose amount is 2 × 10 ^Thirteen atoms / cm ² After the acceleration voltage was set to 90 kV, the dose amount was set to 1 × 10 ^Fifteen atoms / cm ² And an acceleration voltage of 10 kV. (FIG. 18 (F))
[0288]
Through the above steps, the impurity regions 34 and 36 are formed in the respective semiconductor layers.
[0289]
Next, the mask 35 made of resist is removed, and a 50 nm-thick silicon oxynitride film (composition ratio: Si = 32.8%, O = 63.7%, N) is formed as the first interlayer insulating film 37 by a plasma CVD method. = 3.5%).
[0290]
Next, recovery of crystallinity of the semiconductor layer and activation of impurity elements added to the respective semiconductor layers are performed by heat treatment. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere by a thermal annealing method using a furnace annealing furnace. (FIG. 18 (G))
[0291]
Next, a second interlayer insulating film 38 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 37. In this embodiment, after a silicon nitride film with a thickness of 50 nm is formed by a CVD method, a silicon oxide film with a thickness of 400 nm is formed. When heat treatment is performed, hydrogenation treatment can be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at 410 ° C. for one hour using a furnace annealing furnace.
[0292]
Subsequently, a wiring 39 electrically connected to each impurity region is formed. In this embodiment, a stacked film of a 50-nm-thick Ti film, a 500-nm-thick Al—Si film, and a 50-nm-thick Ti film is formed by patterning. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a three- or more-layer structure. Further, the material of the wiring is not limited to Al and Ti. For example, a wiring may be formed by forming Al or Cu on a TaN film and then patterning a laminated film in which a Ti film is formed. (FIG. 18 (H))
[0293]
As described above, an N-channel TFT 51 and a P-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm are formed.
[0294]
FIG. 19 shows the results of measuring these electrical characteristics. FIG. 19A shows the electrical characteristics of the N-channel TFT 51, and FIG. 19B shows the electrical characteristics of the P-channel TFT 52. The measurement conditions of the electric characteristics were two measurement points, and the drain voltage Vd was 1 V and 5 V in the range of the gate voltage Vg = −16 to 16 V. In FIG. 19, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by dotted lines.
[0295]
Since a crystal grain having a large grain size is formed in a semiconductor film crystallized using the present invention, when a TFT is manufactured using the semiconductor film, the number of crystal grain boundaries included in a channel formation region thereof is increased. Can be reduced. Further, since the formed crystal grains are aligned in one direction, the number of times carriers cross the crystal grain boundaries can be extremely reduced. Therefore, a TFT having good electrical characteristics can be obtained as shown in FIG. In particular, the mobility is 524 cm for an N-channel TFT. ² / Vs, 205 cm for P-channel TFT ² / Vs. If a semiconductor device is manufactured using such a TFT, the operation characteristics and reliability can be improved.
[0296]
This embodiment can be implemented by freely combining with Embodiment Modes 1 to 6 and Embodiments 1 to 4.
[0297]
(Example 8)
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method described in Embodiment 6 will be described with reference to FIGS. In this embodiment, a manufacturing method will be described, focusing on a TFT having a gate electrode manufactured by the same etching process. In this case, as in Embodiments 1 to 5, the description of the formation of the gate electrode corresponding to the TFT and the description of the doping process are omitted. Actually, this embodiment is implemented in combination with the method described in the first to fifth embodiments and the like.
[0298]
Steps until an amorphous silicon film is formed as a semiconductor film are the same as those in the seventh embodiment. Note that the amorphous silicon film was formed with a thickness of 150 nm. (FIG. 20A)
[0299]
Then, using a method described in Japanese Patent Application Laid-Open No. 7-183540, an aqueous solution of nickel acetate (5 ppm by weight, volume: 10 ml) is applied on the semiconductor film by spin coating to form a metal-containing layer 41. I do. Then, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Thus, a semiconductor film 42 was obtained. (FIG. 20 (B))
[0300]
Subsequently, the crystallinity of the semiconductor film 42 is improved by a laser annealing method. The condition of the laser annealing method is that a continuous wave YVO ₄ An elliptical beam 1106 of 200 μm × 50 μm is formed by using the second harmonic (wavelength 532 nm, 5.5 W) of the laser and setting the incident angle φ of the laser beam to the convex lens 1103 in the optical system shown in FIG. . The elliptical beam 1106 is irradiated while moving the substrate at a speed of 20 cm / s or 50 cm / s to improve the crystallinity of the semiconductor film 42. Thus, a semiconductor film 43 is obtained. (FIG. 20 (C))
[0301]
Steps after crystallization of the semiconductor film in FIG. 20C are similar to the steps in FIGS. 18C to 18H shown in the seventh embodiment. Thus, an N-channel TFT 51 and a P-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm are formed. These electrical properties were measured.
[0302]
The electrical characteristics of the TFT manufactured by the above steps are shown in FIGS. FIGS. 21A and 21B show the electrical characteristics of a TFT manufactured by moving the substrate at a speed of 20 cm / s in the laser annealing step of FIG. 20C. FIG. 21A shows the electrical characteristics of the N-channel TFT 51. FIG. 21B shows the electrical characteristics of the P-channel TFT 52. FIGS. 22A and 22B show electrical characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. 20C. FIG. 22A shows the electrical characteristics of the N-channel TFT 51. FIG. 22B shows the electrical characteristics of the P-channel TFT 52. In addition, the measurement conditions of the electric characteristics were a drain voltage Vd = 1 V and 5 V within a range of the gate voltage Vg = −16 to 16 V. 21 and 22, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by dotted lines.
[0303]
Since a crystal grain having a large grain size is formed in a semiconductor film crystallized using the present invention, when a TFT is manufactured using the semiconductor film, the number of crystal grain boundaries included in a channel formation region thereof is increased. Can be reduced. Furthermore, the formed crystal grains are aligned in one direction, and the number of grain boundaries formed in a direction intersecting the relative scanning direction of the laser beam is small. Can be reduced.
[0304]
Therefore, a TFT having good electric characteristics can be obtained as shown in FIGS. In particular, the mobility is 510 cm in the N-channel TFT in FIG. ² / Vs, 200 cm for P-channel TFT ² / Vs, and 595 cm in the N-channel TFT in FIG. ² / Vs, 199 cm for P-channel TFT ² / Vs, which is very excellent. When a semiconductor device is manufactured using such a TFT, the operation characteristics and reliability can be improved.
[0305]
FIG. 23 shows the electrical characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. FIG. 23A shows the electrical characteristics of the N-channel TFT 51. FIG. 23B shows the electrical characteristics of the P-channel TFT 52.
[0306]
In addition, the measurement conditions of the electrical characteristics were as follows: the gate voltage Vg = −16 to 16 V, and the drain voltage Vd = 0.1 V and 5 V.
[0307]
As shown in FIG. 23, a TFT having good electric characteristics can be obtained. In particular, the mobility is 657 cm in the N-channel TFT shown in FIG. ² / Vs, 219 cm in the P-channel TFT shown in FIG. ² / Vs, which is very excellent. When a semiconductor device is manufactured using such a TFT, the operation characteristics and reliability can be improved.
[0308]
This embodiment can be implemented by freely combining with Embodiment Modes 1 to 6 and Embodiments 1 to 4.
[0309]
(Example 9)
In this embodiment, an example of a display system manufactured using the present invention will be described with reference to FIGS.
[0310]
Here, the display system includes a circuit on which a display device and a CPU portion are formed, including a circuit externally provided by an FPC or the like. Embodiments 1 to 6 and Embodiments 1 to 8 are used for the method for manufacturing the display device and the CPU. FIG. 28 shows a configuration example of the display system.
[0311]
A circuit having a configuration as shown in FIGS. 5 and 27 is formed on the substrate 500. Here, an example using a circuit having the configuration shown in FIG. 27 will be described. In the display system 700, the substrate 500 is electrically connected to the power supply circuit 701, the clock oscillation circuit 702, the VRAM 703, the ROM 704, and the WRAM 705 by the FPC 710. Here, the power supply circuit 701 is a circuit that converts a power supply input to the display system 700 into a circuit power supply formed on the substrate 500. The clock oscillation circuit 702 is a circuit that inputs a control signal such as a clock signal to a circuit formed on the substrate 500. The VRAM 703 is a circuit for storing a video signal in a format input to the GPU 507. The ROM 704 is a circuit in which information for controlling the CPU 507 and a video signal input to the display system 700 are stored. The WRAM 705 is a work area for the CPU 507 to perform processing.
[0312]
Note that both the SRAM 504 provided over the substrate 500 and the WRAM 705 connected by the FPC 710 function as a work area of the CPU 507, and thus either one of them can be omitted. For example, when the access from the CPU 507 is large and the storage capacity is relatively small, it is preferable to use the SRAM 504. Conversely, when the large storage capacity is required but the access from the CPU 507 is relatively small, the WRAM 705 is used. Is preferred.
[0313]
(Example 10)
Example 1 In this example, examples of electronic devices manufactured using the present invention will be described with reference to FIGS.
[0314]
Examples of electronic devices manufactured by using the present invention include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (car audio, an audio component, and the like), a notebook personal computer, a game device, and a mobile phone. An information terminal (mobile computer, mobile phone, portable game machine, electronic book, or the like), an image reproducing apparatus provided with a recording medium (specifically, a recording medium such as a digital versatile disc (DVD) is reproduced, and the image is displayed. Device with a display that can be used). FIG. 13 shows specific examples of these electronic devices.
[0315]
FIG. 13A illustrates a display device, which includes a housing 1401, a support base 1402, and a display portion 1403. The present invention can be applied to a display device included in the display portion 1403. By using the present invention, a small and lightweight display device can be realized.
[0316]
FIG. 13B illustrates a video camera, which includes a main body 1411, a display portion 1412, an audio input 1413, an operation switch 1414, a battery 1415, an image receiving portion 1416, and the like. The present invention can be applied to a display device included in the display portion 1412. By using the present invention, a video camera can be reduced in size and weight.
[0317]
FIG. 13C illustrates a laptop personal computer, which includes a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The present invention can be applied to a display device included in the display portion 1423. By using the present invention, a personal computer can be reduced in size and weight.
[0318]
FIG. 13D illustrates a portable information terminal, which includes a main body 1431, a stylus 1432, a display portion 1433, operation buttons 1434, an external interface 1435, and the like. The present invention can be applied to a display device included in the display portion 1433. By using the present invention, a small and lightweight portable information terminal can be realized.
[0319]
FIG. 13E illustrates a sound reproducing device, specifically, an audio device for a vehicle, which includes a main body 1441, a display portion 1442, operation switches 1443 and 1444, and the like. The present invention can be applied to a display device included in the display portion 1442. Also, this time, the in-vehicle audio device has been described as an example, but it may be used for a portable or home audio device. By using the present invention, the size and weight of the sound reproducing device can be reduced.
[0320]
FIG. 13F illustrates a digital camera, which includes a main body 1451, a display portion (A) 1452, an eyepiece 1453, operation switches 1454, a display portion (B) 1455, a battery 1456, and the like. The present invention can be applied to a display device included in the display portion (A) 1452 and the display portion (B) 1455. By using the present invention, a digital camera can be reduced in size and weight.
[0321]
FIG. 13G illustrates a mobile phone, which includes a main body 1461, an audio output portion 1462, an audio input portion 1463, a display portion 1464, operation switches 1465, an antenna 1466, and the like. The present invention can be applied to a display device included in the display portion 1464. By using the present invention, a mobile phone can be reduced in size and weight.
[0322]
Display devices used in these electronic devices can use not only glass substrates but also heat-resistant plastic substrates. Thereby, the weight can be further reduced.
[0323]
The present invention is not limited to the electronic devices described above, and includes various electronic devices using the semiconductor devices manufactured by the manufacturing methods described in Embodiment Modes 1 to 6 and Examples 1 to 8. be able to.
[0324]
【The invention's effect】
A gate metal is partially etched for each of TFTs having different required characteristics to form a gate electrode. That is, for each TFT having different required characteristics, the resist is exposed to form a resist mask, and the gate metal is etched. At this time, the gate electrode fabrication process of each TFT is performed under conditions optimized according to required characteristics. Thus, it is possible to provide a method for manufacturing a semiconductor device in which a plurality of TFTs each having different characteristics or having different design rules can be separately formed over the same substrate.
[0325]
Therefore, circuits having various functions can be manufactured over one substrate. In this way, a circuit that has been conventionally externally mounted with an IC chip or the like can be manufactured on the same substrate, and the device can be reduced in size and weight. Further, since a plurality of TFTs having different characteristics can be separately formed with a smaller number of masks, the number of steps can be reduced, and the cost can be reduced.
[0326]
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 2 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 3 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 4 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a top view of a semiconductor device of the present invention.
FIG. 6 illustrates a method for manufacturing a semiconductor device including a liquid crystal display device or the like of the present invention.
FIG. 7 illustrates a method for manufacturing a semiconductor device including an OLED display device or the like of the present invention.
FIG. 8 illustrates a method for manufacturing a semiconductor device including an OLED display device or the like of the present invention.
FIG. 9 illustrates a method for manufacturing a conventional semiconductor device.
FIG. 10 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 11 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 12 is a circuit diagram illustrating a structure of a pixel portion of a liquid crystal display device.
FIG. 13 illustrates an electronic device of the invention.
FIG. 14 is a schematic view of an optical system used for laser annealing.
FIG. 15 is an SEM observation image of a semiconductor thin film of a TFT formed by the method for manufacturing a semiconductor device of the present invention.
FIG. 16 is an SEM observation image of a semiconductor thin film of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 17 is a graph showing characteristics of a semiconductor active layer of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 18 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 19 illustrates electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 20 illustrates a method for manufacturing a semiconductor device of the present invention.
FIG. 21 is a diagram showing electric characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 22 illustrates electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 23 illustrates electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 24 is a diagram illustrating a shape of a wiring formed by a method for manufacturing a semiconductor device of the present invention.
FIG. 25 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention, following FIG. 4C;
FIG. 26 is a diagram illustrating a method for manufacturing a semiconductor device of the present invention, following FIG. 4C;
FIG. 27 is a top view of a semiconductor device of the present invention.
FIG. 28 is a diagram illustrating a display system using the semiconductor device of the present invention.

Claims (8)

In a method for manufacturing a semiconductor device in which a conductive layer is formed and patterned on an insulating surface to form a wiring,
Forming a first resist mask by first exposure means;
Using the first resist mask, etching a first region of the conductive layer to form a first wiring;
Forming a second resist mask by a second exposure unit having a higher resolution than the first exposure unit;
The second resist mask is used to etch a second region of the conductive layer and a part of the first wiring to form a second wiring connected to the first wiring. Of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a conductive layer is formed and patterned on an insulating surface to form a wiring,
Forming a first resist mask by a 1: 1 projection exposure apparatus;
Using the first resist mask, etching a first region of the conductive layer to form a first wiring;
Forming a second resist mask by a reduction projection exposure apparatus;
The second resist mask is used to etch a second region of the conductive layer and a part of the first wiring to form a second wiring connected to the first wiring. Of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a conductive layer is formed and patterned on an insulating surface to form a wiring,
Forming a first resist mask by first exposure means;
Using the first resist mask, etching a first region of the conductive layer to form a first wiring;
Forming a second resist mask by a second exposure unit having a shorter wavelength of light used by the first exposure unit;
The second resist mask is used to etch a second region of the conductive layer and a part of the first wiring to form a second wiring connected to the first wiring. Of manufacturing a semiconductor device. In a method for manufacturing a semiconductor device in which a conductive layer is formed over an insulating surface and patterned to form a wiring,
Forming a first resist mask by first exposure means;
Using the first resist mask, a first region of the conductive layer is etched to form a first wiring having a tapered end.
Forming a second resist mask by a second exposure means;
Using the second resist mask, a second region of the conductive layer and a part of the first wiring are etched, and a second end connected to the first wiring has a vertical end. A method for manufacturing a semiconductor device, wherein a wiring is formed. In a method for manufacturing a semiconductor device in which a conductive layer is formed over an insulating surface and patterned to form a wiring,
Forming a first resist mask by first exposure means;
Using the first resist mask, a first region of the conductive layer is etched to form a first wiring having a tapered end.
Forming a second resist mask by a second exposure unit having a higher resolution than the first exposure unit;
Using the second resist mask, a second region of the conductive layer and a part of the first wiring are etched, and a second end connected to the first wiring has a vertical end. A method for manufacturing a semiconductor device, wherein a wiring is formed. In claim 4 or claim 5,
A method of manufacturing a semiconductor device, wherein the first exposure means uses a 1: 1 projection exposure apparatus, and the second exposure means uses a reduction projection exposure apparatus. In claim 4 or claim 5,
A method for manufacturing a semiconductor device, wherein a wavelength of light used for the second exposure means is shorter than a wavelength of light used for the first exposure means. An electronic device manufactured using the method for manufacturing a semiconductor device according to claim 1.

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