JP2003229433A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device which can form a plurality of TFTs having different characteristics on the same substrate. <P>SOLUTION: A gate metal is formed and the gate metal is partially etched for every TFT of required different characteristics to form the gate electrode. Namely, a resist mask is formed through exposure of resist for every TFT of required different characteristics. Using the resist mask, the gate metal is etched for every TFT of required different characteristics. In this case, the gate metal covering a semiconductor active layer of the TFT other than those where gate electrodes are being patterned is still covered with the resist. The gate electrode of each TFT can be formed under the optimized condition conforming to the required characteristics. Moreover, an impurity element is doped, as required, to the source region, drain region, Lov region and Loff region. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device including a thin film transistor. In particular, the present invention relates to a method for manufacturing a semiconductor device which has a plurality of circuits and is driven by different power supply voltages. Further, the present invention relates to an electronic device using the semiconductor device.

2. Description of the Related Art In recent years, a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film formed on a substrate having an insulating surface.
(Hereinafter, referred to as “)”, and a semiconductor device having a circuit formed of TFTs is under development. As a typical example of a semiconductor device having a circuit formed of TFTs, an active matrix liquid crystal display device or an active matrix O
An LED (Organic Light Emitting Diode) display device and the like are known.

Here, an example of a method for manufacturing a TFT will be given. FIG. 9 is used for the description.

As shown in FIG. 9A, a polycrystalline semiconductor film formed by a method such as crystallizing an amorphous semiconductor film is patterned on a substrate 1101 having an insulating surface to form a semiconductor. Active layers 1102c and 1
102d is formed. Semiconductor active layers 1102c and 1
An insulating film 1103, a conductive film 1104, and
A resist 1186 is formed. Since the gate electrode of the TFT is formed by the conductive film 1104, the conductive film 110
4 is also called a gate metal. In addition, in FIG.
An example in which the gate metal is formed to have a single-layer structure of the conductive film 1104 is shown.

After forming the resist 1186, a resist mask for patterning the gate metal is prepared. The resist 1186 is exposed with a pattern to expose the resist 1186. Then, by developing, masks (resist masks) 1123 and 1124 made of resist as shown in FIG. 9B are formed.
Conductive film 1 using resist masks 1123 and 1124
Etch 104. Thus, the gate electrode 112
1 and the gate electrode 1122 are produced. Then N
An impurity element imparting a mold is doped (doping 1). Thus, the semiconductor active layers 1102c and 1102d
N-type impurity regions 1125a, 1125b, 112
6a, 1126b are formed.

Next, as shown in FIG. 9C, the resist masks 1123 and 1124 are removed and a new resist mask 1128 is formed. After that, an impurity element imparting P-type conductivity is doped (doping 2). Thus, the impurity region 1129 is formed in the semiconductor active layer 1102d.
a, 1129b are formed. Here, the impurity region 11
N-type impurity elements in doping 1 are added to 29a and 1129b. However, by adding a P-type impurity element at a high concentration in doping 2, the impurity regions 1129a and 1129b are P-channel type.
It functions as a source region and a drain region of the TFT without any problem.

In this way, the N-channel type TFT,
A P-channel type TFT can be formed.

[0007]

In recent years, a TFT having a crystalline semiconductor film (typically a polycrystalline film) as an active layer (hereinafter, referred to as
The characteristics such as field effect mobility of the polycrystalline TFT) are improved. Therefore, it is becoming possible to form circuits having various functions using the TFT.
Therefore, it is expected and attempted to form a circuit, which has been conventionally formed on a single crystal substrate, on a substrate having an insulating surface such as a glass substrate using a TFT. For example, on a substrate on which pixels of a display device such as a liquid crystal display device are formed, an arithmetic processing circuit using TFTs,
It is expected to form memory elements and the like.

Here, when various circuits are formed using TFTs on the same substrate having an insulating surface, the characteristics required for the TFTs forming the circuits differ depending on the function of each circuit. . Therefore, TF with different characteristics
It is necessary to make T differently. Hereinafter, the difference in characteristics required for the TFTs forming the circuit according to the function of the circuit will be described with reference to specific examples.

For example, a case where an active matrix type liquid crystal display device and an arithmetic processing circuit are to be formed on the same substrate by using TFTs will be described as an example. An active matrix type liquid crystal display device includes a pixel portion configured by a plurality of pixels arranged in a matrix and a drive circuit portion (hereinafter, referred to as a pixel drive circuit portion) that inputs a video signal to the pixel portion. Have.

FIG. 12 shows an example of the configuration of a pixel portion of an active matrix type liquid crystal display device. A plurality of signal lines S1 to Sx and scanning lines G1 to Gy are arranged in the pixel portion. Pixels are arranged at the intersections of the signal lines S1 to Sx and the scanning lines G1 to Gy. Each pixel has a switching element. The switching elements include scan lines G1 to Gy.
The input of the video signal input to the signal lines S1 to Sx to each pixel is selected according to the signal input to the pixel. In FIG. 12, a TFT (hereinafter referred to as a pixel TFT) 3002 is shown as the switching element. In addition, the signal line S1
From Sx to Sx, a storage capacitor 3001 that holds a signal input to a pixel and a liquid crystal element 3003 whose transmittance changes according to a video signal input through a pixel TFT 3002 are included.

In each pixel, the gate electrode of the pixel TFT 3002 is connected to one of the scanning lines G1 to Gy.
One of a source region and a drain region of the pixel TFT 3002 is connected to one of the signal lines S1 to Sx, and the other is connected to one electrode of the storage capacitor 3001 and the liquid crystal element 3.
003 to one electrode.

The pixel TFT 3002 forming a pixel is required to have a small off current. This is to prevent the leakage current from changing the voltage applied between the electrodes of the liquid crystal element 3003 arranged in each pixel, changing the transmittance, and disturbing the image. Also, the pixel TFT 3002
In a liquid crystal display device of a type in which an image is visually recognized through the liquid crystal display device (hereinafter, referred to as a transmission type), the pixel T
It is required to miniaturize the FT3002. further,
A voltage of about 16 V is usually applied between the electrodes of the liquid crystal element 3003. Therefore, the pixel TFT 3002 and the like are required to have a withstand voltage of about 16V. Therefore, the TF having a structure including a low-concentration impurity region (hereinafter referred to as a Lov region) which overlaps with the gate electrode and a low-concentration impurity region (hereinafter referred to as a Loff region) which does not overlap with the gate electrode
It is desirable to set to T.

On the other hand, a TFT which constitutes a pixel drive circuit section
(Hereinafter, referred to as a pixel drive circuit TFT) is a pixel T
The reduction of off-current and miniaturization are not required as much as FT. However, since it operates with a power supply voltage of about 16 V, withstand voltage is required.

A high driving frequency is required in the arithmetic processing circuit. Therefore, the TFT forming the arithmetic circuit is required to have improved carrier mobility and miniaturization. on the other hand,
The arithmetic circuit manufactured by the miniaturized TFT is 3 to 5
It becomes possible to operate with a power supply voltage of about V, and the withstand voltage of the TFT is not required as much as the pixel TFT or the pixel drive circuit TFT.

It is necessary to manufacture different TFTs according to the above-mentioned required characteristics.

Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which has different characteristics on the same substrate or different TFTs and different design rules from each other. .

[0017]

In order to solve the above-mentioned problems, the present invention takes the following measures.

A method for producing a gate electrode is to form a gate metal, and partially etch the gate metal for each TFT having different required characteristics. That is, a resist mask is produced by exposing the resist for each TFT having different required characteristics. Using the resist mask, the gate metal is etched for each TFT having different required characteristics. Here, the gate metal which covers the semiconductor active layer of the TFT other than the TFT whose gate electrode is being patterned is covered with a resist mask. Each TF
The gate electrode manufacturing process of T may be performed under conditions optimized according to the required characteristics.

Here, the deposited gate metal may have a single layer structure, a laminated structure of two layers, or a multilayer structure of two or more layers.

The steps up to gate metal film formation can be the same for TFTs formed on the same substrate. Further, in all TFTs formed on the same substrate, it is possible to use the same process after forming the gate electrode. Note that it is not always necessary that all TFTs formed on the same substrate have the same steps except for the gate electrode formation. Some of the steps can be common. Thus, with fewer masks,
It is possible to create a plurality of TFTs having different characteristics.

The shape of the gate electrode to be formed can be changed by changing the method of etching the gate metal for each TFT having different required characteristics. For example, a TFT having a gate electrode having a shape having a tapered end portion and a TFT having a gate electrode having a shape having a substantially vertical end portion.
And can be made differently. In a TFT provided with a gate electrode having a tapered end portion, it is possible to dope an impurity element through the tapered portion and form a low-concentration impurity region in a self-aligned manner. Therefore,
It is possible to obtain a TFT having a structure with excellent pressure resistance. Here, it is difficult to reduce the gate length and the gate width in a TFT having a tapered gate electrode at the end. That is, it is not suitable for miniaturization. On the other hand, a TFT provided with a gate electrode having a shape having substantially vertical ends has a shape suitable for miniaturization. Thus, the shape of the gate electrode of the TFT can be changed according to the required characteristics.

The wiring can be formed by etching the gate metal at the same time as forming the gate electrode having the tapered end portion. The shape of this wiring has a tapered end. A wiring having a tapered end portion prevents disconnection of a film formed on the wiring,
Defects can be reduced.

The wiring can be formed by etching the gate metal at the same time as forming the gate electrode having a shape having substantially vertical ends. The shape of this wiring has substantially vertical ends. The wiring having a substantially vertical end portion has a ratio L / L between the wiring width (L) and the wiring interval (S) as compared with a wiring having a tapered end portion having the same cross-sectional area.
It is possible to reduce S. Therefore, the wiring having the vertical end portion has a shape suitable for integration. Thus, the shape of the wiring can be changed according to the portion of the semiconductor device.

Further, the exposure means of the resist used when patterning the gate electrode is changed for each TFT having different required characteristics. In this way, the patterning resolution of the gate electrode can be changed. Note that the exposure means indicates an exposure condition and an exposure device. The exposure apparatus has a radiant energy source (optical power source, electron beam source, or X-ray source) for exposing the resist, and the radiant energy source is used to expose the pattern on the original image (reticle or mask) onto the resist. Device. As the usable exposure apparatus, a reduction projection exposure apparatus (commonly known as a stepper)
Another example is a mirror projection type exposure apparatus (hereinafter, referred to as MPA) which is a 1 × projection exposure apparatus, but is not limited thereto. A known exposure device can be used freely. The exposure conditions include the wavelength of the radiant energy source used for the exposure, the magnification for exposing the resist to the original image (reticle or mask), the resist material, the exposure time, and the like.

Further, in order to form a source region, a drain region, a Lov region, a Loff region, etc. of each TFT, doping with an impurity element is performed as necessary.

An example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. A typical example of a method for manufacturing a semiconductor device of the present invention is shown in FIG. In FIG. 1A, a first TFT having different required characteristics
A process of manufacturing the first TFT and the second TFT on the same substrate will be described.

A gate insulating film, a gate metal, and a resist are sequentially formed in common on each semiconductor active layer of the first TFT and the second TFT (gate metal and resist film formation). After that, the first exposure is performed and the first TFT is
A resist mask for forming the gate electrode of is formed. After that, the gate metal is etched using the resist mask to manufacture the gate electrode of the first TFT (manufacture of the gate electrode of the first TFT). After that, doping with an impurity element is performed. The gate metal on the semiconductor active layer corresponding to the second TFT is covered with a resist mask so as not to be etched while performing steps such as the first exposure, the formation of the gate electrode, and the doping with respect to the first TFT. .

Next, after removing the resist mask, a new resist film is formed so as to cover the regions for forming the first TFT and the second TFT (resist film formation).
After that, second exposure is performed to form a resist mask for forming a gate electrode of the second TFT. After that, the gate metal is etched using the resist mask to form the gate electrode of the second TFT (second
Fabrication of TFT gate electrode). After that, doping with an impurity element is performed. For the second TFT, the second exposure,
The gate metal on the semiconductor active layer corresponding to the first TFT is covered with a resist mask so as not to be etched while performing steps such as fabrication of the gate electrode and doping.

Thus, the first TFT and the second TFT
Make differently.

Each TFT (first TFT, second T
FT) In the step of forming each gate electrode, the gate metal may be etched stepwise, and the impurity element doping step may be performed in the meantime.

In the following, an example in which the gate metal is etched stepwise in the step of forming the gate electrodes of the first TFT and the second TFT, and the impurity element doping step is performed in the meantime is shown in FIG. Shown in. Note that in FIG. 1D, only the manufacturing process of the gate electrode of either the first TFT or the second TFT will be focused and described.

As shown in FIG. 1D, after the first gate metal etching (gate metal etching 1), the impurity element is doped. Next, after the second gate metal etching (gate metal etching 2) is performed, doping with an impurity element is performed. Further, the gate electrode is produced by the third etching of the gate metal (gate metal etching 3).

Here, in the above two times of doping,
The shape of the gate metal serving as a mask in doping with an impurity element is changed. Thus, in the semiconductor active layer,
It is possible to form a region to which the impurity element is added by both of the two dopings and a region to which the impurity element is added only by the doping process after the gate metal etching 2. In this way, a region in which the impurity element is added at a high concentration and a region in which the impurity element is added at a low concentration are formed in the semiconductor active layer.

The process as shown in FIG.
It may be performed in the step of forming the gate electrode in (A) (the step of forming the gate electrode of the first TFT and the step of forming the gate electrode of the second TFT).

The subsequent step of doping the impurity element is not always necessary for the TFT in which the gate manufacturing step as shown in FIG. 1D is performed.

FIG. 1B shows an example of a method for manufacturing a semiconductor device of the present invention which is different from that in FIG. In the process shown in FIG. 1A, each TFT (first TFT, second TF
After forming the gate electrode of T), doping with an impurity element is performed. However, in the manufacturing method shown in FIG. 1B, after the gate electrode of the first TFT is manufactured, the gate electrode of the second TFT is manufactured without doping the impurity element. Then, finally, the first TFT and the second TFT are manufactured by performing the step of doping the impurity element in common for the first TFT and the second TFT. In the step shown in FIG. 1B, the number of times of doping is smaller than that in FIG. 1A, and the number of manufacturing steps can be reduced.

FIG. 1C is an example of a method for manufacturing a semiconductor device of the present invention, which is different from those in FIGS. 1A and 1B. Figure 1
The manufacturing method illustrated in (C) is a combination of the manufacturing method illustrated in FIG. 1A and the manufacturing method illustrated in FIG. In other words, this is a manufacturing method in which part of the doping step in manufacturing the first TFT and part of the doping step in manufacturing the second TFT are performed at the same time. Since part of the doping step of the manufacturing process of the first TFT and the manufacturing process of the second TFT is performed at the same time, the manufacturing process can be simplified as compared with the manufacturing method of FIG. On the other hand, since the doping process is performed in each of the manufacturing process of the first TFT and the manufacturing process of the second TFT, the condition for doping the impurity element is set to the first in the manufacturing method of FIG. It is also possible to change the TFT and the second TFT.

Each TFT (first TFT, second T
FT) In the step of forming each gate electrode, the gate metal may be etched stepwise, and the impurity element doping step may be performed in the meantime. For example, in FIG.
The step as shown in FIG. 1D may be performed in the step of forming the gate electrode in FIG. 1C (step of forming the gate electrode of the first TFT and step of forming the gate electrode of the second TFT). The subsequent step of doping the impurity element is not always necessary for the TFT in which the gate manufacturing step shown in FIG. 1D is performed.

In each of the manufacturing methods shown in FIGS. 1A to 1C, the exposure means used in the first exposure step and the exposure means used in the second exposure step are the same. Can be different or different. An exposure means used in the first exposure step and an exposure means used in the second exposure step,
The following are examples of making them different.

For example, for the first TFT, the second T
When FT is required to be finer, the wavelength of light used in the second exposure step is shorter than the wavelength of light used in the first exposure step. Also, for example, the first TF
When the second TFT is required to be finer than T, exposure is performed using MPA in the first exposure step and exposure is performed using a stepper in the second exposure step. .

A method of changing the exposure means in the formation of the resist mask for forming the gate electrodes of the first TFT and the second TFT will be described with reference to FIG.

As shown in FIG. 11A, a TFT (first TFT) having a gate electrode patterned on a substrate by a resist mask obtained by the first exposure process.
Region (first region) and a region (second region) having a TFT (second TFT) whose gate electrode is patterned by the resist mask obtained by the second exposure process.
Area).

Here, it is desirable that the fabrication of the gate electrode of the first TFT and the fabrication of the gate electrode of the second TFT be performed after the fabrication of the gate electrode of the TFT that requires miniaturization. Thus, the wiring formed by etching the gate metal in the step of forming the gate electrode of the first TFT and the wiring formed by etching the gate metal in the step of forming the gate electrode of the second TFT. It is possible to connect and smoothly.

Further, each of the first exposure step and the second exposure step may be performed using a plurality of exposure means. For example, as shown in FIG. 11B, a region (first region) where the gate electrode is patterned by the resist mask obtained by the first exposure process is used as the first exposure means and the first exposure. It is possible to perform patterning using a resist mask formed by using both the second exposure means different from the means. That is, after forming a resist film that can be commonly used for both the first exposure unit and the second exposure unit, exposure is performed by the first exposure unit in the first region.
After that, exposure is performed by the second exposure unit. Finally, development may be performed to form a resist mask.

In each of the manufacturing process of the first TFT and the manufacturing process of the second TFT in FIG. 1, a resist mask is newly formed in addition to the resist mask required for etching the gate metal, and a specific region is selected. An impurity element may be added as an option. In this way, it is possible to form an impurity region which is not formed by the gate electrode in a self-aligned manner.

In addition, a sidewall may be formed on the side surface of the gate electrode with an insulator. Further, the LDD region may be formed by adding an impurity element using the sidewall as a mask. In particular, when forming an LDD region or the like in a TFT that requires miniaturization, the mask using the above-described sidewall method can align the mask more accurately than forming the LDD region using a resist mask. Therefore, it is preferable.

In the step of manufacturing the gate electrode of the first TFT shown in FIG. 1, the gate electrodes corresponding to two TFTs having different polarities may be manufactured at the same time. Further, in the step of manufacturing the gate electrode of the second TFT in FIG. 1, gate electrodes corresponding to two TFTs having different polarities may be manufactured at the same time. At this time, in the manufacturing process of the first TFT and the manufacturing process of the second TFT, T of each polarity is used.
It is necessary to change the doping condition of the impurity element according to the FT. Therefore, a resist mask may be newly formed in addition to the resist mask required for etching the gate metal, and the impurity element may be selectively added to a specific region.

The semiconductor film forming the semiconductor active layers of the first TFT and the second TFT may be crystallized by laser annealing using continuous wave laser light.

Although FIG. 1 shows a process of separately forming the gate electrode of the TFT by two exposure processes (first exposure and second exposure), the present invention is not limited to this.
The present invention has a plurality of exposure steps, and can be applied to a step of forming a gate electrode of a TFT for each exposure step.

In this way, it is possible to provide a method for manufacturing a semiconductor device in which a plurality of TFTs having different characteristics or different design rules can be separately manufactured on the same substrate.

According to the present invention, circuits having various functions can be manufactured on the same substrate. In this way, it is possible to fabricate a circuit, which has been conventionally mounted externally with an IC chip or the like, on the same substrate, and to reduce the size and weight of the device. In addition, since it is possible to separately produce a plurality of TFTs having different characteristics with a smaller number of masks, it is possible to reduce an increase in the number of steps and keep costs low.

[0052]

(Embodiment Mode 1) In this embodiment mode, an example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. Note that the manufacturing process example shown in Embodiment Mode 1 is different from that shown in FIG.
This corresponds to the example shown in (C). In particular, in manufacturing the gate electrode of the first TFT in FIG.
This corresponds to an example in which the step of the pattern shown in (3) is used and the doping immediately after the gate electrode of the first TFT is formed is omitted.

In FIG. 2A, as the substrate 101, a quartz substrate, a silicon substrate, a metal substrate or a stainless steel substrate having an insulating film formed on its surface is used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this manufacturing process may be used. In this embodiment mode, a substrate 101 made of glass such as barium borosilicate glass or aluminoborosilicate glass is used.

Next, a base film (not shown) made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed on the substrate 101. The base film may have a single-layer structure of the insulating film or a structure in which two or more insulating films are laminated.

In this embodiment, the first layer of the base film is used.
By using plasma CVD method _Four, NH₃, And N
₂A silicon nitride oxide film formed by using O as a reaction gas
~ 200nm (preferably 50-100nm)
To do. In this embodiment mode, a silicon oxynitride film is formed to a thickness of 50 nm.
To form. Next, plasma is used as the second layer of the base film.
SiH using CVD method_FourAnd N₂O as a reaction gas
The silicon oxynitride film to be formed is 50 to 200 nm (preferably,
It is formed to a thickness of 100 to 150 nm). In this embodiment
Forms a silicon oxynitride film with a thickness of 100 nm.

Subsequently, a semiconductor film is formed on the base film. The semiconductor film has a thickness of 25 to 80 nm (preferably 30) by known means (sputtering method, LPCVD method, plasma CVD method, etc.).
A semiconductor film is formed to a thickness of 60 nm). Next, the semiconductor film is crystallized by a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing, thermal crystallization method using a metal element that promotes crystallization, etc.). Note that the thermal crystallization method using a metal element that promotes crystallization and the laser crystallization method may be combined. For example, the laser crystallization method may be performed after the thermal crystallization method using a metal element that promotes crystallization.

Then, the obtained crystalline semiconductor film is patterned into a desired shape to form a semiconductor layer (semiconductor active layer) 10
2a to 102d are formed. As the semiconductor layer,
A compound semiconductor film having an amorphous structure such as an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, or an amorphous silicon germanium film can be used.

In this embodiment mode, an amorphous silicon film having a film thickness of 55 nm is formed by using the plasma CVD method. And
A solution containing nickel was held on the amorphous silicon film, and the amorphous silicon film was dehydrogenated (500 ° C., 1 hour) and then thermally crystallized (550 ° C., 4 hours). A crystalline silicon film is formed. Then, the island-shaped semiconductor layer 102a is subjected to patterning processing using a photolithography method.
To form 102d.

As a laser for forming a crystalline semiconductor film by a laser crystallization method, a continuous wave or pulsed gas laser or solid laser may be used. Examples of the former gas laser include excimer laser, YAG laser, and YVO.
₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, etc. can be used. As the latter solid-state laser, Cr,
A laser using a crystal of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with Nd, Er, Ho, Ce, Co, Ti or Tm can be used. The fundamental wave of the laser depends on the doping material, 1 μm
Laser light having front and rear fundamental waves can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element. In order to obtain crystals with a large grain size when crystallizing the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and to apply the second to fourth harmonics of the fundamental wave. . Typically, the second harmonic (532 nm) or the third harmonic (355 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) is applied.

The laser light emitted from the continuous oscillation YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. Further, there is also a method of emitting a harmonic by inserting a YVO ₄ crystal and a non-linear optical element in the resonator. Then, preferably, a rectangular or elliptical laser beam is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. Energy density at this time is 0.01-100 MW
/ Cm ² (preferably 0.1 to 10 MW / cm ² ) is required. Then, the semiconductor film is moved relative to the laser beam at a speed of about 10 to 2000 cm / s for irradiation.

When the above laser is used, it is advisable that the laser beam emitted from the laser oscillator is linearly condensed by an optical system and irradiated onto the semiconductor film. The crystallization conditions are appropriately set. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 700 mJ / cm ² (typically 200 to 300 mJ / cm
² ) is good. When using a YAG laser,
Pulse oscillation frequency 1 to 300Hz using the second harmonic
And the laser energy density is 300 to 1000 mJ / c
m ² (typically 350 to 500 mJ / cm ² ) is recommended. And a width of 100 to 1000 μm (preferably a width of 400 μm
It is also possible to irradiate the laser beam condensed linearly in m) over the entire surface of the substrate and set the overlapping rate (overlap rate) of the linear beams at this time to 50 to 98%.

However, in this embodiment, since the amorphous silicon film is crystallized by using the metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and a heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed to form the amorphous silicon film in the amorphous silicon film. The metal element is diffused, and the amorphous silicon film is removed by etching after heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed.

After forming the island-shaped semiconductor layers 102a to 102d, a slight amount of impurity element (boron or phosphorus) may be doped. Thus, the threshold value of the TFT can be controlled by adding a slight amount of the impurity element also to the region which will be the channel region.

Next, a gate insulating film 103 which covers the semiconductor layers 102a to 102d is formed. Gate insulating film 103
Is formed by plasma CVD or sputtering to a film thickness of 40
It is formed of an insulating film containing silicon having a thickness of 150 nm. In this embodiment mode, plasma CVD is used as the gate insulating film 103.
A silicon oxynitride film is formed to a thickness of 115 nm by the method.
Of course, the gate insulating film 103 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure. Note that when a silicon oxide film is used as the gate insulating film 103, T
EOS (Tetraethyl Orthosilicate) and O ₂ are mixed, reaction pressure is 40 Pa, substrate temperature is 300 to 400 ° C.,
High frequency (13.56MHz), power density 0.5-0.8W / c
It may be formed by discharging at m ² . The silicon oxide film formed through the above steps can be provided with favorable characteristics as the gate insulating film 103 by subsequent thermal annealing at 400 to 500 ° C.

Here, an impurity element may be doped in a specific region of the semiconductor layers 102a to 102d before forming the gate electrode. By forming the gate electrode so as to overlap the impurity region formed at this time, the Lov region or the like can be formed. The semiconductor layer 10
When doping 2a to 102d with an impurity element, an insulating film (referred to as a doping insulating film) other than the gate insulating film 103 may be formed. In this case, after the doping process is completed, the doping insulating film is removed.

Next, the first conductive film 104a is formed of TaN to a thickness of 20 to 100 nm, and the second conductive film 104b is formed.
Is formed with W to a thickness of 100 to 400 nm. Thus
A gate metal having a two-layer laminated structure is formed. In this embodiment mode, a first conductive film 104a formed of a TaN film having a thickness of 30 nm and a second conductive film 104b formed of a W film having a thickness of 370 nm are stacked.

In this embodiment mode, the first conductive film 104a is used.
The TaN film is formed by sputtering using a Ta target in an atmosphere containing nitrogen. The W film which is the second conductive film 104b is formed by a sputtering method using a W target. In addition, tungsten hexafluoride (W
It can also be formed by a thermal CVD method using F ₆ ). In any case, it is necessary to reduce the resistance in order to use it as the gate electrode, and it is desirable that the resistivity of the W film is 20 μΩcm or less. Although the resistivity of the W film can be lowered by enlarging the crystal grains, when the W film contains many impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in the present embodiment, high-purity W (purity 9
9.9999%) target sputtering method,
Further, by forming the W film with sufficient consideration so that impurities are not mixed from the vapor phase during film formation, the resistivity of 9 to 2 is obtained.
Achieve 0μΩcm.

In this embodiment, the first conductive film 10 is used.
4a is a TaN film and the second conductive film 104b is a W film, but the material forming the first conductive film 104a and the second conductive film 104b is not particularly limited. First conductive film 104
a and the second conductive film 104b are made of Ta, W, Ti, M.
It may be formed of an element selected from o, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Further, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or AgPd
It may be formed of a Cu alloy.

Next, a resist 105 is formed. As a film forming method of the resist 105, a coating method can be used. A spin coater or a roll coater may be used for the coating method. The resist 105 can be either a positive type or a negative type, and can be selected according to the light source used at the time of exposure.

Next, as shown in FIG. 2B, the resist 105 is exposed (first exposure) to form the resist mask 10.
8, 109 and 185 are formed, and a first etching process (gate metal etching 1) for forming a gate electrode is performed. In the present embodiment, as the etching method of the first etching process, ICP (Inductively Coupling) is used.
led plasma: an inductively coupled plasma) etching method is used, CF ₄ and Cl ₂ are mixed as an etching gas, and a coil-type electrode is RF 500 W (13.56 MH) at a pressure of 1 Pa.
z) Power is supplied to generate plasma. 100W RF (13.56MHz) on the substrate side (sample stage)
Power is applied and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

However, the first conductive film 104a and the second conductive film 104 formed on the semiconductor layers 102c and 102d.
Since the portion b is covered with the resist mask 185, it is not etched.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, and the first conductive layer 106a, 106a, due to the effect of the bias voltage applied to the substrate side.
The ends of 107a and the second conductive layers 106b and 107b are tapered. Here, the angle (taper angle) of the portion having a tapered shape (tapered portion) means the substrate 10.
1 It is defined as the angle formed by the surface (horizontal plane) and the inclined part of the tapered part. By appropriately selecting the etching conditions, the angle of the tapered portions of the first conductive layer and the second conductive layer can be set to 15 to 45 °. Gate insulating film 1
In order to etch without leaving a residue on 03,
It is advisable to increase the etching time at a rate of about 10 to 20%. The selection ratio of the silicon oxynitride film to the W film is 2
4 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is 20 to 50 due to the overetching treatment.
It will be etched by about nm. Thus, the first shape conductive layers 106 and 107 (the first conductive layers 106a and 107a and the second conductive layers 106b and 107) including the first conductive layer and the second conductive layer are formed by the first etching treatment.
b) is formed. At this time, in the gate insulating film 103, the exposed region is etched by about 20 to 50 nm to form a thinned region.

Then, the first doping process (dope
1) is performed and an impurity element imparting N-type is added. Do
Ion doping method or ion implantation method
You can go in. The condition of the ion doping method is a dose of 1 ×
10¹³~ 5 x 10¹⁴atoms / cm ²And the acceleration voltage is 60-
It is performed at 100 kV. As an impurity element that imparts N-type
Group 15 elements, typically phosphorus (P) or arsenic
(As) is used, but phosphorus (P) is used here. This
In the case of, the first shape conductive layers 106 and 107 (first conductive layers) are formed.
Conductive layers 106a, 107a and second conductive layers 106b, 10
7b) is used as a mask for the impurity element imparting N-type
The first impurity regions 110a and 110 in a self-aligning manner.
b, 111a, 111b are formed. First impurity region
1 × 1 in areas 110a, 110b, 111a, 111b
0²⁰~ 1 x 10^{twenty one}atoms / cm³N type is given in the concentration range of
Impurity element is added.

Next, as shown in FIG. 2C, a second etching process (gate metal etching 2) is performed without removing the resist mask. CF as etching gas
_The W film is selectively etched using ₄ , Cl ₂ and O ₂ . Thus, the second shape conductive layers 412 and 413 (first conductive layers 412a and 412) are formed by the second etching treatment.
3a and second conductive layers 412b, 413b) are formed.
At this time, in the gate insulating film 103, the exposed region is further etched and thinned by about 20 to 50 nm.

The etching reaction of the W film or the Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the radical or ion species generated and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluoride and chloride of W and Ta,
WF ₆ which is a fluoride of
l ₅ , TaF ₅ , and TaCl ₅ are in the same level. Therefore, C
Both the W film and the Ta film are etched by the mixed gas of F ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, Ta has a relatively small increase in etching rate even if F increases. Moreover, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since Ta oxide does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, W film and Ta
It becomes possible to make a difference in the etching rate from the film, and W
The etching rate of the film can be made higher than that of the Ta film.

Then, a second doping process (doping 2) is performed. In this case, the dose amount is lower than that in the first doping process, and the impurity element imparting N-type is doped under the condition of high acceleration voltage. For example, the acceleration voltage is 70 to 120 kV, and the dose is 1 × 10 ¹³ atoms / cm ² , and the first semiconductor layer is formed on the island-shaped semiconductor layer in FIG. 2B.
Impurity regions 110a, 110b, 111a, 111b of
A new impurity region is formed inside. Doping is
The second conductive layers 412b and 413b are used as masks for the impurity element, and doping is performed so that the impurity element is also added to the semiconductor layers in the regions below the first conductive layers 412a and 413a. Thus, the second impurity region 416
a, 416b, 418a, 418b are formed. The second impurity regions 416a, 416b, 418a, 41
The concentration of phosphorus (P) added to 8b is the same as that of the first conductive layer 4
There is a gradual concentration gradient according to the film thickness of the tapered portions 12a and 413a. Note that the first conductive layer 412a,
In the semiconductor layer which overlaps with the tapered portion of 413a, the first
Although the impurity concentrations are slightly lowered from the ends of the tapered portions of the conductive layers 412a and 413a toward the inside, the concentrations are almost the same.

Then, as shown in FIG. 2D, a third etching process (gate metal etching 3) is performed. CHF ₆ is used as an etching gas and a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 412a and 413a are partially etched, so that the region where the first conductive layer and the semiconductor layer overlap with each other is reduced. By the third etching treatment, the third shape conductive layers 112 and 113 (the first conductive layers 112a and 113a and the second conductive layers 112b and 113) are formed.
b) is formed. At this time, in the gate insulating film 103, the exposed region is further etched and thinned by about 20 to 50 nm. The second etching is performed by the third etching process.
Impurity regions 416a, 416b, 418a, 418b of
Are second impurity regions 117a, 117b, 119a, 119b overlapping the first conductive layers 112a, 113a, and
Third impurity regions 116a, 116b, 118a, 118b are formed between the first impurity region and the second impurity region.

Next, as shown in FIG. 2E, after removing the resist masks 108, 109 and 185, a new resist 186 is formed. As a film forming method of the resist 186, a coating method can be used. A spin coater or roll coater may be used for the coating method. The resist 186 can be either a positive type or a negative type and can be selected according to the light source used at the time of exposure. The resist 186 may be made of the same material as the resist 105 used in the first exposure, or may be different.

Next, the resist 186 is exposed (second exposure) to form resist masks 123, 124 and 187 (FIG. 2 (F)). The exposure means in the second exposure may be the same as or different from the first exposure. Then, a fourth etching process (gate metal etching 4) is performed. Thus, the fourth shape conductive layers 121 and 122 (first conductive layers 121a and 122a, second conductive layers 121b and 122) having substantially vertical ends are formed.
b) is formed. Note that the semiconductor layers 102a and 102b
The third shape conductive layers 112 and 113 (first conductive layers 112a and 113a, second conductive layer 112) formed thereover.
The part (b, 113b) is covered with the resist mask 187 and is not etched.

After that, a third doping process (doping 3) is performed. In the third doping process, an impurity element imparting N-type is added. The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atom.
s / cm ² and accelerating voltage of 60 to 100 kV. N
As the impurity element imparting the type, an element belonging to Group 15 is used, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the resist masks 123, 124, and 187 are used as masks for the impurity element imparting N-type conductivity, and the fourth impurity regions 125 a and 1
25b, 126a, 126b are formed. 1 in the fourth impurity regions 125a, 125b, 126a, 126b
An impurity element imparting N-type is added in a concentration range of × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Note that the semiconductor layer 102
Since a and 102b are covered with the resist mask 187, the impurity element is not added in the third doping process.

In the present embodiment, the conditions for doping the fourth impurity regions 125a, 125b, 126a, 126b with the impurity element (third doping process) are as follows.
First impurity regions 110a, 110b, 111a, 11
The conditions for doping the impurity element 1b (first doping process) are the same. However, it is not limited to this.
The conditions may be different between the first doping process and the third doping process.

Next, as shown in FIG. 2G, after removing the resist masks 187, 123, and 124, new resist masks 127 and 128 are formed, and a fourth doping process (doping 4) is performed. In the fourth doping process, an impurity element imparting P-type is added. The doping method may be an ion doping method or an ion implantation method. Fourth impurity regions 190a, 190b, 191a in which a P-type impurity element is added to the island-shaped semiconductor layers 102b and 102d forming the P-channel TFT.
191b, 129a and 129b are formed. At this time, the third shape conductive layer 113b and the fourth shape conductive layer 12
2 is used as a mask for the impurity element to form the impurity region in a self-aligned manner. Note that the island-shaped semiconductor layers 102a and 102c forming the N-channel TFT are entirely covered with resist masks 127 and 128.

The fourth doping regions 190a, 190b, 191a, 191b, 1b, 1b, 1b, 1b, 1b, 1b
Phosphorus is added to 29a and 129b at different concentrations. However, an impurity element imparting P-type conductivity is added to any of the regions by the ion doping method using diborane (B ₂ H ₆ ). At this time, the concentration of the impurity element imparting P-type in the fourth impurity regions 190a, 190b, 191a, and 191b is 2 × 10 ²⁰ to 2 × 10 ²¹ at.
It should be oms / cm ³ . Thus, the fourth impurity regions 190a, 190b, 191a, 191b function as a source region and a drain region of the P-channel TFT without any problem. Also, the fourth impurity regions 129a, 1
29b functions as a Lov region of the P-channel TFT without any problem.

Through the above steps, each semiconductor layer 1
Impurity regions are formed at 02a to 102d. Third shape conductive layers 112 and 113 overlapping the island-shaped semiconductor layer, and
The fourth shape conductive layers 121 and 122 function as gate electrodes.

Thus, as shown in FIG. 2H, the N-channel TFT 71, the P-channel TFT 72, the N-channel TFT 73 and the P-channel TFT 74 are formed.

The N-channel TFT 71 has high-concentration impurity regions 110a and 110b corresponding to the channel region 192, the source region and the drain region, low-concentration impurity regions (Lov regions) 117a and 117b overlapping the gate electrode, and not overlapping the gate electrode. It has low-concentration impurity regions (Loff regions) 116a and 116b. On the other hand, the P-channel TFT 72 has high-concentration impurity regions 190a and 19a corresponding to the channel region 193, the source region and the drain region.
0b, and low concentration impurity regions (Lov regions) 129a and 129b overlapping with the gate electrode. The structure has no Loff region. N-channel type TFT 71 and P
The gate electrode of the channel TFT 72 has a tapered end portion. Therefore, the TFT has an inappropriate shape for making the gate electrode small. However, the Lov region and the Loff region are formed in the gate electrode manufacturing process.
Since it can be manufactured in a self-aligning manner, the number of steps in manufacturing a TFT can be suppressed. In this way, it is possible to reduce the number of steps and form a TFT having high pressure resistance.

Further, the N-channel TFT 73 has a channel region 194 and high concentration impurity regions 125a and 125b corresponding to the source region and the drain region. Also,
The P-channel TFT 74 has a high-concentration impurity region 1 corresponding to the channel region 195, the source region and the drain region.
91a and 191b. The N-channel TFT 73 and the P-channel TFT 74 have a single drain structure. N-channel TFT 73, P-channel TFT 7
When 4 is a TFT having a Lov region or a Loff region, a new mask is required, which causes a problem that the number of steps is increased. However, since the edge of the gate electrode is vertically etched, miniaturization is possible.

For example, a circuit which is required to withstand voltage is manufactured by using the N-channel TFT 71 and the P-channel TFT 72, and the N-channel TFT 73 and the P-channel TFT are formed.
With 74, a circuit that requires miniaturization can be manufactured.

The exposure means used in the first exposure step and the exposure means used in the second exposure step can be the same or different. Here, generally, the shorter the wavelength of the radiant energy source used for exposure, the higher the resolution during exposure.
Therefore, for example, when miniaturization is required for the N-channel TFT 73 and the P-channel TFT 74 with respect to the N-channel TFT 71 and the P-channel TFT 72, the first
The wavelength of light used in the second exposure step is shorter than the wavelength of light used in the second exposure step.

The exposure apparatus used in the first exposure step and the exposure apparatus used in the second exposure step can be the same or different.

For example, for the N-channel type TFT 71 and the P-channel type TFT 72, the N-channel type TFT 73, P
When the channel type TFT 74 is required to be miniaturized,
In the first exposure step, exposure is performed using MPA, and in the second exposure step, exposure is performed using a stepper.
In general, MPA is capable of exposing a large area at one time, which is advantageous in productivity of semiconductor devices. On the other hand, in the stepper, the pattern on the reticle is projected by an optical system, and the substrate-side stage is operated and stopped (step and repeat) to expose the pattern on the resist. Compared to MPA, it is not possible to expose a large area at a time, but line and space (L & S) resolution (hereinafter, resolution is L
& S resolution).

As another example, an N-channel type TFT
71, N channel type T to P channel type TFT 72
When the FT73 and the P-channel TFT 74 are required to be miniaturized, the step of the second exposure is performed in the first exposure step using a stepper having a small reduction rate when the pattern on the reticle is projected onto the resist by the optical system. In the step (1), exposure is performed using a stepper having a large reduction rate when the pattern on the reticle is projected onto the resist by the optical system. The reduction ratio of the stepper means the pattern on the reticle is 1 / N (N
Is an integer), and N when projected on the resist. Generally, a stepper having a large reduction rate when projecting a pattern on a reticle onto a resist by an optical system has a narrow range capable of being exposed at one time, but has a high resolution. On the other hand, the stepper, which has a small reduction rate when the pattern on the reticle is projected onto the resist by the optical system, has a wide range that can be exposed at one time but has a low resolution.

As described above, by changing the exposure means in the first exposure step and the second exposure step, a semiconductor device having a TFT with high productivity and good characteristics can be manufactured. Is possible. The exposure unit (exposure condition and exposure apparatus) used in the first exposure and the second exposure steps is not limited to the above. It is possible to freely use known exposure means. Further, each of the first exposure step and the second exposure step may be performed using a plurality of exposure means.

In this embodiment mode, a manufacturing process of a single-gate type TFT is shown, but a double-gate structure or a multi-gate structure having more gates may be used.

In this embodiment mode, a top gate type TFT is shown and its manufacturing process is shown. However, the method for manufacturing a semiconductor device of the present invention is not limited to the dual gate type TF.
It is also applicable to T. Note that a dual-gate TFT is a TFT that has a gate electrode that overlaps with a channel region with an insulating film in between and a gate electrode that overlaps with the insulating film below the channel region.

Further, by using the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom in the shapes of electrodes and wirings of elements other than TFTs formed by using gate metal.

[Embodiment Mode 2] In this embodiment mode, an example of a method for manufacturing a semiconductor device of the present invention, which is different from that in Embodiment Mode 1, is described with reference to FIGS. Note that the manufacturing process example shown in Embodiment Mode 2 corresponds to the example shown in FIG. 1C as a means for solving the problems.

In FIG. 3A, the substrate 201 is made of quartz.
Table of substrate, silicon substrate, metal substrate or stainless steel substrate
The one with an insulating film formed on the surface is used. In addition,
A plastic substrate with heat resistance that can withstand the processing temperature
You may use. In this embodiment, barium borosilicate gas is used.
Base made of glass such as lath and aluminoborosilicate glass
A plate 201 is used. Then, silicon oxide is formed on the substrate 201.
Film, silicon nitride film or silicon oxynitride film
A base film (not shown) is formed. The base film is the insulation
A structure in which two or more layers of the insulating film are laminated even in a single-layer structure of the film
May be In this embodiment, the first layer of the base film and
Then, using the plasma CVD method, SiH _Four, NH₃, And
And N₂A silicon oxynitride film formed using O as a reaction gas
To a thickness of 10 to 200 nm (preferably 50 to 100 nm)
Form. In this embodiment mode, a silicon nitride oxide film having a thickness of 50 nm is used.
To the thickness of. Next, as the second layer of the base film,
Using the Zuma CVD method, SiH_FourAnd N₂O as reaction gas
The silicon oxynitride film formed by 50 to 200 nm (preferably
The thickness is preferably 100 to 150 nm). Of this implementation
In the form, a silicon oxynitride film is formed to a thickness of 100 nm.
It

Subsequently, a semiconductor film is formed on the base film.
The semiconductor film has a thickness of 25 to 80 nm (preferably 3 nm) by known means (sputtering method, LPCVD method, plasma CVD method, etc.).
A semiconductor film is formed to a thickness of 0 to 60 nm). Next, the semiconductor film is crystallized by a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing, thermal crystallization method using a metal element that promotes crystallization, etc.). Note that the thermal crystallization method using a metal element that promotes crystallization and the laser crystallization method may be combined. For example, the laser crystallization method may be performed after the thermal crystallization method using a metal element that promotes crystallization.

Then, the obtained crystalline semiconductor film is patterned into a desired shape to form a semiconductor layer (semiconductor active layer) 20.
2a to 202e are formed. As the semiconductor layer,
A compound semiconductor film having an amorphous structure such as an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, or an amorphous silicon germanium film can be used. In this embodiment mode, an amorphous silicon film having a thickness of 55 nm is formed by a plasma CVD method. Then, a solution containing nickel is held on the amorphous silicon film, the amorphous silicon film is dehydrogenated (500 ° C., 1 hour), and then thermally crystallized (550
C., 4 hours) to form a crystalline silicon film. After that, island-shaped semiconductor layers 202a to 202e are formed by a patterning process using a photolithography method.

As a laser for forming a crystalline semiconductor film by a laser crystallization method, a continuous wave or pulsed gas laser or solid laser may be used. Examples of the former gas laser include excimer laser, YAG laser, and YVO.
₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti: sapphire laser, etc. can be used. As the latter solid-state laser, Cr,
A laser using a crystal of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with Nd, Er, Ho, Ce, Co, Ti or Tm can be used. The fundamental wave of the laser depends on the doping material, 1 μm
Laser light having front and rear fundamental waves can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element. In order to obtain crystals with a large grain size when crystallizing the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and to apply the second to fourth harmonics of the fundamental wave. . Typically, the second harmonic (532 nm) or the third harmonic (355 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) is applied.

Laser light emitted from a continuous oscillation YVO ₄ laser with an output of 10 W is converted into a harmonic by a non-linear optical element. Further, there is also a method of emitting a harmonic by inserting a YVO ₄ crystal and a non-linear optical element in the resonator. Then, preferably, a rectangular or elliptical laser beam is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. Energy density at this time is 0.01-100 MW
/ Cm ² (preferably 0.1 to 10 MW / cm ² ) is required. Then, the semiconductor film is moved relative to the laser beam at a speed of about 10 to 2000 cm / s for irradiation.

When the above laser is used, it is advisable that the laser beam emitted from the laser oscillator is linearly condensed by the optical system and irradiated onto the semiconductor film. The crystallization conditions are appropriately set. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 700 mJ / cm ² (typically 200 to 300 mJ / cm ² ).
cm ² ) is good. When a YAG laser is used, its second harmonic is used to generate a pulse oscillation frequency of 1 to 30.
0Hz, laser energy density 300-1000
mJ / cm ² may (typically 350~500mJ / cm ²⁾ to. And a width of 100 to 1000 μm (preferably a width of 40
The laser beam converged linearly at 0 μm) may be irradiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear beams at this time may be set to 50 to 98%.

However, in this embodiment, since the amorphous silicon film is crystallized by using the metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and a heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed to form the amorphous silicon film in the amorphous silicon film. The metal element is diffused, and the amorphous silicon film is removed by etching after heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed.

After forming the island-shaped semiconductor layers 202a to 202e, a slight amount of impurity element (boron or phosphorus) may be doped. Thus, the threshold value of the TFT can be controlled by adding a slight amount of the impurity element also to the region which will be the channel region.

Then, a gate insulating film 203 which covers the semiconductor layers 202a to 202e is formed. Gate insulating film 203
Is formed by plasma CVD or sputtering to a film thickness of 40
It is formed of an insulating film containing silicon having a thickness of 150 nm. In this embodiment mode, plasma CVD is used as the gate insulating film 203.
A silicon oxynitride film is formed to a thickness of 115 nm by the method.
Of course, the gate insulating film 203 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure. Note that when a silicon oxide film is used as the gate insulating film 203, T
EOS (Tetraethyl Orthosilicate) and O ₂ are mixed, reaction pressure is 40 Pa, substrate temperature is 300 to 400 ° C.,
High frequency (13.56MHz) power density 0.5-0.8W / cm ²
It may be formed by discharging. The silicon oxide film manufactured through the above steps can be provided with favorable characteristics as the gate insulating film 203 by subsequent thermal annealing at 400 to 500 ° C.

Here, a specific region of the semiconductor layers 202a to 202e may be doped with an impurity element before forming the gate electrode. The Lov region and the like can be formed by forming the gate electrode so as to overlap with the impurity region formed at this time. The semiconductor layer 20
When doping 2a to 202e with an impurity element, an insulating film (referred to as a doping insulating film) different from the gate insulating film 203 may be formed. In this case, after the doping process is completed, the doping insulating film is removed.

Next, the first conductive film 204a is formed of TaN to a thickness of 20 to 100 nm, and the second conductive film 204b is formed.
Is formed with W to a thickness of 100 to 400 nm. In this embodiment, the first conductive film 2 made of a TaN film having a film thickness of 30 nm is used.
04a and a second conductive film 2 made of a W film having a thickness of 370 nm
04b is laminated. In this embodiment mode, the TaN film which is the first conductive film 204a is formed by a sputtering method in a nitrogen-containing atmosphere using a Ta target. The W film which is the second conductive film 204b is formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and the resistivity of the W film is 20 μΩ.
It is desirable to make it below cm. Although the resistivity of the W film can be lowered by enlarging the crystal grains, when the W film contains many impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity 99.9999%) target, and with sufficient consideration so that impurities are not mixed from the gas phase during film formation. By forming, a resistivity of 9
We were able to achieve ~ 20μΩcm.

In this embodiment, the first conductive film 20 is used.
Although 4a is a TaN film and the second conductive film 204b is a W film, the materials forming the first conductive film 204a and the second conductive film 204b are not particularly limited. First conductive film 204
a and the second conductive film 204b are formed of Ta, W, Ti, M.
It may be formed of an element selected from o, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Further, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or AgPd
It may be formed of a Cu alloy.

Next, a resist 205 is formed. As a method for forming the resist 205, a coating method can be used. A spin coater or a roll coater may be used for the coating method. The resist 205 can be either a positive type or a negative type, and can be selected according to the light source used at the time of exposure.

Next, the resist 205 is exposed (first exposure) to form resist masks 209, 210, 211 and 285, and a first etching process (gate metal etching 1) for forming a gate electrode is performed. Perform (FIG. 3 (B)). In the first etching process, the first and second
The etching conditions are as follows. In the present embodiment, as the first etching condition, ICP (Inductively Coupled Pl
asma: inductively coupled plasma etching method, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the flow rate ratio of each gas is set to 25:25:10 (sccm),
500 W RF (1
(3.56 MHz) Power is supplied to generate plasma for etching. RF (13.56 MHz) power of 150 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. Then, the W film is etched under the first etching condition so that the end portion of the second conductive layer 204b is tapered. Then, the resist mask 2
09, 210, 211 were changed to the second etching condition without being removed, CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow ratios were set to 30:30 (sccm),
500 W RF (1
3.56MHz) Power is supplied to generate plasma 15
Perform etching for about a second. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. Under the second etching condition, the first conductive layer 204a and the second conductive layer 204a
Etching is performed to the same level as in b. Note that in order to perform etching without leaving a residue on the gate insulating film 203, the etching time may be increased at a rate of approximately 10 to 20%. In the above-described first etching treatment, by adjusting the shape of the resist mask to an appropriate shape, the end portions of the first conductive layer 204a and the second conductive layer 204b are separated by the effect of the bias voltage applied to the substrate side. It becomes a taper shape. Thus, the first etching process makes
Shaped conductive layers 206, 207, 208 (first conductive layers 206 a, 207 a, 208 a, second conductive layer 206
b, 207b, 208b) are formed. Gate insulating film 2
In 03, the exposed region is etched and thinned by about 20 to 50 nm.

Next, as shown in FIG. 3C, a second etching process (gate metal etching 2) is performed without removing the resist masks 209, 210, 211 and 285. In the second etching process, S is used as an etching gas.
Using F ₆ , Cl ₂ and O ₂ , each gas flow rate ratio is 2
At 4:12:24 (sccm), 700 W RF (13.56 MHz) power is applied to the coil side power at a pressure of 1.3 Pa to generate plasma, and etching is performed for about 25 seconds. RF of 10W on the substrate side (sample stage)
(13.56 MHz) is turned on and a substantially negative self-bias voltage is applied. In this way, the W film is selectively etched and the second shape conductive layers 212 to 214 (first
Conductive layers 212a to 214a and second conductive layers 212b to
214b) is formed. At this time, the first conductive layer 206
a to 208a are hardly etched. In addition, since portions of the first conductive film 204a and the second conductive film 204b formed over the semiconductor layers 202d and 202e are covered with the resist mask 285, the first etching treatment and the second etching treatment are performed. Is not etched through.

Then, the resist masks 209, 210,
A first doping process (Doping 1) is performed without removing 211, and an impurity element imparting N-type conductivity is added to the semiconductor layers 202a to 202c at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5
X 10 ¹⁴ atoms / cm ² and acceleration voltage of 40 to 80 kV. In this embodiment, the dose amount is 5.0 × 10 ^13.
The atoms / cm ² are used, and the acceleration voltage is set to 50 kV. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used.
In this case, the second shape conductive layers 212 to 214 are used as masks for the impurity element imparting N-type, and the first impurity regions 218a, 218b, 219a, and 2 are self-aligned.
19b, 220a, 220b are formed. Then, the first impurity regions 218a, 218b, 219a, 219b,
220a and 220b have 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms /
An impurity element imparting N-type is added in the concentration range of cm ³ .

Subsequently, as shown in FIG. 3D, after removing the resist masks 209, 210, 211 and 285,
Resist masks 221, 239 and 240 are newly formed. The second doping process (doping 2) is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 3 × 10 ¹⁵ atoms /
cm ² and the acceleration voltage is 60 to 120 kV. In this embodiment, the dose amount is 3.0 × 10 ¹⁵ atoms / cm ²
And the acceleration voltage is set to 65 kV. In the second doping treatment, the second conductive layer 213b is used as a mask for the impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. Here, in the second doping process, the resist mask 239 is formed so as to cover the semiconductor layer 202c to be the P-channel TFT. Note that the resist mask 240 is not always necessary.

As a result of performing the second doping process described above, 1 × 10 ^{18 to} 5 × are formed in the second impurity regions (Lov regions) 225a and 225b overlapping the first conductive layer 213a.
An impurity element imparting N-type is added in a concentration range of 10 ¹⁹ atoms / cm ³ . In addition, the third impurity regions 222a and 222
b, 224a, and 224b are 1 × 10 ^{19 to} 5 × 10 ²¹ at
An impurity element imparting N-type is added in the concentration range of oms / cm ³ . Further, among the first impurity regions 218a and 218b formed by the first doping process, there are regions 223a and 223b covered with the resist 221 in the second doping process, but the first impurity regions continue. Call it.

In this embodiment, the second impurity regions 225a and 225b are formed only by the second doping process.
And the third impurity regions 222a, 222b, 224a,
224b, but is not limited thereto. It may be formed by performing the doping process a plurality of times by appropriately changing the conditions for performing the doping process.

Next, as shown in FIG. 3E, after removing the resist masks 221, 239 and 240, a new resist 286 is formed. As a method for forming the resist 286, a coating method can be used. A spin coater or a roll coater may be used for the coating method. The resist 286 can be either a positive type or a negative type and can be selected according to the light source used at the time of exposure. In addition,
The resist 286 is the resist 2 used in the first exposure.
The same material as 05 may be used, or different materials may be used.

Next, the resist 286 is exposed (second exposure) to form resist masks 230, 231, and 287 (FIG. 3 (F)). The exposure means in the second exposure may be the same as or different from the first exposure. Thus, the third etching process (gate metal etching 3) is performed. Thus, the third shape conductive layers 228, 229 (first conductive layers 228a, 229a, second conductive layers 228b, 22) having substantially vertical ends are formed.
9b) is formed. Note that the semiconductor layers 202a and 202a
b, the second shape conductive layer 21 formed on 202c
2, 213, 214 (first conductive layers 212a, 213
a, 214a, second conductive layers 212b, 213b, 21
The portion 4b) is covered with the resist mask 287 and is not etched.

After that, a third doping process (doping 3) is performed. In the third doping process, an impurity element imparting N-type is added. The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atom.
s / cm ² and accelerating voltage of 60 to 100 kV. N
As the impurity element imparting the type, an element belonging to Group 15 is used, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the resist masks 230, 231, 287 are used as masks for the impurity element imparting N-type, and the fourth impurity regions 232a, 232a, 23 are formed.
2b, 233a and 233b are formed. 1 × in the fourth impurity regions 232a, 232b, 233a, 233b.
An impurity element imparting N-type is added within a concentration range of 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Note that the semiconductor layers 202a to
Since 202c is covered with the resist mask 287, the impurity element is not added in the third doping treatment.

Next, as shown in FIG. 3G, a fourth doping process (doping 4) is performed. In the fourth doping process, an impurity element imparting P-type is added.
The doping method may be an ion doping method or an ion implantation method. Fifth impurity regions 235a, 235b, 238 in which a P-type impurity element is added to the island-shaped semiconductor layers 202c and 202e forming the P-channel TFT.
a, 238b and sixth impurity regions 236a, 236b
To form. At this time, the second shape conductive layer 214b and the third shape conductive layer 229 are used as masks for the impurity element to form the impurity regions in a self-aligned manner. In this embodiment mode, an ion doping method using diborane (B ₂ H ₆ ) is used. As conditions for the ion doping method, the dose amount is 1 × 10 ¹⁶ atoms / cm ² and the acceleration voltage is 80 kV. Thus, the P-type impurity element can be added to the regions 236a and 236b of the semiconductor active layer which overlap with the second shape conductive layer 214a through the second shape conductive layer 214a. Here, the sixth impurity regions 236a, 2
The concentration of the P-type impurity element added to 36b can be made lower than the concentration of the P-type impurity element added to the fifth impurity regions 235a and 235b. Note that the island-shaped semiconductor layers 202a, 202b, and 202d forming the N-channel TFT are entirely covered with resist masks 234 and 237 during the fourth doping treatment. Note that the fifth impurity region 235 is formed by the first doping treatment, the second doping treatment, and the third doping treatment.
Although phosphorus is added to a, 235b, 238a, and 238b at different concentrations, the fifth impurity region 23 can be formed by adding an element imparting P-type at a high concentration.
5a, 235b, 238a, and 238b function as a source region and a drain region of the P-channel TFT without any problem.

Through the above steps, each semiconductor layer 2
Impurity regions are formed in 02a to 202e. Second shape conductive layers 212, 213 and 21 overlapping the island-shaped semiconductor layers
4 and the third shape conductive layers 228 and 229 function as gate electrodes.

Thus, as shown in FIG. 3H, an N-channel TFT 61, an N-channel TFT 62, a P-channel TFT 63, an N-channel TFT 64 and a P-channel TFT 65 are formed.

The N-channel TFT 61 includes a channel region 292, high-concentration impurity regions 222a and 222b corresponding to the source and drain regions, and low-concentration impurity regions (Loff regions) 223a and 223 that do not overlap with the gate electrode.
b. The N-channel TFT 62 has a channel region 293, high-concentration impurity regions 224a and 224b corresponding to the source and drain regions, and low-concentration impurity regions (Lov regions) 225a and 225b overlapping with the gate electrode. On the other hand, the P-channel TFT 63 has a channel region 294, high concentration impurity regions 235a and 235b corresponding to the source and drain regions, and low concentration impurity regions (Lov regions) 236a and 236b overlapping with the gate electrode. N-channel TFT 61, N-channel TFT 6
The gate electrodes of the 2 and P-channel TFTs 63 have tapered end portions. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode. But Lov
The region and the Loff region can be formed in a self-aligned manner in the process of forming the gate electrode.
The number of steps in T fabrication can be suppressed. In this way, it is possible to reduce the number of steps and form a TFT having high pressure resistance.

The N-channel TFT 64 has a channel region 295 and high-concentration impurity regions 232a and 232b corresponding to the source and drain regions. Also,
The P-channel TFT 65 has a high-concentration impurity region 2 corresponding to the channel region 296, the source region and the drain region.
38a and 238b. The N-channel TFT 64 and the P-channel TFT 65 have a single drain structure. N-channel TFT 64, P-channel TFT 6
No. 5 has a problem that a new mask is required when the TFT having the Lov region and the Loff region is used, and the number of steps is increased. However, since the edge of the gate electrode is vertically etched, miniaturization is possible.

The exposure means for producing the gate electrodes of the N-channel TFT 61, the N-channel TFT 62, the P-channel TFT 63, the N-channel TFT 64 and the P-channel TFT 65 is the same as that of the first embodiment. The description is omitted here.

For example, with the N-channel type TFT 61, the N-channel type TFT 62, and the P-channel type TFT 63,
N-channel TFTs are manufactured by manufacturing circuits that require pressure resistance.
A circuit that requires miniaturization can be manufactured using the 64 and P-channel TFTs 65. At this time, the exposure means in manufacturing the gate electrode of each TFT can be the same as that in the first embodiment.

Although the manufacturing process of the single-gate TFT is described in this embodiment mode, a double-gate structure or a multi-gate structure having more gates may be used. In addition, in this embodiment mode, a top-gate TFT is shown and a manufacturing process thereof is shown. However, the method for manufacturing the semiconductor device of the present invention is not limited to the dual gate type TFT
It is also possible to apply to.

Further, by using the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom in the shapes of electrodes and wirings of elements other than TFTs formed by using gate metal. (Embodiment Mode 3) In this embodiment mode, an example of a method for manufacturing a semiconductor device of the present invention, which is different from those in Embodiment Modes 1 and 2, is described with reference to FIGS. The third embodiment
The example of the manufacturing process shown in 1 corresponds to the example shown in FIG. 1B in the means for solving the problem. Since the steps up to gate metal etching 2 are the same as the steps described with reference to FIG. 3 in the second embodiment, the same parts are denoted by the same reference numerals and the description thereof will be omitted.

According to the steps of the second embodiment, up to FIG. Next, as shown in FIG. 4D, the resist masks 209 to 211 and 285 are removed, a new resist film is formed and exposed (second exposure), and the resist mask 3 is formed.
30, 331, 388 are formed. The exposure means in the second exposure may be the same as or different from that in the first exposure. Thus, the third etching process (gate metal etching 3) is performed. Thus, the third shaped conductive layers 328, 329 having substantially vertical edges.
(First conductive layers 328a, 329a, second conductive layer 32
8b, 329b) are formed. Note that the semiconductor layer 202
The second shape conductive layers 212, 213, 214 (first conductive layers 212a, 202a, 202c) formed on a, 202b, 202c.
213a and 214a, the second conductive layers 212b and 213
The portion (b, 214b) is not etched because it is covered with the resist mask 388.

After that, as shown in FIG. 4E, after removing the resist masks 330, 331 and 388, a first doping process (doping 1) is performed to perform the semiconductor layer 202.
An impurity element imparting N-type is added to a to 202e at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are that the dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage is 40 to 80 kV. In this embodiment, the dose amount is 5.0 × 10 ¹³ atoms / cm ² and the acceleration voltage is 5
Perform as 0 kV. As an impurity element imparting N-type,
An element belonging to Group 15 may be used, and phosphorus (P) or arsenic (As) is typically used, but phosphorus (P) is used in this embodiment. In this case, the second shape conductive layers 212 to 214 and the third shape conductive layers 328 and 32.
9 as a mask against the impurity element imparting N-type,
The first impurity regions 318a, 318b, 3 are self-aligned.
19a, 319b, 320a, 320b, 1220a,
1220b, 1221a and 1221b are formed. Then, the first impurity regions 318a, 318b, 319a, 3
19b, 320a, 320b, 1220a, 1220
1 × 10 ¹⁸ to 1 × 10 for b, 1221a, and 1221b
An impurity element imparting N-type is added within a concentration range of ²⁰ atoms / cm ³ .

Subsequently, as shown in FIG. 4F, new resist masks 321, 327, and 333 are formed. First
The second doping process (doping 2) is performed at an acceleration voltage higher than that of the second doping process. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 3 × 10 ¹⁵ atoms / cm ² and the acceleration voltage is 60 to 120 kV. In this embodiment mode, the dose amount is 3.0 × 10 ¹⁵ atoms / cm ² and the acceleration voltage is 65 kV. The second doping process is performed in the second shape conductive layer 213b and the third shape conductive layer 32.
Using 8 as a mask for the impurity element, doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. Note that resist masks 327 and 333 are formed so as to cover the semiconductor layers 202c and 202e to be P-channel TFTs in the second doping treatment.

As a result of the above second doping process, the second impurity region 3 overlapping with the first conductive layer 213a is formed.
25a and 325b include 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm
An impurity element imparting N-type is added within the concentration range of ³ .
In addition, the third impurity regions 322a, 322b, 324a,
1 × 10 ^{19 to} 5 × 1 for 324b, 332a, and 332b.
An impurity element imparting N-type is added within the concentration range of 0 ²¹ atoms / cm ³ . Further, among the first impurity regions 318a and 318b formed by the first doping process, there are regions 323a and 323b covered with the resist 321 in the second doping process, but the first impurity regions continue. Call it.

In this embodiment mode, the second impurity regions 325a, 325b and the third impurity regions 322a, 322b, 324a, 3 are formed only by the second doping process.
Although 24b, 332a, and 332b are formed, it is not limited thereto. By appropriately changing the conditions for performing the doping process,
It may be formed by a plurality of doping processes.

Next, as shown in FIG. 4G, after removing the resist masks 321, 327 and 333, new resist masks 334 and 337 are formed. Then, a third doping process (doping 3) is performed. In the third doping process, an impurity element imparting P-type is added. The doping method may be an ion doping method or an ion implantation method. Fourth impurity regions 335 a, 335 b, 3 in which a P-type impurity element is added to the island-shaped semiconductor layers 202 c and 202 e forming the P-channel TFT.
38a, 338b and fifth impurity regions 336a, 33.
6b is formed. At this time, the second shape conductive layer 214b
Using the third shape conductive layer 329 as a mask for the impurity element, the impurity regions are formed in a self-aligned manner.
In this embodiment mode, an ion doping method using diborane (B ₂ H ₆ ) is used. As conditions for the ion doping method, the dose amount is 1 × 10 ¹⁶ atoms / cm ² and the acceleration voltage is 80 kV. Thus, the P-type impurity element can be added to the regions 336a and 336b of the semiconductor active layer which overlap with the second shape conductive layer 214a through the second shape conductive layer 214a. Here, the fifth impurity region 336a,
The concentration of the P-type impurity element added to 336b can be lower than the concentration of the P-type impurity element added to the fourth impurity regions 335a and 335b. During the third doping process, the island-shaped semiconductor layers 202a, 202b, and 202d forming the N-channel TFT are entirely covered with resist masks 334 and 337. Note that the fourth impurity region 335 is formed by the first doping treatment, the second doping treatment, and the third doping treatment.
Although phosphorus is added to the a, 335b, 338a, and 338b, the fourth impurity regions 335a, 335b, and 33 are formed by adding a high-concentration element that imparts P-type conductivity.
8a and 338b function as a source region and a drain region of the P-channel TFT without any problem.

Through the above steps, each semiconductor layer 2
Impurity regions are formed in 02a to 202e. Second shape conductive layers 212, 213 and 21 overlapping the island-shaped semiconductor layers
4 and the third shape conductive layers 328 and 329 function as gate electrodes.

Thus, as shown in FIG. 4H, an N-channel TFT 361, an N-channel TFT 362, a P-channel TFT 363, an N-channel TFT 364, P.
The channel type TFT 365 is formed.

The N-channel TFT 361 includes a channel region 392, high-concentration impurity regions 322a and 322b corresponding to the source and drain regions, and low-concentration impurity regions (Loff regions) 323a and 32 that do not overlap with the gate electrode.
With 3b. The N-channel TFT 362 includes a channel region 393, high-concentration impurity regions 324a and 324b corresponding to the source and drain regions, and low-concentration impurity regions (Lov regions) 325a and 325b overlapping with the gate electrode.
Have. On the other hand, the P-channel TFT 363 has a channel region 394, high-concentration impurity regions 335a and 335b corresponding to the source and drain regions, and low-concentration impurity regions (Lov regions) 336a and 336 overlapping with the gate electrode.
b. The gate electrodes of the N-channel TFT 361, the N-channel TFT 362, and the P-channel TFT 363 have tapered end portions. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode. However, the Lov region and the Loff region can be formed in a self-aligned manner in the process of forming the gate electrode, so that the number of steps in manufacturing the TFT can be suppressed.
In this way, it is possible to reduce the number of steps and form a TFT having high pressure resistance.

The N-channel TFT 364 has a channel region 395 and high-concentration impurity regions 332a and 332b corresponding to the source and drain regions. The P-channel TFT 365 has a high-concentration impurity region 33 corresponding to the channel region 396, the source region and the drain region.
8a and 338b. The N-channel TFT 364 and the P-channel TFT 365 have a single drain structure. N-channel TFT 364, P-channel TF
T365 has a problem that a new mask is required when manufacturing a Lov region or a Loff region, which results in an increase in the number of steps. However, since it is manufactured using a process in which the end of the gate electrode may be vertically etched,
Miniaturization is possible.

In the third embodiment, as shown in FIG.
In the step shown in (F), the resist masks that cover only the third shape conductive layer 328 and the peripheral portion of the third shape conductive layer 328 are changed to resist masks 321, 327, and 333.
By forming at the same time, the Loff region can be formed in the N-channel TFT 364 without increasing the number of steps.

Regarding the exposure means in the manufacture of the gate electrodes of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364 and the P-channel TFT 365,
Since it is the same as that of the first embodiment, the description thereof is omitted here.

For example, the N-channel type TFT 361, the N-channel type TFT 362, and the P-channel type TFT 363 form a circuit having a high withstand voltage, and the N-channel type TFT 364 and the P-channel type TFT 365 require a fine circuit. Can be produced. At this time, the exposure means in manufacturing the gate electrode of each TFT can be the same as that in the first embodiment.

Although the manufacturing process of the single gate type TFT is shown in this embodiment mode, a double gate structure or a multi-gate structure having more gates may be used. In addition, in this embodiment mode, a top-gate TFT is shown and a manufacturing process thereof is shown. However, the method for manufacturing the semiconductor device of the present invention is not limited to the dual gate type TFT
It is also possible to apply to.

Further, by using the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom in the shapes of electrodes and wirings of elements other than TFTs formed by using gate metal.

[Embodiment Mode 4] In this embodiment mode, an example of a method for manufacturing a semiconductor device of the present invention, which is different from those in Embodiment Modes 1 to 3, is described with reference to FIGS. Note that the manufacturing process example shown in Embodiment Mode 4 corresponds to the example shown in FIG. 1B as a means for solving the problems. Note that the steps up to the gate metal etching 3 are the same as the steps described with reference to FIG. 4 in the third embodiment, so description thereof will be omitted.

According to the steps of the third embodiment, FIG.
Up to. Next, as shown in FIG. 25E, the resist masks 330, 331, 388 are removed and a new resist mask 8000 is formed. Resist mask 80
00 to form a P-channel TFT semiconductor layer 20.
2e is covered. A first doping process (Doping 1) is performed, and an impurity element imparting N-type conductivity is added to the semiconductor layers 202a to 202d at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used.
To use. In this case, the second shape conductive layers 212 to 21
The fourth and third conductive layers 328 are used as a mask for the impurity element imparting N-type conductivity, and the first impurity regions 831 are formed.
8a, 8318b, 8319a, 8319b, 8320
a, 8320b, 8220a, 8220b are formed.
First impurity regions 8318a, 8318b, 8319
a, 8319b, 8320a, 8320b, 8220
An impurity element imparting N-type is added to a and 8220b.

Subsequently, as shown in FIG. 25F, after removing the resist mask 8000, new resist masks 9101 and 9102 are formed. A second doping process (Doping 2) is performed, and an impurity element imparting P-type conductivity is added to the semiconductor layer 202e at a low concentration. The second doping treatment may be performed by an ion doping method or an ion implantation method. In this embodiment mode, an ion doping method using diborane (B ₂ H ₆ ) is used. Thus, the third shape conductive layer 3
Second impurity regions 8221a and 8221b are formed as a mask for imparting P-type conductivity with reference numeral 29. A P-type impurity element is added to the second impurity regions 8221a and 8221b.

Next, as shown in FIG. 25G, after removing the resist masks 9101 and 9102, resist masks 9321, 9327, 9003 and 9333 are formed. After that, a third doping process (doping 3) is performed in which an impurity element imparting N-type conductivity is added. The third doping process (doping 3) is performed at an acceleration voltage higher than that of the first doping process. In the third doping treatment, the second shape conductive layer 213b is used as a mask for the impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer 213a. In addition, at the time of the third doping process, P
Semiconductor layers 202c and 202e to be channel type TFTs
Resist masks 9327 and 9333 are formed so as to cover the. In addition, the first impurity regions 8318a and 8318a, 8
A resist mask 9321 is formed so as to cover part of the 318b and the second shape conductive layer 212. A resist mask 9003 is formed so as to cover part of the first impurity regions 8220a and 8220b and the conductive layer 328 having the third shape.
Are formed. The first impurity regions 8318a and 8318b which are not covered with the resist mask 9321 and the first impurity regions 82 which are not covered with the resist mask 9003.
An N-type impurity element is added to 20a and 8220b in the third doping step. Note that the first impurity regions 8318a, 8318b, 8220a, 8220b
Of the resist 932 in the third doping process
Areas 9323a, 9323 covered by 1, 9003
Although there are b, 9004a, and 9004b, they are referred to as a first impurity region. In addition, the second shape conductive layer 21
The conditions (acceleration voltage or the like) in the third doping process are set so that the impurity element imparting N-type conductivity is added to the lower portion of the second shape conductive layer 213a which does not overlap with 3b. The concentration of the impurity element added through the second shape conductive layer 213a can be lower than the concentration of the impurity element added without the second shape conductive layer 213a. Thus, the third impurity regions 9322a and 9322 to which the impurity element imparting N-type is added at high concentration are added.
b, 9324a, 9324b, 9332a, 9332b
And an impurity element imparting N-type at a low concentration was added 9
323a, 9323b, 9325a, 9325b, 90
04a and 9004b are formed.

Next, as shown in FIG. 25H, after removing the resist masks 9321, 9327, 9003 and 9333, the resist masks 9334, 9337 and 900 are removed.
5 is formed. After that, a fourth doping process (doping 4) is performed to add an impurity element imparting P-type conductivity. In the fourth doping process (Doping 4), the second
The accelerating voltage is higher than that of the doping process. In the fourth doping process, the second shape conductive layer 214b is used as a mask for the impurity element, and the first conductive layer 214a is used.
Doping is performed so that the impurity element is added to the semiconductor layer below the taper portion. Note that in the fourth doping treatment, the semiconductor layer 202 to be an N-channel TFT is formed.
Resist masks 9334 and 9337 are formed so as to cover a, 202b, and 202d. In addition, a resist mask 9005 is formed so as to cover part of the second impurity regions 8221a and 8221b and the conductive layer 329 having the third shape.
Are formed. In the second impurity regions 8221a and 8221b which are not covered with the resist mask 9005, the fourth impurity regions
A P-type impurity element is added by the doping process of. Of the second impurity regions 8221a and 8221b, the resist 9005 in the fourth doping treatment is used.
Although there are regions 9006a and 9006b which are covered with, they are continuously called second impurity regions. In addition, the second shape conductive layer 2 that does not overlap with the second shape conductive layer 214b
The conditions (acceleration voltage, etc.) in the fourth doping process are set so that the impurity element imparting P-type is also added to the lower part of 14a. The concentration of the impurity element added through the second shape conductive layer 214a can be lower than the concentration of the impurity element added without passing through the second shape conductive layer 214a. Thus, the fourth impurity region 933 to which the impurity element imparting P-type is added at high concentration is added.
5a, 9335b, 9338a, 9338b, and 9336a to which an impurity element imparting P-type is added at a low concentration,
9336b, 9006a, and 9006b are formed.

Although phosphorus is added to the fourth impurity regions 9335a and 9335b by the first doping treatment, by adding a high concentration of an element imparting P-type conductivity, the fourth impurity regions 9335a and 9335b are doped. 9335a, 9335
b functions as a source region and a drain region of the P-channel TFT without any problem.

Through the above steps, each semiconductor layer 2
Impurity regions are formed in 02a to 202e. Second shape conductive layers 212, 213 and 21 overlapping the island-shaped semiconductor layers
4 and the third shape conductive layers 328 and 329 function as gate electrodes.

Thus, as shown in FIG. 25I, an N-channel TFT 9361 and an N-channel TFT 936 are provided.
2, P-channel type TFT 9363, N-channel type TFT
9364 and a P-channel TFT 9365 are formed.

The N-channel TFT 9361 includes a channel region 9392, high-concentration impurity regions 9322a and 9322b corresponding to source and drain regions, and a low-concentration impurity region (Loff region) 932 which does not overlap with the gate electrode.
3a and 9323b. N-channel TFT 936
2 is high concentration impurity regions 9324a and 9324 corresponding to the channel region 9393, the source region and the drain region.
b, low-concentration impurity regions (Lov regions) 9325a and 9325b overlapping with the gate electrode. On the other hand, the P-channel TFT 9363 has a high-concentration impurity region 93 corresponding to the channel region 9394, the source region, and the drain region.
35a and 9335b, and low concentration impurity regions (Lov regions) 9336a and 9336b overlapping with the gate electrode.
N-channel TFT 9361, N-channel TFT 93
The gate electrodes of the 62 and P-channel TFT 9363 are
It has a tapered end. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode.

The N-channel TFT 9364 has a channel region 9395 and high-concentration impurity regions 9332a and 9332b corresponding to the source and drain regions. Further, low concentration impurity regions (Loff regions) 9004a and 9004b which do not overlap with the gate electrode are provided. P
The channel type TFT 9365 has a channel region 9396,
High concentration impurity regions 9338a and 9338b corresponding to the source region and the drain region are provided. In addition, a low concentration impurity region (Loff region) 900 which does not overlap with the gate electrode
6a and 9006b. In this embodiment mode, an N-channel TFT 9364 and a P-channel TFT 9365 are used.
Also, the process of forming the Loff region is shown.

N-channel TFT 9361, N-channel TFT 9362, P-channel TFT 9363, N-channel TFT 9364, P-channel TFT 9365.
Since the exposure means for manufacturing each gate electrode is the same as that in the first embodiment, the description thereof is omitted here.

In this embodiment mode, a manufacturing process of a single-gate type TFT is shown, but a double-gate structure or a multi-gate structure having more gates may be used. In addition, in this embodiment mode, a top-gate TFT is shown and a manufacturing process thereof is shown. However, the method for manufacturing the semiconductor device of the present invention is not limited to the dual gate type TFT
It is also possible to apply to.

Further, by using the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom in the shapes of electrodes and wirings of elements other than TFTs formed by using gate metal.

[Embodiment Mode 5] In this embodiment mode, an example of a method for manufacturing a semiconductor device of the present invention, which is different from those in Embodiment Modes 1 to 4, is described with reference to FIGS. Note that the manufacturing process example shown in Embodiment Mode 5 corresponds to the example shown in FIG. 1B as a means for solving the problems. Since the steps up to gate metal etching 3 are the same as the steps described with reference to FIG. 25 in the fourth embodiment, description thereof will be omitted.

According to the steps of the fourth embodiment, FIG.
Up to. Next, as shown in FIG. 26E, the resist masks 330, 331, and 388 are removed and a new resist mask 8000 is formed. Resist mask 80
00 to form a P-channel TFT semiconductor layer 20.
2e is covered. A first doping process (Doping 1) is performed, and an impurity element imparting N-type conductivity is added to the semiconductor layers 202a to 202d at a low concentration. The first doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used.
To use. In this case, the second shape conductive layers 212 to 21
The fourth and third conductive layers 328 are used as a mask for the impurity element imparting N-type conductivity, and the first impurity regions 831 are formed.
8a, 8318b, 8319a, 8319b, 8320
a, 8320b, 8220a, 8220b are formed.

Next, as shown in FIG. 26F, the resist mask 8000 is removed and a new resist mask 80 is formed.
01 and 8002 are formed. By the resist mask 8002, the semiconductor layer 202c to be a P-channel TFT,
The semiconductor layer 202d that serves as an N-channel TFT and the semiconductor layer 202e that serves as a P-channel TFT are covered. Further, with the resist mask 8001, parts of the first impurity regions 8318a and 8318b 8323a and 8323 are formed.
b is covered. A second doping process (doping 2) is performed, and an impurity element imparting N-type conductivity is added to the semiconductor layers 202a and 202b at a low concentration. The second doping treatment may be performed by an ion doping method or an ion implantation method. As the impurity element imparting N-type, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, phosphorus (P) is used.
To use. In this case, the second shape conductive layer 213b is
The second impurity regions 8322a, 8322b, 8324a, and 83 are used as masks for the impurity element imparting a mold.
24b is formed. Note that the region 8323a covered with the resist mask 8001 in the second doping treatment,
Although 8323b exists, it is continuously referred to as a first impurity region. In addition, the conditions in the second doping treatment (acceleration voltage Etc.) is set. The second
The concentration of the impurity element added through the conductive layer 213a having the above shape can be lower than the concentration of the impurity element added without passing through the conductive layer 213a having the second shape.
Thus, the second impurity regions 8322a, 8322b, and 832 to which the impurity element imparting N-type is added at high concentration
4a and 8324b and first impurity regions 8323a and 8323 to which an impurity element imparting N-type is added at a low concentration.
b, third impurity regions 8325a and 8325b are formed.

Next, as shown in FIG. 26G, the resist masks 8001 and 8002 are removed and new resist masks 8003 and 8004 are formed. By the resist mask 8003, a semiconductor layer 202a to be an N-channel TFT and a semiconductor layer 202b to be an N-channel TFT are formed.
And the semiconductor layer 202d to be an N-channel TFT is covered with the resist mask 8004. Third doping treatment (doping 3) is performed, and an impurity element imparting P-type conductivity is added to the semiconductor layers 202c and 202e. The second doping treatment may be performed by an ion doping method or an ion implantation method. In this embodiment mode, an ion doping method using diborane (B ₂ H ₆ ) is used. Thus
Fourth impurity regions 8335a, 8335b, 8332a, 8332b to which an impurity element imparting P-type conductivity is added are formed. Note that the fourth impurity regions 8335a and 83
The impurity element imparting N-type conductivity is added to 35b by the first doping treatment. Function as an impurity region without any problem. Note that a resist mask that covers the semiconductor layer 202c is provided in the first doping treatment,
It is possible to prevent the N-type impurity element from being added to the regions to be the impurity regions 8335a and 8335b.

Then, as shown in FIG. 26H, the resist masks 8003 and 8004 are removed, and an insulating film 8005 is formed.
To form. As the insulating film 8005, it is preferable to use a film having excellent coverage. For example, silicon oxide can be used.

Next, as shown in FIG. 26I, the insulating film 8003 is anisotropically etched to form the sidewalls 80.
06a, 8006b, 8007a, 8007b, 800
8a, 8008b, 8009a, 8009b, 8010
a, 8010b is formed.

Next, as shown in FIG. 26J, resist masks 8011 and 8012 are formed. The semiconductor layers 202a to 20a are formed by the resist masks 8011 and 8012.
The entire surfaces of 2c and 202e are covered. After that, a fourth doping treatment is performed to add an impurity element imparting N-type conductivity. The fourth doping treatment is performed using the third shape conductive layer 328 and the sidewalls 8009a and 8009b as masks against the impurity element. First impurity region 8 not covered with resist masks 8011 and 8012
An N-type impurity element is added to 220a and 8220b in the fourth doping step. Note that, among the first impurity regions 8220a and 8220b, sidewalls 8009a and 8009b in the fourth doping treatment are performed.
Although there are regions 8014a and 8014b covered with, they are continuously called first impurity regions. Thus, the fifth impurity regions 8013a and 8013b to which the impurity element imparting N-type is added at a high concentration and the first impurity region 8014 to which the impurity element imparting N-type is added at a low concentration are added.
a, 8014b is formed.

Through the above steps, each semiconductor layer 2
Impurity regions are formed in 02a to 202e. Second shape conductive layers 212, 213 and 21 overlapping the island-shaped semiconductor layers
4 and the third shape conductive layers 328 and 329 function as gate electrodes.

Thus, as shown in FIG. 26K, an N-channel TFT 8361 and an N-channel TFT 836 are provided.
2, P-channel TFT 8363, N-channel TFT
8364 and a P-channel TFT 8365 are formed.

The N-channel TFT 8361 includes a channel region 8392, high-concentration impurity regions 8322a and 8322b corresponding to source and drain regions, and a low-concentration impurity region (Loff region) 832 which does not overlap with the gate electrode.
3a and 8323b. N-channel type TFT 836
Reference numeral 2 denotes high-concentration impurity regions 8324a and 8324 corresponding to the channel region 8393, the source region, and the drain region.
b, low concentration impurity regions (Lov regions) 8325a and 8325b overlapping with the gate electrode are provided. On the other hand, the P-channel TFT 8363 has a high-concentration impurity region 83 corresponding to the channel region 8394, the source region and the drain region.
35a and 8335b. N-channel type TFT 83
61, N channel type TFT 8362 and P channel type T
The gate electrode of FT 8363 has a tapered end portion. Therefore, the TFT has an inappropriate shape for reducing the size of the gate electrode.

Further, the N-channel TFT 8364 has a channel region 8395 and high-concentration impurity regions 8013a and 8013b corresponding to the source region and the drain region. Further, low concentration impurity regions (Loff regions) 8014a and 8014b which do not overlap with the gate electrode are provided. P
The channel TFT 8365 has a channel region 8396,
High concentration impurity regions 8010a and 8010b corresponding to the source region and the drain region are provided. In this embodiment mode, the step of forming the Loff region in the N-channel TFT 8364 is also shown.

N-channel TFT 8361, N-channel TFT 8362, P-channel TFT 8363, N-channel TFT 8364, P-channel TFT 8365.
Since the exposure means for manufacturing each gate electrode is the same as that in the first embodiment, the description thereof is omitted here.

Although the manufacturing process of the single gate type TFT is shown in this embodiment mode, a double gate structure or a multi-gate structure having more gates may be used. In addition, in this embodiment mode, a top-gate TFT is shown and a manufacturing process thereof is shown. However, the method for manufacturing the semiconductor device of the present invention is not limited to the dual gate type TFT
It is also possible to apply to.

By using the method for manufacturing a semiconductor device of the present invention, it is possible to increase the degree of freedom in the shape of electrodes, wirings, etc. of elements other than TFTs formed using gate metal.

(Embodiment Mode 6) In this embodiment mode, an example of a wiring formed of a gate metal in the manufacturing method shown in Embodiment Modes 1 to 5 will be described.
10 and 24 are used for the description.

In the manufacturing method of Embodiment Modes 1 to 5, the step of etching the gate metal using the resist mask formed by the first exposure, and the second step
Focusing on the step of etching the gate metal by using the resist mask formed by the exposure, the method for smoothly connecting the wiring formed in each step will be described. FIG. 10 is used for the description.

FIG. 10A is a top view showing a resist mask 401 formed on the gate metal 400 by the first exposure. FIG. 10B shows a state in which the gate metal 400 is etched using the resist mask 401 of FIG. 10A. Note that FIG. 10B shows a state where the gate metal is vertically etched along the end portion of the resist mask 401. However, when the manufacturing method described in any of Embodiments 1 to 5 is used, the end portion of the wiring has a tapered shape. By the etching process using the resist mask 401, the width L
One wiring 402 is formed.

Then, the resist mask 401 is removed,
A resist mask 403 is formed by the second exposure.
FIG. 10C is a top view showing the resist mask 403 formed by the second exposure. FIG. 10 (D) shows
A state where the gate metal 400 is etched using the resist mask 403 in FIG. 10C is shown. The wiring 404 having a width L2 is formed by etching using the resist mask 401.

Here, by increasing the resolution of the patterning of the second exposure to be higher than the resolution of the patterning of the first exposure, as shown in FIG.
5, the wiring 402 and the wiring 404 can be smoothly connected. That is, the TFT in which the gate electrode is manufactured using the resist mask formed by the first exposure
On the other hand, it is assumed that the TFT in which the gate electrode is manufactured using the resist mask formed by the second exposure needs to be miniaturized. Thus, the wiring 402 and the wiring 404 can be smoothly connected to each other as illustrated in FIG.

Next, in the manufacturing method shown in Embodiment Modes 1 to 5, a cross-sectional view of the wiring formed by the gate metal is shown.

FIG. 24A is a cross-sectional view of a wiring formed by etching a gate metal using a resist mask formed by the first exposure in the manufacturing method of Embodiment Modes 1 to 5. Shown in. 24B is a cross-sectional view of a wiring formed by etching a gate metal using a resist mask formed by second exposure in the manufacturing method of Embodiment Modes 1 to 5. FIG. Show. The wirings 441a and 441b shown in FIG. 24A each have a shape having tapered end portions with a wiring width L1. Wiring 441a,
The wirings 441b are arranged at the wiring interval S1. Further, the wirings 442a and 442b shown in FIG. 24B each have a shape having substantially vertical end portions of the wiring width L2. They are arranged with a wiring interval S1. For comparison, the cross-sectional areas of the wirings 442a and 442b are
It is assumed that the cross-sectional area of each of the wirings 441a and 441b is equal.

The ratio L2 / S1 between the wiring width L2 of the wirings 442a and 442b and the wiring interval S1 is determined by the wirings 441a and 441b.
Can be made smaller than the ratio L1 / S1 between the wiring width L1 and the wiring interval S1. That is, the wirings 442a and 442b
Is a shape suitable for integration.

In this way, in the semiconductor device, the shape of the wiring formed by the gate metal can be appropriately selected. This embodiment mode can be implemented by freely combining with Embodiment Modes 1 to 5.

[0180]

Embodiment 1 In this embodiment, a semiconductor having an arithmetic processing circuit (CPU), a memory circuit, and the like formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. An example of manufacturing the device will be described.

FIG. 5 is a top view of a semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention. In FIG. 5, the semiconductor device includes a display device 551 and a display device 551 including TFTs formed over a substrate 500 having an insulating surface.
And a PU unit 552. The display device 551 includes the pixel unit 5
01, the scanning line driving circuit 502, the signal line driving circuit 503
Have. Further, the CPU unit 552 has a CPU 507, S
It has a RAM (memory circuit) 504. In the display device 551, the pixel portion 501 displays an image. In addition, by the scan line driver circuit 502 and the signal line driver circuit 503,
The input of the video signal to each pixel of the pixel portion is controlled. SR
The AM (memory circuit) 504 is composed of a plurality of memory cells (not shown) arranged in a matrix. Each memory cell has a function of storing a signal input / output in the CPU 507 or the like. The CPU 507 also has a function of outputting a control signal to the scan line driver circuit 502 and the signal line driver circuit 503.

The CPU section 552 may have a GPU (video signal processing circuit) 557. This structure is shown in FIG. The same parts as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. GPU (video signal processing circuit) 55
7, the signal input from the outside of the substrate 500 is converted into a signal to be input to the display device 551.

5 and 27, a case where a liquid crystal display device is used as the display device 551 is shown as an example. As the pixel portion 501 of the liquid crystal display device 551, the configuration shown in FIG. 12 can be used in the problem to be solved by the invention.

In FIG. 12, the TFT 30 which constitutes a pixel
02 is required to have a small off current. this is,
Liquid crystal element 300 arranged in each pixel due to leakage current
This is to prevent the disturbance of the image due to the change of the voltage applied between the electrodes of No. 3 and the change of the transmittance. Also, the pixel TFT
In a liquid crystal display device of a type (transmission type) in which an image is viewed through 3002, the pixel TFT 30 is used in order to increase the aperture ratio.
02 is required to be miniaturized. Further, a voltage of about 16V is usually applied between the electrodes of the liquid crystal element 3003. Therefore, the pixel TFT 3002, etc.
A certain degree of pressure resistance is required. Therefore, Lov area and Lo
It is necessary to use a TFT having a structure having an ff region.

On the other hand, in FIG. 5 and FIG. 27, the pixel drive circuit section (scan line drive circuit 502 and signal line drive circuit 503)
The TFT (pixel drive circuit TFT) that constitutes the
The reduction of off-current and miniaturization are not required as much as FT.
However, since it operates with a power supply voltage of about 16 V, withstand voltage is required.

The arithmetic processing circuit (CPU section) 552 requires a high driving frequency. Therefore, the CPU unit 552
In the TFT (hereinafter, referred to as an arithmetic circuit TFT) constituting the above, it is required to improve carrier mobility and miniaturize. On the other hand, since the arithmetic processing circuit (CPU unit) 552 manufactured by a miniaturized TFT operates with a power supply voltage of about 3 to 5 V, the withstand voltage of the TFT is not required to be as high as that of the pixel TFT or the pixel drive circuit TFT. .

[0187] Therefore, in order to make different TFTs which form the circuits shown in FIG. 5 and FIG. 27, in the third embodiment,
The manufacturing method shown in FIG. 4 is used. The N-channel TFT 361 shown in FIG. 4 is used as a pixel TFT. The N-channel TFT 361 has a high effect of suppressing off current.
It is a structure having a Loff region. Further, the N-channel TFT 362 and the P-channel TFT 36 shown in FIG.
3 is used as a pixel drive circuit TFT. Each of the N-channel TFT 362 and the P-channel TFT 363 has Lov that has a high effect of suppressing deterioration due to hot carriers.
The structure has a region with high pressure resistance. In addition, the N-channel TFT 364 and the P-channel TFT shown in FIG.
365 is used as a TFT for an arithmetic circuit. Each of the N-channel TFT 364 and the P-channel TFT 365 has a shape that can be miniaturized. That is, 16
A portion of the liquid crystal display device 551 that operates with a power supply voltage of about V is manufactured, and a CPU portion 552 that operates with a power supply voltage of about 3 to 5 V is manufactured by a step of manufacturing a gate electrode that follows the second exposure in FIG. ..

Thus, a semiconductor device having an arithmetic processing circuit (CPU), a memory circuit, and the like formed over the same substrate as the display device can be manufactured using TFTs suitable for each circuit.

The present invention can be implemented by freely combining with the first to sixth embodiments.

(Embodiment 2) In this embodiment, a CPU portion (arithmetic processing circuit (CPU), memory circuit, etc.) formed on the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. An example of manufacturing a semiconductor device having: Note that the configurations of the display device and the CPU unit, and the TFTs used in those circuits can be the same as those in the first embodiment.

FIG. 6 shows a cross-sectional view of a semiconductor device manufactured by using the present invention. An N-channel TFT 361 is representatively shown as a pixel TFT forming a pixel portion. In addition, an N-channel type TF is used as an element forming the pixel drive circuit section.
The T362 and the P-channel TFT 363 are shown as representatives. C
An N-channel TFT 36 is used as an element forming the PU unit.
4 and P-channel TFT 365 are shown as representatives. Since the manufacturing method of the N-channel TFT 361, the N-channel TFT 362, the P-channel TFT 363, the N-channel TFT 364, and the P-channel TFT 365 is the same as the manufacturing method shown in FIGS. The description is omitted. The same parts as those in FIG. 4 will be described using the same reference numerals.

As shown in FIG. 6A, a first interlayer insulating film 6036 is formed. The first interlayer insulating film 6036 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method.
In this embodiment, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course, the first interlayer insulating film 6
036 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a heat treatment (heat treatment) is performed,
The crystallinity of the semiconductor layer is recovered and the impurity element added to the semiconductor layer is activated. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed by heat treatment at 410 ° C. for 1 hour. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In addition, heat treatment may be performed before forming the first interlayer insulating film 6036. However, when the gate electrodes of the N-channel type TFT 361, the N-channel type TFT 362, the P-channel type TFT 363, the N-channel type TFT 364 and the P-channel type TFT 365 are vulnerable to heat, it is necessary to protect the wiring or the like as in this embodiment. It is preferable to perform the heat treatment after forming the first interlayer insulating film 6036 (an insulating film containing silicon as a main component, for example, a silicon nitride film).

As described above, the first interlayer insulating film 6036
By performing heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer can be performed at the same time as the activation process. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 6036. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the first interlayer insulating film 60
The semiconductor layer may be hydrogenated regardless of the presence of 36. As other means of hydrogenation, means using plasma-excited hydrogen (plasma hydrogenation), 3 to 10
300 to 450 ° C. in an atmosphere containing 0% hydrogen
Alternatively, the heat treatment may be performed for 1 to 12 hours.

Next, as shown in FIG. 6B, a second interlayer insulating film 6037 is formed on the first interlayer insulating film 6036. An inorganic insulating film can be used as the second interlayer insulating film 6037. For example, a silicon oxide film formed by the CVD method, a silicon oxide film applied by the SOG (Spin On Glass) method, or the like can be used.
An organic insulating film can be used as the second interlayer insulating film 6037. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked-layer structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used. In this embodiment, an acrylic film having a thickness of 1.6 μm is formed. The second interlayer insulating film 6037 can reduce unevenness due to the TFTs (N-channel TFT 361, N-channel TFT 362, P-channel TFT 363, N-channel TFT 364, and P-channel TFT 365) and flatten it. Especially the second
Since the interlayer insulating film 6037 has a strong implication of flattening,
A film having excellent flatness is preferable.

Next, the second interlayer insulating film 6037, the first interlayer insulating film 6036, and the gate insulating film 203 are etched by dry etching or wet etching, and the N-channel TFT 361 and the N-channel TFT 361 are formed.
362, P-channel TFT 363, N-channel TF
Contact holes reaching the source region and the drain region of the T364 and the P-channel TFT 365 are formed. Then, wirings 6040 to 604 electrically connected to the source region and the drain region of each TFT, respectively.
6 and the pixel electrode 6039 are formed. Note that in this embodiment, the wirings 6040 to 6046 and the pixel electrode 6039 are
A laminated film of a Ti film having a film thickness of 50 nm and an alloy film of Al and Ti having a film thickness of 500 nm is continuously formed by a sputtering method and patterned into a desired shape. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The material of the wiring is not limited to Al and Ti, but other conductive films may be used. For example, the wiring may be formed by forming an Al film or a Cu film on the TaN film and then patterning the laminated film having the Ti film formed thereon. However,
It is preferable to use a material having excellent reflectivity.

Subsequently, as shown in FIG. 6C, an alignment film 6047 is formed on a portion including at least the pixel electrode 6039, and rubbing treatment is performed. In this embodiment, the organic resin film such as the acrylic resin film is patterned before the alignment film 6047 is formed, so that the columnar spacer 6048 for holding the space between the substrates is formed at a desired position. Further, the spacers are not limited to the columnar spacers, and spherical spacers may be dispersed over the entire surface of the substrate.

Next, a counter substrate 7000 is prepared. Colored layer (color filter) 7001 on the counter substrate 7000
˜7003, a planarization film 7004 is formed. At this time,
The first coloring layer 7001 and the second coloring layer 7002 are overlapped with each other to form a light-shielding portion, and the second coloring layer 7002 and part of the third coloring layer 7003 are overlapped with each other to form a light-shielding portion. Further, the first coloring layer 7001 and the third coloring layer 7003 may be partly overlapped with each other to form a light-blocking portion. In this way, the number of steps can be reduced by shielding the gaps between the pixels with the light-shielding portion formed of the stacked colored layers without newly forming a light-shielding layer.

Next, a counter electrode 7005 made of a transparent conductive film is formed on the flattening film 7004 at least in a portion corresponding to the pixel portion. After that, an alignment film 7006 is formed over the entire surface of the counter substrate 7005, and rubbing treatment is performed.

Then, the substrate 201 provided with the pixel portion, the driver circuit portion, and the CPU portion and the counter substrate 7000 are attached to each other with a sealant 7007. The sealing material 7007 includes
A filler (not shown) is mixed, and the substrate 201 and the counter substrate 7 are formed by the filler and the columnar spacer 6048.
000 is stuck at a uniform interval. After that, a liquid crystal material 7008 is injected between both substrates (201 and 7000) and completely sealed by a sealing material (not shown). A known material may be used for the liquid crystal material 7008. In this way, the liquid crystal display device is completed.

Then, a polarizing plate and an FPC (not shown) are attached. The FPC connects the terminals routed from the element or circuit formed on the substrate 201 to the external signal terminals. In this way, it is completed as a product.

In this embodiment, a reflection type liquid crystal display device in which the pixel electrode 6039 is formed of a metal film having excellent reflectivity and the counter electrode 7005 is formed of a light-transmitting material is shown as an example. Is not limited to this. For example, the pixel electrode 6
039 is formed of a light-transmitting material, and the counter electrode 700
The present invention can be applied to a transmissive liquid crystal display device in which 5 is formed of a material having reflectivity. The present invention can also be applied to a transflective liquid crystal display device.

This example is the same as the first to sixth embodiments.
And, it is possible to implement by freely combining with the first embodiment.

[Embodiment 3] In this embodiment, a CPU portion (arithmetic processing circuit (CPU), memory circuit, or the like) formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. An example of manufacturing a semiconductor device having: Note that the configurations of the display device and the CPU section, and the TFTs used in those circuits can be the same as those in the first embodiment.

However, in this embodiment, the display device is an OLED display device in which an OLED element is arranged in each pixel. The OLED element has a configuration including an anode, a cathode, and an organic compound layer sandwiched between the anode and the cathode. The OLED element emits light by applying a voltage between the anode and the cathode. The organic compound layer can have a laminated structure. A typical example is a laminated structure of "hole transport layer / light emitting layer / electron transport layer" proposed by Tang et al. Of Kodak Eastman Company. In addition, a hole injection layer / hole transport layer / light emitting layer / electron transport layer or a hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer are laminated in this order on the anode. The structure is fine. You may dope a fluorescent dye etc. with respect to a light emitting layer. All layers provided between the cathode and the anode of the OLED element are collectively referred to as an organic compound layer. Therefore, the above-mentioned hole injection layer, hole transport layer,
The light emitting layer, the electron transport layer, the electron injection layer and the like are all included in the organic compound layer. When a predetermined voltage is applied to the organic compound layer having the above structure from a pair of electrodes (anode and cathode), carriers are recombined in the light emitting layer to emit light. The OLED element emits light (fluorescence) from singlet excitons.
Emission from triplet excitons (phosphorescence)
You may use either or. The OLED display device is attracting attention as a next-generation flat panel display because it has excellent responsiveness, operates at low voltage, and has a wide viewing angle.

FIG. 7 shows a cross-sectional view of a semiconductor device manufactured by using the present invention. As a TFT that constitutes a pixel portion,
A TFT connected in series with an LED element is an N-channel type T
Representatively shown as FT361. In addition, as elements forming the pixel drive circuit section, N-channel TFT 362 and P
The channel TFT 363 is shown as a representative. An N-channel TFT 364 and a P-channel TFT 365 are shown as representatives of the elements constituting the CPU section. N-channel type TFT3
61, N-channel TFT 362, P-channel TFT
363, N-channel TFT 364, P-channel TF
The manufacturing method of T365 is similar to the manufacturing method shown in FIG. 4 in Embodiment Mode 3; therefore, the description is omitted here. The same parts as those in FIG. 4 will be described using the same reference numerals.

According to the third embodiment, the state shown in FIG. 7A is produced. In FIG. 7B, a first interlayer insulating film 5036 is formed. The first interlayer insulating film 5036 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 100 is formed by the plasma CVD method.
A silicon oxynitride film having a thickness of nm is formed. Of course, the first interlayer insulating film 5036 is not limited to the silicon oxynitride film,
Another insulating film containing silicon may be used as a single layer or a laminated structure. Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed by heat treatment at 410 ° C. for 1 hour. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Further, heat treatment may be performed before forming the first interlayer insulating film 5036. However, when the gate electrodes of the N-channel type TFT 361, the N-channel type TFT 362, the P-channel type TFT 363, the N-channel type TFT 364 and the P-channel type TFT 365 are vulnerable to heat, it is necessary to protect the wiring and the like as in this embodiment. It is preferable to perform the heat treatment after forming the first interlayer insulating film 5036 (insulating film containing silicon as a main component, for example, a silicon nitride film).

As described above, the first interlayer insulating film 5036
By performing heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer can be performed at the same time as the activation process. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5036. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5036. As other means of hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation), 3
300-4 in an atmosphere containing ~ 100% hydrogen
Means for performing heat treatment at 50 ° C. for 1 to 12 hours may be used.

Next, on the first interlayer insulating film 5036,
A second interlayer insulating film 5037 is formed. An inorganic insulating film can be used as the second interlayer insulating film 5037. For example, a silicon oxide film formed by the CVD method, a silicon oxide film applied by the SOG (Spin On Glass) method, or the like can be used. Further, an organic insulating film can be used as the second interlayer insulating film 5037.
For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.
In this embodiment, an acrylic film having a thickness of 1.6 μm is formed.
The second interlayer insulating film 5037 can reduce unevenness due to the TFT formed over the substrate 201 and flatten it. In particular, since the second interlayer insulating film 5037 has a strong implication of flattening, a film having excellent flatness is preferable.

Next, the second interlayer insulating film 5037, the first interlayer insulating film 5036, and the gate insulating film 203 are etched by dry etching or wet etching, and the N channel type TFT 361 and the N channel type TFT 361 are etched.
362, P-channel TFT 363, N-channel TF
Contact holes reaching the source region and the drain region of the T364 and the P-channel TFT 365 are formed.

Next, the pixel electrode 50 made of a transparent conductive film.
38 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (ITO), a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, indium oxide, or the like can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 5038 corresponds to the anode of the OLED element. In this embodiment, ITO
Is formed into a film with a thickness of 110 nm and is patterned, and the pixel electrode 5
038 is formed.

Next, each TFT (N-channel type TFT 3
61, N-channel TFT 362, P-channel TFT
363, N-channel type TFT 364 and P-channel type T
FT365) Wirings 5039 to 5046 electrically connected to the respective source and drain regions are formed. Note that in this embodiment, the wirings 5039 to 5046 are used.
Is formed by continuously forming a laminated film of a Ti film having a film thickness of 100 nm, an Al film having a film thickness of 350 nm, and a Ti film having a film thickness of 100 nm by a sputtering method, and patterning the film into a desired shape. Of course, the structure is not limited to the three-layer structure, and may be a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. The material of the wiring is not limited to Al and Ti, but other conductive films may be used. For example, wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed. Thus, one of the source region and the drain region of the N-channel TFT 361 in the pixel portion is electrically connected to the pixel electrode 5038 by the wiring 5039. Here, the wiring 5039 and the pixel electrode 5038 are electrically connected by overlapping part of the pixel electrode 5038 and part of the wiring 5039.

Next, as shown in FIG. 7D, a third interlayer insulating film 5047 is formed. Third interlayer insulating film 504
An inorganic insulating film or an organic insulating film can be used as 7. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used. You can An acrylic resin film or the like can be used as the organic insulating film.

An example of a combination of the second interlayer insulating film 5037 and the third interlayer insulating film 5047 is given below. A stacked film of acrylic and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used as the second interlayer insulating film 5037, and a silicon nitride film formed by a sputtering method is used as the third interlayer insulating film 5047. Alternatively, there is a combination using a silicon nitride oxide film. Second interlayer insulating film 503
There is a combination in which a silicon oxide film formed by the plasma CVD method is used as 7, and a silicon oxide film formed by the plasma CVD method is also used as the third interlayer insulating film 5047. Further, as the second interlayer insulating film 5037, S
There is a combination in which a silicon oxide film formed by the OG method is used and a silicon oxide film formed by the SOG method is also used as the third interlayer insulating film 5047. Further, a stacked film of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037, and an oxidation formed by a plasma CVD method is used as the third interlayer insulating film 5047. There is a combination using a silicon film. Further, as the second interlayer insulating film 5037,
There is a combination in which acrylic is used and acrylic is also used as the third interlayer insulating film 5047. Further, there is a combination in which a stacked film of acrylic and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037, and a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5047. . Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5037 and acrylic is used as the third interlayer insulating film 5047.

Pixel electrode 50 of third interlayer insulating film 5047
An opening is formed at a position corresponding to 38. The third interlayer insulating film 5047 functions as a bank. By using a wet etching method when forming the opening, it is possible to easily form a tapered side wall. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic compound layer due to the step difference becomes a significant problem, so caution is required. Carbon particles or metal particles may be added to the third interlayer insulating film 5047 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 10 ¹²
The addition amount of carbon particles or metal particles may be adjusted so as to be Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

Next, an organic compound layer 5048 is formed on the pixel electrode 5038 exposed in the opening of the third interlayer insulating film 5047. As the organic compound layer 5048, a known organic light emitting material can be used. Note that both an organic light emitting material and an inorganic light emitting material may be used, or an inorganic light emitting material may be used instead of the organic light emitting material.

As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, or a medium molecular weight organic light emitting material can be freely used. The medium-molecular organic luminescent material means an organic luminescent material having no sublimation property and a degree of polymerization of about 20 or less.

In this embodiment, the organic compound layer 5048 is formed by a low molecular weight organic light emitting material by a vapor deposition method.
Specifically, a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70-nm light emitting layer is provided thereon.
nm thick tris-8-quinolinolato aluminum complex (A
1q ₃ ) film is provided to form a laminated structure. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

As an example of using a high molecular organic light emitting material, as a hole injecting layer, polythiophene (PE) having a thickness of 20 nm is used.
A DOT film is provided by a spin coating method, and para-phenylene vinylene (PP) having a thickness of about 100 nm is formed thereon as a light emitting layer.
V) Organic compound layer 5048 having a laminated structure provided with a film
May be configured. By using a PPV π-conjugated polymer, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer and the electron injection layer.

The organic compound layer 5048 is not limited to the one having a layered structure in which the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, etc. are clearly distinguished. That is, the organic compound layer 5048 is a hole injection layer,
A structure having a mixed layer of materials forming the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like may be used.
For example, a mixed layer composed of a material forming an electron transport layer (hereinafter referred to as an electron transport material) and a material forming a light emitting layer (hereinafter referred to as a light emitting material) is referred to as an electron transport layer and a light emitting layer. Organic compound layer 50 having a structure between layers
It may be 48.

Next, a counter electrode 5049 made of a conductive film is provided on the organic compound layer 5048. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. An MgAg film (alloy film of magnesium and silver) may be used. In this embodiment, the counter electrode 504
9 corresponds to the cathode of the OLED element. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added can be freely used.

When the counter electrode 5049 is formed, O
The LED element is completed. Note that an OLED element refers to a diode including a pixel electrode (anode) 5038, an organic compound layer 5048, and a counter electrode (cathode) 5049.

It is effective to provide the passivation film 5050 so as to completely cover the OLED element. The passivation film 5050 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating films can be used as a single layer or a stacked layer in which they are combined. A film with good coverage is a passivation film 505.
It is preferable to use it as 0, a carbon film, especially DLC
It is effective to use a (diamond-like carbon) film. Since the DLC film can be formed in a temperature range of room temperature to 100 ° C. or lower, the organic compound layer 504 having low heat resistance is used.
It is possible to easily form a film on the upper side of 8. Also, DL
The C film has a high blocking effect on oxygen and can suppress oxidation of the organic compound layer 5048.

Note that the steps from the formation of the third interlayer insulating film 5047 to the formation of the passivation film 5050 are continuously performed using a multi-chamber system (or in-line system) film forming apparatus without exposing to the atmosphere. It is effective to process it.

[0225] When the state shown in Fig. 7D is actually completed, a protective film (laminate film, UV curable resin film, etc.) having high airtightness and little degassing and a transparent film are provided so as not to be further exposed to the outside air. It is preferable to perform packaging (encapsulation) with an optical sealing material. At that time, the reliability of the OLED element is improved by making the inside of the sealing material an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

When the airtightness is enhanced by a process such as packaging, a connector (flexible printed circuit: FP) for connecting a terminal routed from an element or a circuit formed on the substrate 201 to an external signal terminal.
C) is attached to complete the product.

This embodiment is the first to sixth embodiments.
Also, it can be implemented by freely combining with the first embodiment.

(Embodiment 4) In this embodiment, a CPU portion (arithmetic processing circuit (CPU), memory circuit, or the like) formed over the same substrate as a display device by using the method for manufacturing a semiconductor device of the present invention. An example of manufacturing a semiconductor device having: Note that the configurations of the display device and the CPU section, and the TFTs used in those circuits can be the same as those in the first embodiment. However, in this embodiment, the display device is an OLED display device in which an OLED element is arranged in each pixel.

FIG. 8 shows a cross-sectional view of a semiconductor device manufactured by using the present invention. As a TFT that constitutes a pixel portion,
A TFT connected in series with an LED element is an N-channel type T
Representatively shown as FT361. In addition, as elements forming the pixel drive circuit section, N-channel TFT 362 and P
The channel TFT 363 is shown as a representative. An N-channel TFT 364 and a P-channel TFT 365 are shown as representatives of the elements constituting the CPU section.

The manufacturing method of the N-channel type TFT 361, the N-channel type TFT 362, the P-channel type TFT 363, the N-channel type TFT 364 and the P-channel type TFT 365 is the same as the manufacturing method shown in FIG. 4 in the third embodiment. The description is omitted here. The same parts as those in FIG. 4 will be described using the same reference numerals.

According to the third embodiment, the state shown in FIG. 8A is produced. As shown in FIG. 8B, a first interlayer insulating film 5101 is formed. This first interlayer insulating film 510
As the first example, a plasma CVD method or a sputtering method is used to form an insulating film containing silicon with a thickness of 100 to 200 nm. In this embodiment, a 100-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course, the first interlayer insulating film 5101 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a heat treatment (heat treatment) is performed,
The crystallinity of the semiconductor layer is recovered and the impurity element added to the semiconductor layer is activated. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the activation treatment is performed by heat treatment at 410 ° C. for 1 hour. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In addition, heat treatment may be performed before forming the first interlayer insulating film 5101. However, when the gate electrodes of the N-channel type TFT 361, the N-channel type TFT 362, the P-channel type TFT 363, the N-channel type TFT 364 and the P-channel type TFT 365 are vulnerable to heat, it is necessary to protect the wiring or the like as in this embodiment. It is preferable to perform the heat treatment after forming the first interlayer insulating film 5101 (insulating film containing silicon as a main component, for example, a silicon nitride film).

As described above, the first interlayer insulating film 5101
By performing heat treatment after forming (an insulating film containing silicon as a main component, for example, a silicon nitride film), hydrogenation of the semiconductor layer can be performed at the same time as the activation process. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5101. Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment. Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5101. As other means of hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation), 3
300-4 in an atmosphere containing ~ 100% hydrogen
Means for performing heat treatment at 50 ° C. for 1 to 12 hours may be used.

Next, on the first interlayer insulating film 5101,
A second interlayer insulating film 5102 is formed. An inorganic insulating film can be used as the second interlayer insulating film 5102. For example, a silicon oxide film formed by the CVD method, a silicon oxide film applied by the SOG (Spin On Glass) method, or the like can be used. An organic insulating film can be used as the second interlayer insulating film 5102. For example, a film of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxide film may be used. Alternatively, a stacked-layer structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used.

Next, the first interlayer insulating film 5101, the second interlayer insulating film 5102, and the gate insulating film 203 are etched by dry etching or wet etching, and each TFT (N channel type TFT 361, N channel type TFT 362, Contact holes reaching the source and drain regions of the P-channel TFT 363, the N-channel TFT 364 and the P-channel TFT 365 are formed.

Next, each TFT (N-channel type TFT 3
61, N-channel TFT 362, P-channel TFT
363, N-channel type TFT 364 and P-channel type T
Wirings 5103 to 5110 electrically connected to the source region and the drain region of the FT 365) are formed. Note that in this embodiment, the wirings 5103 to 5110 are formed into a desired shape by continuously forming a stacked film of a Ti film with a thickness of 100 nm, an Al film with a thickness of 350 nm, and a Ti film with a thickness of 100 nm by a sputtering method. It is formed by patterning. Of course, the structure is not limited to the three-layer structure, and may be a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. The material of the wiring is not limited to Al and Ti, but other conductive films may be used. For example, wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed.

Next, as shown in FIG. 8D, a third interlayer insulating film 5111 is formed. Third interlayer insulating film 511
As 1, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. Also,
An acrylic resin film or the like can be used as the organic insulating film. Alternatively, a stacked-layer structure of an acrylic film and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method may be used. By the third interlayer insulating film 5111, the TFT (N
A channel type TFT 361, an N channel type TFT 362,
P-channel TFT 363, N-channel TFT 364
And P-channel TFT 365) to reduce unevenness,
It can be flattened. In particular, the third interlayer insulating film 51
Since No. 11 has a strong meaning of flattening, a film having excellent flatness is preferable.

Next, by dry etching or wet etching, a contact hole reaching the wiring 5103 is formed in the third interlayer insulating film 5111.

Next, the conductive film is patterned to form a pixel electrode 5112. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. In addition, M
A gAg film (alloy film of magnesium and silver) may be used. The pixel electrode 5112 corresponds to the cathode of the OLED element. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added can be freely used.

The pixel electrode 5112 is the third interlayer insulating film 5
The wiring 5 is formed by the contact hole formed in 111.
An electrical connection is established with 103. Thus, the pixel electrode 5112 is electrically connected to one of the source region and the drain region of the N-channel TFT 361.

Next, a bank 5113 is formed in order to paint the organic compound layer between each pixel separately. The bank 5113 is formed using an inorganic insulating film or an organic insulating film. As the inorganic insulating film, a silicon nitride film or a silicon nitride oxide film formed by a sputtering method, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG method, or the like can be used. An acrylic resin film or the like can be used as the organic insulating film. here,
When forming the bank 5113, a tapered side wall can be easily formed by using a wet etching method. If the side wall of the bank 5113 is not sufficiently gentle, the deterioration of the organic compound layer due to the step difference becomes a significant problem, so caution is required. Note that the pixel electrode 5112
When electrically connecting the wiring 5103 with the wiring 5103, the contact hole formed in the third interlayer insulating film 5111
A bank 5113 is formed. Thus, the unevenness of the pixel electrode due to the unevenness of the contact hole portion is filled with the bank 5113, so that the deterioration of the organic compound layer due to the step is prevented.

Third interlayer insulating film 5111 and bank 5113
An example of the combination of is given below. Third interlayer insulating film 5
A layered film of acrylic and a silicon nitride film or a silicon nitride oxide film formed by a sputtering method is used as 111.
There is a combination of a silicon nitride film or a silicon nitride oxide film formed by a sputtering method as the bank 5113. Plasma CVD as the third interlayer insulating film 5111
There is a combination in which a silicon oxide film formed by a plasma CVD method is used as the bank 5113 as well. In addition, the third interlayer insulating film 51
There is a combination in which a silicon oxide film formed by the SOG method is used as 11, and a silicon oxide film formed by the SOG method is also used as the bank 5113. Further, a combination of using a stacked film of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method as the third interlayer insulating film 5111 and using a silicon oxide film formed by a plasma CVD method as the bank 5113 is a combination. is there.
In addition, there is a combination in which acrylic is used as the third interlayer insulating film 5111 and acrylic is used as the bank 5113. Further, there is a combination in which a stacked film of acrylic and a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5111 and a silicon oxide film formed by a plasma CVD method is used as the bank 5113.
Further, as the third interlayer insulating film 5111, plasma CV is used.
Using a silicon oxide film formed by the D method, the bank 5113
There is a combination using acrylic as. Note that carbon particles or metal particles may be added to the bank 5113 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 10 ¹² Ωm (preferably 1 × 10 ⁶ Ωm).
The addition amount of carbon particles or metal particles may be adjusted so that it becomes × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

Next, an organic compound layer 5114 is formed on the exposed pixel electrode 5112 surrounded by the bank 5113. As the organic compound layer 5114, a known organic light emitting material can be used. Note that both an organic light emitting material and an inorganic light emitting material may be used, or an inorganic light emitting material may be used instead of the organic light emitting material. As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, or a medium molecular weight organic light emitting material can be freely used. The medium-molecular organic luminescent material means an organic luminescent material having no sublimation property and a degree of polymerization of about 20 or less.

In this embodiment, the organic compound layer 5114 is formed using a low molecular weight organic light emitting material by a vapor deposition method.
Specifically, a 70 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided as a light emitting layer, and a 20 nm thick copper phthalocyanine (CuPc) film is provided thereon as a hole injection layer. It has a structure. Alq ₃
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to.

As an example of using a high molecular organic light emitting material, a 20 nm polythiophene (PE
A DOT film is formed by a spin coating method, and para-phenylene vinylene (PP) having a thickness of about 100 nm is formed on the DOT film as a light emitting layer.
V) The organic compound layer 5114 has a laminated structure provided with a film.
May be configured. By using a PPV π-conjugated polymer, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer and the electron injection layer.

The organic compound layer 5114 is not limited to the one having a layered structure in which the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, etc. are clearly distinguished. That is, the organic compound layer 5114 is a hole injection layer,
A structure having a mixed layer of materials forming the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like may be used.
For example, a mixed layer composed of a material forming an electron transport layer (hereinafter referred to as an electron transport material) and a material forming a light emitting layer (hereinafter referred to as a light emitting material) is referred to as an electron transport layer and a light emitting layer. Organic compound layer 51 having a structure between layers
It may be 14.

Next, a counter electrode 5115 made of a transparent conductive film is formed on the organic compound layer 5114. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O), a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide, indium oxide, or the like can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The counter electrode 5115 corresponds to the anode of the OLED element.

At the time when the counter electrode 5115 is formed, O
The LED element is completed. Note that an OLED element refers to a diode including a pixel electrode (cathode) 5112, an organic compound layer 5114, and a counter electrode (anode) 5115.

In this embodiment, since the counter electrode 5115 is formed of the transparent conductive film, the light emitted by the OLED element is emitted toward the side opposite to the substrate 201. In addition, the wiring 5103 is formed by the third interlayer insulating film 5111.
5110 is formed on a layer different from the layer on which the pixel electrode 51 is formed.
Forming twelve. Therefore, the aperture ratio can be increased as compared with the configuration shown in the third embodiment.

It is effective to provide a protective film (passivation film) 5116 so as to completely cover the OLED element. The protective film 5116 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film can be used as a single layer or a stacked layer in which they are combined. When light emitted from the OLED element is emitted from the counter electrode 5115 side as in this embodiment, the protective film 511 is formed.
As 6, it is necessary to use a film that transmits light.

Note that the steps from the formation of the bank 5113 to the formation of the protective film 5116 can be performed continuously by using a multi-chamber type (or in-line type) film forming apparatus without exposing to the atmosphere. It is valid.

In practice, when the state shown in FIG. 8D is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) having high airtightness and less degassing is provided so as not to be exposed to the outside air. It is preferable to perform packaging (encapsulation) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the OL
The reliability of the ED element is improved.

When the airtightness is improved by a process such as packaging, a connector (flexible printed circuit: FP) for connecting a terminal routed from an element or circuit formed on the substrate 201 and an external signal terminal.
C) is attached to complete the product.

This example is the same as the first to sixth embodiments.
Also, it can be implemented by freely combining with the first embodiment.

(Embodiment 5) In this embodiment, in manufacturing a semiconductor active layer of a TFT included in the semiconductor device of the present invention,
An example of a method of crystallizing a semiconductor film is shown.

Plasma C is used as a base film on a glass substrate.
Silicon oxynitride film (composition ratio Si = 32%, O
= 59%, N = 7%, H = 2%) 400 nm. Subsequently, an amorphous silicon film of 150 nm is formed as a semiconductor film on the base film by a plasma CVD method. Then, heat treatment is performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film, and then the semiconductor film is crystallized by a laser annealing method.

As the laser used in the laser annealing method, a continuous wave YVO ₄ laser is used. As the condition of the laser annealing method, the second harmonic (wavelength 532 nm) of the YVO ₄ laser was used as the laser light. The semiconductor film formed on the surface of the substrate was irradiated with laser light as a beam having a predetermined shape by an optical system.

The shape of the beam with which the substrate is irradiated can be changed depending on the type of laser and the optical system. In this way, the aspect ratio and energy density distribution of the beam irradiated on the substrate can be changed.
For example, the shape of the beam with which the substrate is irradiated can be various shapes such as a linear shape, a rectangular shape, and an elliptical shape. In this embodiment, the second harmonic of the YVO ₄ laser is made into an ellipse of 200 μm × 50 μm by an optical system and is irradiated on the semiconductor film.

Here, laser light was formed on the surface of the substrate.
FIG. 1 is a schematic diagram of an optical system used when irradiating a semiconductor film.
4 shows. Laser light emitted from the laser 1101 (Y
VO _FourLaser second harmonic) via mirror 1102
Then, the light enters the convex lens 1103. Laser light is convex
It is obliquely incident on the pixel 1103. Do this
As a result, the focus position shifts due to aberrations such as astigmatism,
Form an elliptical beam 1106 at or near the plane of incidence.
Can be made. And formed in this way
While irradiating the elliptical beam 1106
Glass substrate 1 in the direction indicated by 7 or in the direction indicated by 1108
Move 105. Thus, on the glass substrate 1105
In the semiconductor film 1104 formed on the
Irradiation is performed while moving 1106 relatively. The ellipse
The relative scanning direction of the circular beam 1106 is an elliptical beam.
The direction perpendicular to the major axis of the frame 1106. In this embodiment,
The incident angle φ of the laser beam with respect to the convex lens 1103 is about 20.
Form an elliptical beam of 200 μm × 50 μm
Then, the glass substrate 1105 is moved at a speed of 50 cm / s.
While irradiating, the semiconductor film is crystallized.

The crystalline semiconductor film thus obtained was subjected to Secco etching, and the surface was observed by SEM at 10,000 times. The results are shown in FIG. The secco solution for secco etching is prepared by using HF: H ₂ O = 2: 1 and K ₂ Cr ₂ O ₇ as an additive. Figure 15
Is obtained by relatively scanning the laser light in the direction indicated by the arrow in the figure. It can be seen that large-sized crystal grains are formed parallel to the scanning direction of the laser light. That is, the crystal is grown so as to extend in the scanning direction of the laser light.

As described above, large-sized crystal grains are formed in the semiconductor film crystallized by the method of this embodiment. Therefore, when a TFT is manufactured using the semiconductor film as a semiconductor active layer, the number of crystal grain boundaries included in the channel formation region of the TFT can be reduced.
In addition, since the inside of each crystal grain has crystallinity that can be regarded as a substantially single crystal, high mobility (field effect mobility) similar to that of a transistor including a single crystal semiconductor can be obtained.

Further, by disposing the TFT so that the carrier moving direction is aligned with the extending direction of the formed crystal grains, the number of times the carriers cross the crystal grain boundaries can be extremely reduced. Therefore, variations in the on-current value (the drain current value that flows when the TFT is in the on state), the off current value (the drain current value that flows when the TFT is in the off state), the threshold voltage, the S value, and the field effect mobility. Can be reduced, and the electrical characteristics are significantly improved.

Note that, in order to irradiate the elliptical beam 1106 over a wide area of the semiconductor film, an operation of scanning the elliptical beam 1106 in the direction perpendicular to its major axis and irradiating the semiconductor film (hereinafter referred to as scanning). Have been done multiple times.
Here, the position of the elliptical beam 1106 is shifted in a direction parallel to its long axis for each scan. Further, the scanning direction is reversed between successive scans. Here, in two consecutive scans, one is called a forward scan and the other is called a backward scan.

The size of shifting the position of the elliptical beam 1106 in the direction parallel to its long axis for each scan is expressed as the pitch d. In the forward scan,
In the region where large-sized crystal grains as shown in 5 are formed,
The length of the elliptical beam 1106 in the direction perpendicular to the scanning direction is denoted by D1. In the return scan, FIG.
The length in the direction perpendicular to the scanning direction of the elliptical beam 1106 in the region in which large-sized crystal grains are formed as shown in
Notated as D2. The average value of D1 and D2 is D. At this time, the overlap ratio R _OL [%] is defined by Expression 1.

[0265]

[Formula 1] R _OL = (1-d / D) × 100

In this embodiment, the overlap ratio R _{OL is set} to 0%.

This example is the same as the first to sixth embodiments.
Also, it is possible to freely combine with the first to fourth embodiments.

(Embodiment 6) In this embodiment, in manufacturing a semiconductor active layer of a TFT included in the semiconductor device of the present invention,
An example different from that of Example 5 in the method of crystallizing the semiconductor film will be described.

The steps up to the formation of the amorphous silicon film as the semiconductor film are the same as in the fifth embodiment. After that, JP-A-7
Using the method described in Japanese Patent Application Laid-Open No. 183540, a nickel acetate aqueous solution (concentration in weight: 5 ppm, volume: 10 ml) is applied onto the semiconductor film by spin coating, and 5
Heat treatment is performed in a nitrogen atmosphere at 00 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Subsequently, the crystallinity of the semiconductor film is improved by the laser annealing method.

As the laser used in the laser annealing method, a continuous wave YVO ₄ laser is used. The conditions of the laser annealing method are that the second harmonic (wavelength 532 nm) of the YVO ₄ laser is used as the laser beam, and the incident angle φ of the laser beam with respect to the convex lens 1103 in the optical system shown in FIG.
Is set to about 20 ° to form an elliptical beam of 200 μm × 50 μm. The crystallinity of the semiconductor film is improved by irradiating the elliptical beam while moving the glass substrate 1105 at a speed of 50 cm / s. The elliptical beam 11
The relative scanning direction of 06 is a direction perpendicular to the major axis of the elliptical beam 1106.

The crystalline semiconductor film thus obtained was subjected to Secco etching, and the surface was observed by SEM at 10,000 times. The result is shown in FIG. FIG. 16 is obtained by relatively scanning the laser light in the direction indicated by the arrow in the figure, and shows a state in which large-sized crystal grains are formed extending in the scanning direction. Recognize.

As described above, since large-sized crystal grains are formed in the semiconductor film crystallized using the present invention,
When a TFT is manufactured using the semiconductor film, the number of crystal grain boundaries included in the channel formation region can be reduced. In addition, since each crystal grain has crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor using a single crystal semiconductor.
It is also possible to obtain

Furthermore, the formed crystal grains are aligned in one direction. Therefore, by arranging the TFT so that the moving direction of the carrier is aligned with the extending direction of the formed crystal grain, the number of times the carrier crosses the crystal grain boundary can be extremely reduced. Therefore, the ON current value, OFF current value,
It is also possible to reduce variations in threshold voltage, S value, and field effect mobility, and electrical characteristics are significantly improved.

Note that in order to irradiate the elliptical beam 1106 over a wide area of the semiconductor film, the operation (scan) of scanning the elliptical beam 1106 in the direction perpendicular to its major axis and irradiating the semiconductor film is performed a plurality of times. ing. Here, the position of the elliptical beam 1106 is shifted in a direction parallel to its long axis for each scan. Further, the scanning direction is reversed between successive scans. Here, in two consecutive scans, one is called a forward scan and the other is called a backward scan.

The size of shifting the position of the elliptical beam 1106 in the direction parallel to its long axis for each scan is expressed as the pitch d. Further, in the forward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 1106 in the region in which large-sized crystal grains are formed as shown in FIG. 16 is expressed as D1. In the return scan,
In a region where large-sized crystal grains as shown in 6 are formed,
The length of the elliptical beam 1106 in the direction perpendicular to the scanning direction is represented by D2. The average value of D1 and D2 is D
And

At this time, the overlap rate R _OL [%] is defined as in the case of the equation 1. In this embodiment, the overlap ratio R _OL is 0%.

Further, the result of Raman scattering spectroscopy of the semiconductor film (indicated as Improved CG-Silicon in the figure) obtained by the above crystallization method is shown in FIG. 17 by a bold line. Here, for comparison, the results of Raman scattering spectroscopy of single crystal silicon (indicated as ref. (100) Si Wafer in the figure) are shown by thin lines. Also,
After the amorphous silicon film is formed, heat treatment is performed to release hydrogen contained in the semiconductor film, and then the semiconductor film is crystallized using a pulse oscillation excimer laser (in the figure, excimer laser
The result of Raman scattering spectroscopy (denoted as annealing) is shown by the dotted line in FIG. The Raman shift of the semiconductor film obtained by the method of this example has a peak of 517.3 cm ⁻¹ . The full width at half maximum is 4.96 cm ^-1 . On the other hand, the Raman shift of single crystal silicon has a peak of 520.7 cm ^-1 . The full width at half maximum is 4.44 cm ^-1 . The Raman shift of the semiconductor film crystallized using a pulsed excimer laser is 516.3 cm ⁻¹ .
The full width at half maximum is 6.16 cm ^-1 . From the results of FIG. 17, the crystallinity of the semiconductor film obtained by the crystallization method shown in this embodiment is higher than that of a semiconductor film crystallized using a pulse oscillation excimer laser as compared with a single crystal. You can see that it is close to silicon.

This example is the same as the first to sixth embodiments.
Also, it is possible to freely combine with the first to fourth embodiments.

(Embodiment 7) In this embodiment, an example of manufacturing a TFT using the semiconductor film crystallized by the method shown in Embodiment 5 will be described with reference to FIGS. 14, 18 and 19.

In this example, attention is paid to a TFT having a gate electrode manufactured by the same etching process, and a manufacturing method thereof will be described. At this time, the description of differently forming the gate electrode corresponding to the TFT and the doping process as in the first to fifth embodiments is omitted. In practice, this example is implemented in combination with the methods shown in the first to fifth embodiments.

In this embodiment, a glass substrate is used as the substrate 20, and plasma C is used as the base film 21 on the glass substrate.
Silicon oxynitride film (composition ratio Si = 32%, O
= 27%, N = 24%, H = 17%) 50 nm, silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7)
%, H = 2%) 100 nm. Next, an amorphous silicon film of 150 nm is formed as a semiconductor film 22 on the base film 21 by a plasma CVD method. And 500 ℃
Is heat-treated for 3 hours to release hydrogen contained in the semiconductor film. (Figure 18 (A))

Then, continuous oscillation YVO was used as laser light.
Convex lens 1103 in the optical system shown in FIG. 14 using the second harmonic of _four lasers (wavelength 532 nm, 5.5 W).
The incident angle φ of the laser beam with respect to
An elliptical beam 1106 of m × 50 μm is formed. The semiconductor film 22 is irradiated with the elliptical beam 1106 which is relatively scanned at a speed of 50 cm / s. Thus, the semiconductor film 23 is formed. (Fig. 18 (B))

Then, the first doping process is performed. This is the channel dope for controlling the threshold.
B ₂ H ₆ was used as the material gas, the gas flow rate was 30 sccm,
Current density 0.05μA, acceleration voltage 60kV, dose 1x
It is performed at 10 ¹⁴ atoms / cm ² . Thus, the semiconductor film 24
To form. (Fig. 18 (C))

Then, patterning is performed to etch the semiconductor film 24 into a desired shape. After that, a silicon oxynitride film having a thickness of 115 nm is formed by a plasma CVD method as the gate insulating film 27 which covers the etched semiconductor films 25 and 26. Then, a TaN film 28 having a film thickness of 30 nm and a film thickness of 370 n are formed on the gate insulating film 27 as a conductive film.
A W film 29 of m is laminated. (Figure 18 (D))

A mask (not shown) made of a resist is formed by photolithography, and the W film and TaN are formed.
The film and the gate insulating film are etched. Thus, the conductive layers 30 (30a, 30b), 31 (31a, 31b) and the gate insulating film 32 (32a, 32b) are formed.

Then, the resist mask is removed.
Then, a new mask 33 is formed and a second doping process is performed.
And introducing an impurity element imparting N-type conductivity into the semiconductor film.
It In this case, the conductive layers 30a and 31a impart N type
It becomes a mask against the impurity element, and the impurities are self-aligned.
Region 34 is formed. In this embodiment, the second doping is performed.
There are two conditions for the treatment, because the semiconductor film is as thick as 150 nm.
Divided into In this embodiment, the material gas is phosphine.
In (PH₃), And the dose amount is 2 × 10¹³atoms / cm²
And the acceleration voltage is 90 kV, and the dose is 5
× 10¹⁴atoms / cm ²And set the acceleration voltage to 10 kV.
U (Fig. 18 (E))

Next, after removing the mask 33 made of resist, a new mask 35 made of resist is formed and a third doping process is performed. By the third doping process, the impurity region 36 in which the impurity element imparting P-type is added to the semiconductor film to be the active layer of the P-channel TFT
To form. The conductive layers 30b and 31b are used as masks for the impurity element, and the impurity element imparting P-type is added to form the impurity region 36 in a self-aligned manner. In the present embodiment, the third doping process is also performed under two conditions because the thickness of the semiconductor film is as thick as 150 nm. In this embodiment, diborane (B ₂ H ₆ ) is used as the material gas, the dose amount is 2 × 10 ¹³ atoms / cm ² , the acceleration voltage is 90 kV, and then the dose amount is 1 × 10 ¹⁵ atoms / cm 2. ² and
The acceleration voltage is set to 10 kV. (Fig. 18 (F))

Through the above steps, the impurity regions 34 and 36 are formed in the respective semiconductor layers.

Next, the mask 35 made of resist is removed, and the first interlayer insulating film 37 is formed by the plasma CVD method.
As a silicon oxynitride film having a film thickness of 50 nm (composition ratio Si = 3
2.8%, O = 63.7%, N = 3.5%).

Next, heat treatment is performed to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers. In this embodiment, a thermal annealing method using a furnace annealing furnace is used to perform 550 ° C. in a nitrogen atmosphere.
Heat treatment is performed for 4 hours. (Fig. 18 (G))

Next, a second interlayer insulating film 38 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 37. In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by the CVD method, and then a silicon oxide film having a thickness of 400 nm is formed. Then, when heat treatment is performed, hydrogenation treatment can be performed. In this embodiment, a furnace annealing furnace is used to perform heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere.

Subsequently, a wiring 39 electrically connected to each impurity region is formed. In this embodiment, the film thickness is 50
A Ti film having a thickness of 500 nm, an Al—Si film having a thickness of 500 nm, and a Ti film having a thickness of 50 nm are patterned to form a laminated film. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The material of the wiring is not limited to Al and Ti. For example, wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed. (Fig. 18
(H))

As described above, the N-channel TFT 51 and the P-channel TFT 52 having the channel length of 6 μm and the channel width of 4 μm are formed.

FIG. 1 shows the results of measurement of these electrical characteristics.
9 shows. FIG. 1 shows the electrical characteristics of the N-channel TFT 51.
The electrical characteristics of the P-channel TFT 52 are shown in FIG. 9 (A) and FIG. 19 (B). The electrical characteristics were measured at two measurement points, the gate voltage Vg = -16 to 16V, and the drain voltage Vd = 1V and 5V. In FIG. 19, the drain current (ID) and the gate current (IG) are shown by solid lines, and the mobility (μFE) is shown by dotted lines.

Since large-sized crystal grains are formed in the semiconductor film crystallized by using the present invention, when a TFT is manufactured using the semiconductor film, the crystal grains included in the channel formation region are formed. The number of circles can be reduced. Furthermore, since the formed crystal grains are aligned in one direction, the number of times the carriers cross the crystal grain boundaries can be extremely reduced. Therefore, a TFT having good electric characteristics can be obtained as shown in FIG. Especially mobility is N channel TF
It can be seen that T is 524 cm ² / Vs and P-channel TFT is 205 cm ² / Vs. When a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.

This example is the same as the first to sixth embodiments.
Also, it is possible to freely combine with the first to fourth embodiments.

(Embodiment 8) In this embodiment, an example in which a TFT is manufactured using the semiconductor film crystallized by the method shown in Embodiment 6 will be described with reference to FIGS. 14 and 20 to 23. In this embodiment, attention is paid to a TFT having a gate electrode manufactured by the same etching process,
The manufacturing method will be described. At this time, the description of differently forming the gate electrode corresponding to the TFT and the doping process as in the first to fifth embodiments is omitted.
In practice, this example is implemented in combination with the methods shown in the first to fifth embodiments.

The steps up to the formation of the amorphous silicon film as the semiconductor film are the same as in Example 7. The amorphous silicon film was formed to a thickness of 150 nm. (Figure 20 (A))

Then, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (concentration in terms of weight: 5 ppm,
A volume of 10 ml) is applied to form the metal-containing layer 41.
Then, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Thus, the semiconductor film 42 was obtained. (Figure 20 (B))

Next, the crystallinity of the semiconductor film 42 is improved by the laser annealing method. The conditions of the laser annealing method are that the second harmonic (wavelength 532 nm, 5.5 W) of the continuous wave YVO ₄ laser is used as the laser light, and the incident angle φ of the laser light with respect to the convex lens 1103 in the optical system shown in FIG. An elliptical beam 1106 of 200 μm × 50 μm is formed at about 20 °. The elliptical beam 11
06 is irradiated while moving the substrate at a speed of 20 cm / s or 50 cm / s to improve the crystallinity of the semiconductor film 42. Thus, the semiconductor film 43 is obtained. (Fig. 20
(C))

The steps after crystallization of the semiconductor film of FIG. 20C are shown in FIG. 18C to FIG.
This is the same as the step (H). Thus, the channel length is 6μ
An n-channel TFT 51 and a p-channel TFT 52 having a width of m and a channel width of 4 μm are formed. These electrical characteristics were measured.

The electrical characteristics of the TFT manufactured by the above process are shown in FIGS. 21, 22 and 23. FIG. 21 (A)
Further, FIG. 21B shows electric characteristics of a TFT manufactured by moving the substrate at a speed of 20 cm / s in the laser annealing step of FIG. In FIG. 21 (A), N
The electrical characteristics of the channel TFT 51 are shown. Also in FIG.
(B) shows the electrical characteristics of the P-channel TFT 52. In addition, in FIG. 22A and FIG.
In the laser annealing step of (C), the substrate speed is set to 5
The electrical characteristics of the TFT manufactured by moving at 0 cm / s are shown. FIG. 22A shows the electrical characteristics of the N-channel TFT 51. In addition, in FIG. 22B, a P-channel TF
The electrical characteristics of T52 are shown. The electrical characteristics were measured under the conditions of gate voltage Vg = −16 to 16V and drain voltage Vd = 1V and 5V. 21 and 22, the drain current (ID) and the gate current (I
G) is a solid line, and mobility (μFE) is a dotted line.

Since large-sized crystal grains are formed in the semiconductor film crystallized by using the present invention, when a TFT is manufactured using the semiconductor film, the crystal grains included in the channel formation region are formed. The number of circles can be reduced. Furthermore, since the formed crystal grains are aligned in one direction and few grain boundaries are formed in a direction intersecting the relative scanning direction of the laser light, the number of times carriers cross the crystal grain boundaries is extremely small. Can be reduced.

Therefore, a TFT having good electric characteristics can be obtained as shown in FIGS. Especially mobility
In FIG. 21, in an N-channel TFT, 510 cm ² /
200 cm ² / V for Vs and P-channel TFT
22 and 59 in the N-channel TFT in FIG.
5 cm ² / Vs, 199c in P-channel TFT
It can be seen that it is very excellent at m ² / Vs. And
When a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.

FIG. 23 shows electric characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. FIG. 23
(A) shows the electrical characteristics of the N-channel TFT 51. 23B shows the electrical characteristics of the P-channel TFT 52.

The electrical characteristics are measured under the conditions of gate voltage Vg = -16 to 16V and drain voltage Vd =
It was set to 0.1V and 5V.

As shown in FIG. 23, T having good electrical characteristics
FT is obtained. In particular, the mobility is 657 cm ² / Vs in the N-channel TFT shown in FIG.
219c in the P-channel TFT shown in FIG.
It can be seen that it is very excellent at m ² / Vs. And
When a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.

This embodiment is the first to sixth embodiments.
Also, it is possible to freely combine with the first to fourth embodiments.

(Embodiment 9) In this embodiment, an example of a display system manufactured by using the present invention will be described with reference to FIGS.

Here, the display system is a display device or C
It is assumed that the board on which the PU portion is formed also includes a circuit externally attached by an FPC or the like. As a method for manufacturing the display device and the CPU, Embodiment Modes 1 to 6 and Example 1 to Example 8 are used. FIG. 28 shows a configuration example of the display system.

A circuit having the structure shown in FIG. 5 or FIG. 27 is formed on the substrate 500. Here, FIG.
An example using the circuit having the configuration shown in FIG. Display system 7
00, the FPC 710 causes the substrate 500, the power supply circuit 701, the clock oscillation circuit 702, the VRAM 703,
The ROM 704 and the WRAM 705 are electrically connected. Here, the power supply circuit 701 is a circuit that converts power supplied to the display system 700 into power for the circuit formed on the substrate 500. The clock oscillator circuit 702 is
This is a circuit for inputting a control signal such as a clock signal to a circuit formed on the substrate 500. The VRAM 703 is the GPU 5
This is a circuit for storing the video signal of the format input to 07. The ROM 704 is a circuit in which information for controlling the CPU 507 and a video signal input to the display system 700 are stored. The WRAM 705 is the CPU 507.
Is a work area for processing.

The SRAM provided on the substrate 500
504 and WRAM7 connected by FPC710
Since both 05 function as a work area of the CPU 507, either one can be omitted.
For example, if the CPU 507 is frequently accessed but a relatively small storage capacity is required, it is preferable to use the SRAM 504, and conversely, a large storage capacity is required, but CP
If access from U507 is relatively low, WRA
It is preferable to use M705.

(Embodiment 10) In this embodiment, examples of electronic devices manufactured by using the present invention will be described with reference to FIGS.

As an electronic device manufactured by using the present invention,
Video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound reproduction devices (car audio systems, audio components, etc.), notebook personal computers, game devices, personal digital assistants (mobile computers, mobile phones,
An image reproducing device provided with a recording medium such as a portable game machine or an electronic book (specifically, Digital Versatile Disc (D)
VD) and other recording media are reproduced, and a device equipped with a display capable of displaying the image) is included. Specific examples of these electronic devices are shown in FIGS.

FIG. 13A shows a display device, which is a housing 14
01, a support base 1402, and a display unit 1403. The present invention can be applied to the display device that constitutes the display portion 1403. By using the present invention, reduction in size and weight of a display device can be realized.

FIG. 13B shows a video camera, which includes a main body 1411, a display portion 1412, a voice input 1413, operation switches 1414, a battery 1415, and an image receiving portion 1416.
Etc. The present invention has a display portion 1412.
It can be applied to the display device constituting the. By using the present invention, the size and weight of the video camera can be reduced.

FIG. 13C shows a laptop personal computer, which is composed of a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The present invention can be applied to a display device that constitutes the display portion 1423. By using the present invention, downsizing and weight saving of a personal computer can be realized.

FIG. 13D shows a portable information terminal which includes a main body 1431, a stylus 1432, a display portion 1433, operation buttons 1434, an external interface 1435, and the like. The present invention can be applied to a display device that constitutes the display unit 1433. By using the present invention, it is possible to reduce the size and weight of the portable information terminal.

FIG. 13E shows a sound reproducing device, specifically, a vehicle-mounted audio device, which is composed of a main body 1441, a display portion 1442, operation switches 1443 and 1444 and the like. The present invention can be applied to a display device that constitutes the display unit 1442. Further, although the vehicle-mounted audio device is taken as an example this time, it may be used as a portable or home audio device. By using the present invention, it is possible to reduce the size and weight of the sound reproducing device.

FIG. 13F shows a digital camera including a main body 1451, a display portion (A) 1452, an eyepiece portion 1453,
The operation switch 1454, the display portion (B) 1455, the battery 1456, and the like are included. The present invention can be applied to a display device that forms the display portion (A) 1452 and the display portion (B) 1455. By using the present invention, it is possible to reduce the size and weight of a digital camera.

FIG. 13G shows a mobile phone, which has a main body 14
61, voice output unit 1462, voice input unit 1463, display unit 1464, operation switch 1465, antenna 1466.
Etc. The present invention has a display portion 1464.
It can be applied to the display device constituting the. By using the present invention, the size and weight of a mobile phone can be reduced.

For the display device used in these electronic devices, not only a glass substrate but also a heat-resistant plastic substrate can be used. Thereby, the weight can be further reduced.

The present invention is not limited to the above electronic equipment, and uses the semiconductor device manufactured by the manufacturing method shown in Embodiment Modes 1 to 6 and Examples 1 to 8.
It can be various electronic devices.

[0324]

The gate metal is partially etched for each TFT having different required characteristics to form a gate electrode. That is, the resist is exposed for each TFT having different required characteristics to form a resist mask, and the gate metal is etched. At this time, the gate electrode manufacturing process of each TFT is performed under conditions optimized according to the required characteristics. In this way, it is possible to provide a method for manufacturing a semiconductor device in which a plurality of TFTs having different characteristics or different design rules can be separately manufactured on the same substrate.

Therefore, circuits having various functions can be manufactured on the same substrate. In this way, it is possible to fabricate a circuit, which has been conventionally mounted externally with an IC chip or the like, on the same substrate, and to reduce the size and weight of the device. In addition, since it is possible to separately manufacture a plurality of TFTs having different characteristics with a smaller number of masks, it is possible to reduce the number of steps and the cost.

[0326]

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a method for manufacturing a semiconductor device of the present invention.

2A to 2D are diagrams showing a method for manufacturing a semiconductor device of the present invention.

3A to 3D are diagrams illustrating a method for manufacturing a semiconductor device of the present invention.

4A to 4C are diagrams showing a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a top view of a semiconductor device of the present invention.

6A to 6C are diagrams showing a method for manufacturing a semiconductor device having a liquid crystal display device or the like of the present invention.

7A to 7C are diagrams showing a method for manufacturing a semiconductor device having an OLED display device or the like of the present invention.

FIG. 8 is a diagram showing a method for manufacturing a semiconductor device having an OLED display device of the present invention.

9A to 9C are diagrams showing a conventional method for manufacturing a semiconductor device.

10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a circuit diagram showing a structure of a pixel portion of a liquid crystal display device.

FIG. 13 is a diagram showing an electronic device of the invention.

FIG. 14 is a schematic diagram of an optical system used for laser annealing.

FIG. 15 is an SEM observation image of a semiconductor thin film of a TFT formed by the method for manufacturing a semiconductor device of the present invention.

FIG. 16 is an SEM observation image of a semiconductor thin film of a TFT formed by the method for manufacturing a semiconductor device of the present invention.

FIG. 17 is a graph showing characteristics of a semiconductor active layer of a TFT formed by the method for manufacturing a semiconductor device of the present invention.

FIG. 18 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 19 is a diagram showing electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.

20A to 20C are diagrams illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 21 is a diagram showing electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.

FIG. 22 is a diagram showing electrical characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.

FIG. 23 is a diagram showing electric characteristics of a TFT formed by a method for manufacturing a semiconductor device of the present invention.

FIG. 24 is a diagram showing a shape of a wiring formed by a method for manufacturing a semiconductor device of the present invention.

25A to 25C are diagrams showing a method for manufacturing a semiconductor device of the present invention, which follows FIG. 4C.

26A to 26C are diagrams showing a method for manufacturing a semiconductor device of the present invention, which follows FIG. 4C.

FIG. 27 is a top view of the semiconductor device of the invention.

FIG. 28 is a diagram showing a display system using a semiconductor device of the present invention.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 617J F term (reference) 2H092 JA25 JA38 KA17 KB03 KB22 KB24 KB25 MA08 MA16 MA17 MA27 NA21 5F052 AA02 AA11 AA17 AA24 BA02 BA07 BB02 BB05 BB07 DA02 DA03 DB02 DB03 DB07 EA12 EA15 EA16 FA06 JA01 JA03 JA04 5F110 AA30 BB02 BB03 BB04 BB07 CC02 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE22 EE23 EE28 EE30 EE32 EE44 EE45 FF02 FF04 FF09 FF28 FF30 FF36 GG01 GG02 GG13 GG25 GG28 GG29 GG32. PP35 PP38 QQ02 QQ04 QQ09 QQ10 QQ11 QQ19 QQ23 QQ24 QQ25 QQ28

Claims (17)

[Claims] 1. A method of manufacturing a semiconductor device having a first TFT and a second TFT in which a gate electrode is formed of the same conductive layer, wherein a first resist mask is formed by a first exposure means. A first step of forming, and a first step of forming the conductive layer by using the first resist mask.
A second step of forming a gate electrode of the first TFT by etching the area of the first TFT, and a third step of forming a second resist mask by a second exposure means after the second step. And a fourth step of forming a gate electrode of the second TFT by etching a second region of the conductive layer, which is different from the first region, using the second resist mask. In the second step, a gate electrode having tapered ends is manufactured, and in the fourth step, a gate electrode having vertical ends is manufactured. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first exposure means and the second exposure means have different resolutions. 3. A method of manufacturing a semiconductor device having a first TFT and a second TFT in which a gate electrode is formed of the same conductive layer, wherein a first resist mask is formed by a first exposure means. A first step of forming, and a first step of forming the conductive layer by using the first resist mask.
A second step of forming a gate electrode of the first TFT by etching the area of the first TFT, and a third step of forming a second resist mask by a second exposure means after the second step. And a fourth step of forming a gate electrode of the second TFT by etching a second region of the conductive layer, which is different from the first region, using the second resist mask. A method of manufacturing a semiconductor device, wherein the first exposure unit and the second exposure unit have different resolutions. 4. The method according to claim 2 or 3, wherein one of the first exposure unit and the second exposure unit uses an equal-magnification projection exposure apparatus, and the other uses a reduction projection exposure apparatus. A method for manufacturing a semiconductor device, comprising: 5. The semiconductor device according to claim 2, wherein the first exposure unit and the second exposure unit have different wavelengths of light used for exposure. Manufacturing method. 6. The method according to claim 1, wherein the first resist mask covers a second region of the conductive layer, and the second resist mask is the first resist mask. A method for manufacturing a semiconductor device, which covers a gate electrode of a TFT. 7. A method of manufacturing a semiconductor device having a first TFT and a second TFT, in which a gate electrode is formed of the same conductive layer, wherein a first resist mask is formed by a first exposure means. A first step of forming, and a first step of forming the conductive layer by using the first resist mask.
The second step of forming the gate electrode of the first TFT by etching the region of the first TFT, and after the second step, the semiconductor active layer of the first TFT is doped with the first impurity element. A third step, a fourth step of forming a second resist mask by a second exposure unit after the third step, and a step of forming the first region using the second resist mask. Etching a second region of the different conductive layer to form a gate electrode of the second TFT, and after the fifth step, on the semiconductor active layer of the second TFT, A sixth step of doping with a second impurity element, and a method for manufacturing a semiconductor device. 8. A method of manufacturing a semiconductor device having a first TFT and a second TFT, in which a gate electrode is formed of the same conductive layer, wherein a first resist mask is formed by a first exposure means. A first step of forming, and a first step of forming the conductive layer by using the first resist mask.
The second step of forming the gate electrode of the first TFT by etching the region of the first TFT, and after the second step, the semiconductor active layer of the first TFT is doped with the first impurity element. A third step, a fourth step of forming a second resist mask by a second exposure unit after the third step, and a step of forming the first region using the second resist mask. Etching a second region of the different conductive layer to form a gate electrode of the second TFT, and after the fifth step, on the semiconductor active layer of the second TFT, A sixth step of doping a second impurity element; and, after the sixth step, doping a third impurity element into the semiconductor active layer of the first TFT and the semiconductor active layer of the second TFT. And a seventh step of A method for manufacturing a semiconductor device. 9. A method of manufacturing a semiconductor device having a first TFT and a second TFT, in which a gate electrode is formed of the same conductive layer, wherein a first resist mask is formed by a first exposure means. A first step of forming, and a first step of forming the conductive layer by using the first resist mask.
A second step of forming a gate electrode of the first TFT by etching the area of the first TFT, and a third step of forming a second resist mask by a second exposure means after the second step. A fourth step of etching a second region of the conductive layer different from the first region using the second resist mask to form a gate electrode of the second TFT; After the step of 4, there is a fifth step of doping an impurity element into the semiconductor active layer of the first TFT and the semiconductor active layer of the second TFT. 10. The method according to claim 7, wherein in the second step, the first region of the conductive layer is etched to form a conductive layer having a first shape. And a ninth step of doping the semiconductor active layer of the first TFT with a fourth impurity element after the eighth step, and the first shape after the ninth step. And a tenth step of manufacturing the gate electrode of the first TFT by etching the conductive layer of. 11. The eighth process according to claim 7, wherein in the second step, the first region of the conductive layer is etched to form a conductive layer having a first shape. And a ninth step of doping the semiconductor active layer of the first TFT with a fourth impurity element after the eighth step, and etching the conductive layer having the first shape, A tenth step of forming a conductive layer having a second shape; an eleventh step of doping the semiconductor active layer of the first TFT with a fifth impurity element after the tenth step; After the eleventh step, a twelfth step of etching the second-shaped conductive layer to form a gate electrode of the first TFT, the method for manufacturing a semiconductor device. 12. The method according to claim 7, wherein the first resist mask covers the second region of the conductive layer, and the second resist mask is the first resist mask. A method for manufacturing a semiconductor device, which covers a gate electrode of a TFT. 13. The method for manufacturing a semiconductor device according to claim 7, wherein the first exposure unit and the second exposure unit have different resolutions. 14. The method according to claim 13, wherein one of the first exposure unit and the second exposure unit uses a unit-magnification projection exposure apparatus, and the other uses a reduction projection exposure apparatus. Manufacturing method of semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 13, wherein the first exposure unit and the second exposure unit have different wavelengths of light used for exposure. 16. The semiconductor film forming a semiconductor active layer of the first TFT and the second TFT according to claim 1, wherein a semiconductor film using a continuous wave laser beam is used for the semiconductor film. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is crystallized. 17. An electronic device manufactured by using the method for manufacturing the semiconductor device according to claim 1. Description: