JP4761646B2 - Non-volatile memory - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically writable and erasable semiconductor nonvolatile memory (EEPROM or Electrically Erasable and Programmable Read Only Memory). The present invention also relates to a semiconductor device composed of a thin film transistor (hereinafter referred to as TFT) formed using SOI (Silicon On Insulator) technology. In particular, the present invention relates to a semiconductor device in which a semiconductor nonvolatile memory, a pixel portion, and a driver circuit for the pixel portion are integrally formed on a substrate having an insulating surface.
[0002]
In this specification, an electrically writable and erasable semiconductor non-volatile memory (EEPROM) literally indicates an entire semiconductor non-volatile memory capable of electrical writing and erasing, for example, full function. EEPROM and flash memory are included in the category. In addition, unless otherwise specified, nonvolatile memory and semiconductor nonvolatile memory are used synonymously with EEPROM. In this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics. For example, an electro-optical device typified by a liquid crystal display device and an EL display device, and an electronic device on which the electro-optical device is mounted. Includes equipment in its category.
[0003]
[Prior art]
In recent years, multi-function and high-performance small semiconductor devices typified by portable devices such as portable computers and mobile phones are rapidly spreading. Along with this, a semiconductor nonvolatile memory has been attracting attention as a memory constituting a semiconductor device. Although the semiconductor nonvolatile memory is inferior in storage capacity as compared with a magnetic disk, it has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like. Recently, those having sufficient performance in the number of rewrites and data retention time, which have been problems of the semiconductor nonvolatile memory, have been developed, and the movement to use the semiconductor nonvolatile memory as a substitute for the magnetic disk has increased. It was.
[0004]
Semiconductor nonvolatile memories are roughly classified into two types: full-function EEPROMs and flash memories. The full function EEPROM is a semiconductor non-volatile memory capable of erasing bit by bit, and can perform writing, reading and erasing operations every bit. Although it has a higher function than a flash memory, it is inferior in integration and cost. On the other hand, a flash memory is a semiconductor nonvolatile memory that performs batch erase of the entire memory or erase in units of blocks of the memory, and realizes high integration density and low cost at the expense of erase operation for each bit.
[0005]
Here, a full-function EEPROM having a higher function is taken up as a conventional semiconductor nonvolatile memory, and a circuit diagram, a sectional view of a memory cell, and a driving method will be described.
[0006]
FIG. 4 shows a circuit diagram of a conventional full-function EEPROM. In FIG. 4, a full-function EEPROM includes a memory cell array 405 in which a plurality of memory cells (1, 1) to (n, m) are arranged in a matrix of vertical m × horizontal n, an X address decoder 401, and a Y address decoder. 402, and other peripheral circuits 403 and 404. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary.
[0007]
Each memory cell (considering memory cell (i, j) as a representative) (where i is an integer of 1 to n and j is an integer of 1 to m) includes an n-channel memory transistor Tr1 and an n-channel memory transistor Tr1. A selection transistor Tr2 is included, and these two transistors are connected in series. The source electrode and control gate electrode of the memory transistor Tr1 are connected to the source line Si and the word line Wj, respectively, and the drain electrode and gate electrode of the selection transistor Tr2 are connected to the bit line Bi and the selection line Vj, respectively. . The bit lines B1 to Bn are connected to the Y address decoder 402, the word lines W1 to Wm and the selection lines V1 to Vm are connected to the X address decoder 401, respectively, and the source lines S1 to Sn all share a predetermined potential Vs. Is given.
[0008]
When the memory transistor included in each memory cell records 1-bit data, the full-function EEPROM shown in FIG. 4 has a storage capacity of m × n bits.
[0009]
Data writing, reading and erasing are performed in one memory cell selected by the X address decoder 401 and the Y address decoder 402. Taking the memory cell (1, 1) as an example, the write, read and erase operations will be described. Note that in this specification, a writing operation represents an operation of injecting electrons into the floating gate electrode of the memory transistor, and an erasing operation represents an operation of emitting electrons from the floating gate electrode. Accordingly, the threshold voltage of the memory transistor is increased by the write operation, and the threshold voltage is decreased by the erase operation.
[0010]
First, when writing data into the memory transistor Tr1, the source lines S1 to Sn are dropped to GND, and a positive high voltage (for example, 20 V) is applied to the bit line B1 and the word line W1, respectively. Further, a positive voltage (for example, 20 V) is applied to the selection line V1 so that the selection transistor Tr2 is turned on. Under such conditions, a high electric field is generated near the drain of the memory transistor Tr1, and impact ionization occurs. Further, since a high electric field is generated in the gate direction, the generated hot electrons are injected into the floating gate electrode, and as a result, writing is performed. The threshold voltage of the memory transistor Tr1 changes depending on the amount of charge accumulated in the floating gate electrode.
[0011]
When reading data stored in the memory transistor Tr1, the source lines S1 to Sn are dropped to GND and a predetermined voltage (described later) is applied to the word line W1. Further, a voltage that turns on the selection transistor is applied to the selection line V1 (for example, 5 V). Then, the data stored in the memory cell is read from the bit line B1 according to the threshold voltage when the charge is accumulated in the floating gate electrode of the memory transistor Tr1 and when the charge is not accumulated.
[0012]
The predetermined voltage is a threshold voltage in an erased state (a state in which electrons are not accumulated in the floating gate electrode) and a threshold voltage in a written state (a state in which electrons are accumulated in the floating gate electrode). What is necessary is just to set between voltages. For example, if the memory transistor in the erased state has a threshold voltage of 2V or less and the memory transistor in the written state has a threshold voltage of 4V or more, 3V is set as the predetermined voltage, for example. Can be used.
[0013]
When erasing data stored in the memory transistor Tr1, the source line S1 and the word line W1 are dropped to GND, and a positive high voltage (for example, 20 V) is applied to the bit line B1. Further, a positive high voltage (for example, 20 V) is applied to the selection line V1, and the selection transistor Tr2 is turned on. At this time, since a high potential difference is generated between the gate and the drain of the memory transistor Tr1, electrons accumulated in the floating gate electrode are emitted to the drain region by a tunnel current, and erasing is performed.
[0014]
Note that the potentials of the signal lines B2 to Bn and W2 to Wm which are not selected at the time of writing, reading and erasing are all 0V. Moreover, the value of the operating voltage described above is an example, and the value is not limited to that value.
[0015]
In order to perform the operation for each bit, at the time of writing, reading and erasing to the selected memory cell (1, 1), all the memory cells other than the non-selected memory cell (in this case, the memory cell (1, 1)) The cell must not be written, read or erased. Actually, in the memory cells other than the first row, since the selection lines V2 to Vn are 0 V, the selection transistor is turned off, and writing and erasing to the memory transistor are not performed, and there is no influence at the time of reading. Further, in the memory cells other than the first column, no potential difference is generated between the source line and the bit line, so that writing to the memory cell is not performed and there is no influence at the time of reading. Since no potential difference occurs between the word line and the bit line, erasing is not performed.
[0016]
As described above, the write, read, and erase operations to the selected memory cell (1, 1) are performed without causing the non-selected memory cell to malfunction.
[0017]
Finally, FIG. 5 shows a typical cross-sectional structure of a memory cell constituting a conventional full-function EEPROM. In FIG. 5, a memory transistor Tr 1 (n-channel type) and a selection transistor Tr 2 (n-channel type) are formed on a p-type silicon substrate 500. The memory transistor Tr1 includes source / drain regions (high-concentration n-type impurity regions) 501 and 502 and a channel formation region 504 formed near the surface of the silicon substrate 500, a first gate insulating film 506, a floating gate electrode 508, A second gate insulating film 510 and a control gate electrode 511 are included. The selection transistor Tr2 includes source / drain regions (high-concentration n-type impurity regions) 502 and 503, a channel formation region 505, a first gate insulating film 507, and a gate electrode 509 formed near the surface of the silicon substrate 500. Has been. Further, a source wiring 513 and a drain wiring 514 are drawn out over the interlayer film 512 through contact holes.
[0018]
In FIG. 5, the drain region 502 and the floating gate electrode 508 of the memory transistor Tr1 partially overlap with each other with the first gate insulating film 506 interposed therebetween. This overlapped region is a region for flowing a tunnel current in the erase operation.
[0019]
[Problems to be solved by the invention]
It has already been mentioned that semiconductor non-volatile memory is classified into two types: full-function EEPROM and flash memory. A full-function EEPROM is a memory that can be operated bit by bit and is excellent in function. However, the full-function EEPROM has a problem that the memory cell storing 1-bit data is composed of two transistors, that is, a memory transistor and a selection transistor, so that the memory cell area is large and the integration density is low. This hinders miniaturization and cost reduction of the full-function EEPROM.
[0020]
The flash memory can be said to be one of the forms realizing high integration density in the semiconductor nonvolatile memory. A memory cell constituting the flash memory is composed of one memory transistor, and realizes a high integration density at the expense of an erase operation for each bit. In a flash memory, all data must be erased in order to rewrite one bit of data. Therefore, the power consumption is larger than that of a full-function EEPROM, and the reliability is lowered because rewriting is performed even in a memory cell that does not require rewriting. Of course, the flash memory cannot be used for applications that require a 1-bit erase operation.
[0021]
In view of this, it can be said that one of the most important problems in the semiconductor nonvolatile memory is to realize a full-function EEPROM having a high integration density. Such an EEPROM will become an indispensable memory not only for the replacement of the conventional full-function EEPROM, but also for a flash memory and various applications that require high functionality due to the miniaturization and cost reduction. Is expected.
[0022]
The present invention has been made in view of the above circumstances. It is an object of the present invention to provide a full-function EEPROM capable of high integration density and the reduction in size and cost associated therewith. In addition, by forming such a semiconductor nonvolatile memory integrally on a substrate having an insulating surface with components of other semiconductor devices constituted by TFTs, a multifunctional or high-functional and small-sized semiconductor device is provided. The task is to do.
[0023]
[Means for Solving the Problems]
In the conventional full-function EEPROM, since the memory cell is composed of two transistors, a memory transistor and a selection transistor, it is difficult to realize a high integration density. In this case, the cause that hinders the improvement of the integration density is obvious, because the selection transistor that does not perform the memory function is added to the area per bit.
[0024]
The flash memory achieves high integration simply by removing this selection transistor. However, since the selection transistor that performs the function of selecting the memory cell is removed, the operation for each bit is not perfect as a price. The basic idea of the present invention is to add a memory function to the selection transistor in order to realize high integration. By leaving the function as the selection transistor, a semiconductor nonvolatile memory capable of operating for each bit is realized.
[0025]
In the present invention, the semiconductor nonvolatile memory is constituted by a memory cell composed of two memory transistors. The circuit structure of the memory cell is such that a selection transistor is replaced with a memory transistor in a conventional full function EEPROM.
[0026]
The semiconductor non-volatile memory of the present invention is a full-function EEPROM capable of operating for each bit. Further, since two transistors constituting the memory cell both have a memory function, one memory cell can store twice as much data as a conventional full-function EEPROM. Therefore, the semiconductor nonvolatile memory of the present invention has a memory capacity that is twice as large as the conventional full-function EEPROM, and the memory cell area per bit is halved. As a result, according to the present invention, it is possible to provide a full-function EEPROM capable of high integration density and the accompanying reduction in size and cost.
[0027]
Further, the semiconductor nonvolatile memory of the present invention does not require any new process, and the number of masks is the same as that of a conventional full function EEPROM. Therefore, the change from the conventional full-function EEPROM to the nonvolatile memory of the present invention is easy in terms of technology and cost.
[0028]
In the present invention, the semiconductor nonvolatile memory may be formed on a silicon substrate, an SOI substrate, or a substrate having an insulating surface.
[0029]
In particular, in the case of a memory transistor formed on a substrate having an insulating surface (hereinafter referred to as a memory TFT), an arbitrary circuit (typically, a pixel portion, driving of the pixel portion) constituted by a TFT. In the semiconductor device having a circuit), the semiconductor nonvolatile memory of the present invention is newly formed as a memory portion and is incorporated into the system, whereby a multifunctional, high-functional and small-sized semiconductor device can be provided. Become.
[0030]
The configuration of the present invention is shown below.
[0031]
A non-volatile memory comprising at least a memory cell array in which memory cells are arranged in a matrix and a drive circuit for the memory cells,
A non-volatile memory is provided in which the memory cell includes two memory transistors.
[0032]
A memory cell array in which memory cells are arranged in a matrix, a memory cell driving circuit, a plurality of first word lines, a plurality of second word lines, a plurality of bit lines, and a plurality of source lines; A non-volatile memory comprising at least
The memory cell has a first memory transistor and a second memory transistor;
The first memory transistor and the second memory transistor are connected in series,
A gate electrode of the first memory transistor is connected to the first word line;
A gate electrode of the second memory transistor is connected to the second word line;
The remaining one of the source electrode or drain electrode of the first memory transistor is connected to the bit line;
A non-volatile memory is provided in which the remaining one of the source electrode and the drain electrode of the second memory transistor is connected to the source line.
[0033]
The non-volatile memory is preferably capable of writing for each bit and erasing for each bit.
[0034]
The memory cell is preferably written and erased by a tunnel current.
[0035]
The source line and the bit line connected to the memory cell to be written may have the same potential at the time of writing.
[0036]
The first and second memory transistors respectively include a source region, a drain region, a channel formation region, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode. And at least
In each of the first and second memory transistors, one or both of the source region and the drain region and the floating gate electrode partially overlap with each other through the first gate insulating film. Is preferred.
[0037]
Both of the two memory transistors constituting the memory cell may be n-channel transistors.
[0038]
Both of the two memory transistors constituting the memory cell may be p-channel transistors.
[0039]
The memory cell array and the drive circuit for the memory cell can be integrally formed on a substrate having an insulating surface.
[0040]
A pixel portion in which a plurality of pixels are arranged in a matrix on a substrate having an insulating surface, a pixel driving circuit including TFTs for driving the plurality of pixels, and the nonvolatile memory according to claim 9. A semiconductor device comprising at least
The pixel portion, the pixel driver circuit, and the nonvolatile memory are integrally formed on a substrate having the insulating surface.
[0041]
A liquid crystal display device or an EL display device is provided as the semiconductor device.
[0042]
As the semiconductor device, a display, a video camera, a DVD player, a head mounted display, a personal computer, a mobile phone, and a car audio are provided.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
A circuit diagram, a driving method, and a cross-sectional structure of a memory cell of the nonvolatile memory of the present invention will be described.
[0044]
FIG. 1 shows a circuit diagram of an m × n-bit nonvolatile memory of the present invention (m and n are integers of 1 or more, respectively). The nonvolatile memory according to the present embodiment includes a memory cell array 105 in which m × n memory cells (1, 1) to (n, m) are arranged in a matrix of m vertical × n horizontal, memory cell array 105 The driving circuit includes an X address decoder 101, a Y address decoder 102, and other peripheral circuits 103 and 104. Each memory cell includes two memory transistors Tr1 and Tr2. When each memory transistor stores 1-bit data, the nonvolatile memory of this embodiment has a storage capacity of m × n × 2 bits. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary.
[0045]
The memory transistors Tr1 and Tr2 may be either n-channel or p-channel conductive transistors, but in the present embodiment, they are n-channel transistors (see Example 3 for p-channel transistors). In this embodiment, a case where one memory transistor stores 1-bit data is considered. However, one memory transistor can store data of 2 bits or more by a multi-value technique. When one memory transistor stores k bits (k is an integer equal to or greater than 1), the storage capacity of the nonvolatile memory according to the present embodiment is m × n × 2 × k bits.
[0046]
The memory transistor constituting the nonvolatile memory of the present invention may be formed on any of a bulk silicon substrate, an SOI substrate, and a substrate having an insulating surface. In addition, a small nonvolatile memory is realized by forming a memory cell driving circuit (in this embodiment, the X address decoder 101 and the Y address decoder 102) and other peripheral circuits 103 and 104 over the same substrate. can do.
[0047]
In particular, when the nonvolatile memory of the present invention is constituted by a memory TFT formed on a substrate having an insulating surface, it can be integrally formed with any part of a semiconductor device constituted by the TFT. A highly functional and small semiconductor device can be provided (see Examples 5, 6 and 9).
[0048]
In FIG. 1, each memory cell (considering memory cell (i, j) as a representative) (i is an integer between 1 and n and j is an integer between 1 and m) is divided into two memory transistors Tr1 and Tr2, respectively. These two memory transistors Tr1 and Tr2 are connected in series. The source electrode and control gate electrode of the memory transistor Tr1 are connected to the source line Si and the first word line Waj, respectively, and the drain electrode and control gate electrode of the memory transistor Tr2 are connected to the bit line Bi and the second word line Wbj, respectively. Each is connected. The bit lines B1 to Bn and the source lines S1 to Sn are connected to the Y address decoder 102, and the first word lines Wa1 to Wam and the second word lines Wb1 to Wbm are connected to the X address decoder 101, respectively.
[0049]
Next, the cross-sectional structure of the memory cell constituting the nonvolatile memory of the present invention will be described. FIG. 3 shows an example of a cross-sectional structure of a memory cell formed over a substrate having an insulating surface.
[0050]
In FIG. 3, two memory TFTs 316 and 317 constituting a memory cell are formed on a substrate 300 having an insulating surface. The memory TFT 316 includes a semiconductor active layer including source / drain regions 301 and 302 and a channel formation region 304, a first gate insulating film 306, a floating gate electrode 308, a second gate insulating film 310, and a control gate electrode 311. Has been. Similarly, the memory TFT 317 includes a semiconductor active layer including source / drain regions 302 and 303 and a channel formation region 305, a first gate insulating film 307, a floating gate electrode 309, a second gate insulating film 310, and a control gate electrode 312. It is constituted by. On the interlayer film 313, a source electrode 314 and a drain electrode 315 are drawn out through contact holes.
[0051]
In addition, the memory TFT 316 has a region where the source region 301 and the floating gate electrode 308 partially overlap with each other through the first gate insulating film 306, and the memory TFT 317 includes the drain region 303 and the floating gate electrode 309 in the first region. A region partially overlapping with the gate insulating film 307 is provided. This region (hereinafter referred to as an overlap region) is a region for allowing a tunnel current to flow between the floating gate electrode and the source / drain region. As will be described later, the position of the overlap region is related to the operation method of the nonvolatile memory.
[0052]
The non-volatile memory of the present invention is characterized in that a memory transistor having a memory function is used as a selection transistor as compared with a conventional full-function EEPROM. As a result, the nonvolatile memory of the present invention can store 2-bit data for one memory cell, and data can be written, read and erased completely in 1-bit units.
[0053]
In this case, a driving method different from that of the conventional full function EEPROM is used particularly in the writing operation. Specifically, instead of performing hot electron injection, writing by tunneling current is performed. At that time, it is desirable that the source lines are not applied with a common potential, but are connected to a coder with a Y address in the same manner as the bit lines so that a potential can be selectively applied. Hereinafter, taking the memory cell (1, 1) as an example, the writing, reading and erasing operation methods in the memory transistors Tr1 and Tr2 will be described.
[0054]
First, when data is written to the memory transistor Tr1, for example, the source line S1 and the bit line B1 are set to −10V, the first word line Wa1 is set to 10V, and the second word line Wb1 is set to 0V. As a result, the memory transistor Tr1 is turned on, and a high potential difference is generated between the control gate electrode and the channel region. Then, electrons are injected from the channel region into the floating gate by the tunnel current, and writing is performed. In addition, the second word line Wb1 has a value that prevents a potential difference (also referred to as stress) between the control gate electrode, the source electrode, and the drain electrode of the memory transistor Tr2 from being small, and prevents erroneous writing in the memory transistor Tr2. It is necessary.
[0055]
Writing to the memory transistor Tr2 can be performed in the same manner as writing to the memory transistor Tr1. For example, the source line S1 and the bit line B1 may be −10V, the first word line Wa1 may be 0V, and the second word line Wb1 may be 10V. As a result, a high potential difference is generated between the control gate electrode and the drain electrode of the memory transistor Tr2, and electrons are injected (written) into the floating gate due to a tunnel current. On the other hand, only a stress of about 10 V is applied to the memory transistor Tr1, and writing is not performed.
[0056]
Further, the stress in memory cells (also referred to as non-selected memory cells) other than the memory cells (1, 1) is about 10 V at most, and writing is not performed.
[0057]
Next, a read operation will be described. When reading the data stored in the memory transistor Tr1, for example, 0V is applied to the source line S1, a predetermined voltage (described later) is applied to the first word line Wa1, and the memory transistor Tr2 is turned on to the second word line Wb1. A voltage is applied to achieve a state (for example, 8V). As a result, the state (ON or OFF) of the memory transistor Tr1 is determined according to the threshold voltage, and the conduction state (conduction or non-conduction) between the source line S1 and the bit line B1 is determined. Data can be read from the bit line B1.
[0058]
The predetermined voltage is a threshold voltage in an erased state (a state in which electrons are not accumulated in the floating gate electrode) and a threshold voltage in a written state (a state in which electrons are accumulated in the floating gate electrode). What is necessary is just to set between voltages. For example, when the erased memory transistor has a threshold voltage of −1 V or more and 2 V or less, and the written memory transistor has a threshold voltage of 4 V or more and 7 V or less, For example, 3V can be used as the voltage.
[0059]
The same applies to the case of reading data stored in the memory transistor Tr2. For example, the source line S1 is set to 0V, the first word line Wa1 is set to a voltage such that the memory transistor Tr2 is turned on (for example, 8V), and the second word line Wb1 is set to the predetermined voltage (for example, 3V). It is good to apply.
[0060]
Note that all the non-selected memory cells (1, 2) to (1, m) in the same column as the memory cell (1, 1) to be selected need to be non-conductive. In other words, in the memory cells (1, 2) to (1, m), the memory transistor Tr1 or Tr2 needs to be in an off state. In particular, when the threshold distribution is expanded to 0 V or less, there is a possibility of causing a malfunction due to the above-described operating voltage. This problem can be eliminated in several ways. For example, when the threshold voltage distribution of the erased memory transistor is −5 V or more, the memory transistor to be read is Tr1, the source line S1 is 5 V, the first word line Wa1 is 8 V, the second word By setting the line Wb1 to 13 V, all the non-selected memory transistors are turned off and no malfunction occurs. In addition, by providing a verify circuit as a peripheral circuit, it is possible to eliminate a malfunction during reading by a method such as controlling the distribution of the threshold voltage in the erased state to 0 V or more, or using a split gate structure as the memory element. it can.
[0061]
Finally, data erasure will be described. The erase operation uses a tunnel current in the opposite direction to the write operation. When erasing is performed in the memory transistor Tr1, for example, the source line S1 and the bit line B1 are set to 10V, the first word line Wa1 is set to −10V, and the second word line Wb1 is set to 0V. At this time, the memory transistor Tr1 is turned off, and a high potential difference is generated between the control gate electrode and the source electrode. As a result, a tunnel current flows in the overlap region between the control gate electrode and the source electrode, and electrons are emitted from the floating gate to the source region. That is, erasure is performed.
[0062]
The same applies when erasing is performed in the memory transistor Tr2. For example, the source line S1 and the bit line B1 may be 10V, the first word line Wa1 may be 0V, and the second word line Wb1 may be −10V.
[0063]
Further, in the non-selected memory cell, the stress is about 10 V at most, and erroneous erasure is not performed.
[0064]
In the above-described operation method, the potentials of the bit lines B2 to Bn, the source lines S2 to Sn, the first word lines Wa2 to Wam, and the second word lines Wb2 to Wbm that are not selected at the time of writing and reading are All are 0V.
[0065]
As described above, the nonvolatile memory of the present invention can store 2-bit data for one memory cell, and data can be written, read and erased completely in 1-bit units. The nonvolatile memory of the present invention is a full function EEPROM. Compared with a conventional full-function EEPROM having a memory cell composed of one memory transistor and one selection transistor, the integration density is doubled.
[0066]
Of course, the value of the operating voltage described above is an example, and is not limited to that value. Actually, the voltage applied to the memory transistor includes the first gate insulating film, the second gate insulating film, the capacitance between the control gate electrode and the floating gate electrode, the size of the overlap region, etc. Depends on. The operating voltage of the memory transistor changes accordingly.
[0067]
The value of the operating voltage may be any value within a range that does not cause malfunction in the non-selected memory cell while maintaining the potential difference necessary for performing the write, read and erase operations in the selected memory cell. It does not matter.
[0068]
Note that in the operation method of this embodiment, a common potential is not applied to the source line, but the source line is connected to a driver circuit (in this embodiment, a Y address decoder), so that The circuit structure is such that a potential can be selectively applied. With such a circuit structure, there is a disadvantage that the peripheral circuit area increases somewhat, but it is possible to ensure a wide margin of operation. Further, the conventional full-function EEPROM has a problem that a large potential difference is generated between the source and the drain at the time of erasing, so that power consumption increases and a load on the circuit increases. According to the driving method of the present embodiment, since the source line and the bit line have the same potential at the time of erasing, current due to the potential difference between the source and drain does not flow, and such a problem does not occur.
[0069]
The nonvolatile memory of the present invention can simultaneously perform erasing and writing of a plurality of memory transistors. In particular, erasing and writing can be performed simultaneously in units of one memory cell (two memory transistors), one vertical column, one horizontal row, a plurality of vertical columns, a plurality of horizontal rows, all memory cells, and the like. For example, in the case where writing to two memory transistors Tr1 and Tr2 is performed simultaneously in one memory cell (1, 1), the source line S1 and the bit line B1 are set to −10 V, the first word line Wa1 and the second The word line Wb1 may be set to 10V. When erasing is simultaneously performed, the source line S1 and the bit line B1 may be set to 10V, and the first word line Wa1 and the second word line Wb1 may be set to −10V.
[0070]
Example 1
In this embodiment, as an example of the nonvolatile memory of the present invention, a 2048-bit nonvolatile memory composed of p-channel memory transistors is taken up, and a circuit diagram and a driving method will be described.
[0071]
FIG. 6 shows a circuit diagram of the nonvolatile memory of the present embodiment. The nonvolatile memory shown in FIG. 6 includes a memory cell array 605 in which 1024 memory cells (1, 1) to (32, 32) are arranged in a matrix of 32 vertical × 32 horizontal, an X address decoder 601, A Y address decoder 602 and other peripheral circuits 603 and 604 are included. Each memory cell is composed of two p-channel type memory transistors Tr1 and Tr2. When each memory transistor stores 1-bit data, the nonvolatile memory of this embodiment has a storage capacity of 2048 bits. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary.
[0072]
Each memory cell (considering memory cell (i, j) as a representative) (i and j are integers of 1 to 32) each have two memory transistors Tr1 and Tr2, and these two memory transistors Tr1 And Tr2 are connected in series. The source electrode and control gate electrode of the memory transistor Tr1 are connected to the source line Si and the first word line Waj, respectively, and the drain electrode and control gate electrode of the memory transistor Tr2 are connected to the bit line Bi and the second word line Wbj, respectively. Each is connected. The bit lines B1 to B32 and the source lines S1 to S32 are connected to the Y address decoder 602, and the first word lines Wa1 to Wa32 and the second word lines Wb1 to Wb32 are connected to the X address decoder 601.
[0073]
The nonvolatile memory of this embodiment can store 2-bit data for one memory cell, and data can be written, read and erased completely in 1-bit units. The operation method is similar to the operation method of the n-channel nonvolatile memory described in the embodiment mode, in which writing and erasing are performed with a tunnel current. The operation method of the p-channel type nonvolatile memory will be briefly described below.
[0074]
For the write operation and the erase operation, the same operation voltage as that in the embodiment can be used. For example, when erasing the memory transistor Tr1 in the memory cell (1, 1), the source line S1 and the bit line B1 are 10V, the first word line Wa1 is −10V, and the second word line Wb1 is 0V. Good. Further, when writing to the memory transistor Tr1 in the memory cell (1, 1), when the source line S1 and the bit line B1 are −10V, the first word line Wa1 is 10V, and the second word line Wb1 is 0V. Good. When writing and erasing are performed on the memory transistor Tr2, the potential of the first word line and the potential of the second word line may be interchanged. The stress in the non-selected memory cell is about 10 V at the time of writing and erasing, and erroneous writing and erasing are not performed.
[0075]
At the time of writing and erasing, the p-channel memory transistor is in the opposite state (on or off) to the n-channel memory transistor. That is, in the p-channel type, the memory transistor that performs writing is turned off, and the memory transistor that performs erasing is turned on. As a result, the erase operation is performed by a tunnel current flowing through the channel region, and the write operation is performed by a tunnel current flowing through an overlap region between the control gate electrode and the source / drain electrodes. When the operation voltage described above is used, a tunnel current at the time of writing flows between the floating gate electrode and the source region of the memory transistor Tr1 or between the floating gate electrode and the drain region of the memory transistor Tr2. Therefore, it is necessary to form the overlap region between the floating gate electrode and the source region of the memory transistor Tr1 and between the floating gate electrode and the drain region of the memory transistor Tr2.
[0076]
Next, the read operation will be described by taking the memory cell (1, 1) as an example. When reading the data stored in the memory transistor Tr1, for example, 0V is applied to the source line S1, a predetermined voltage (described later) is applied to the first word line Wa1, and the memory transistor Tr2 is turned on to the second word line Wb1. A voltage that is in a state (for example, −5 V) is applied. As a result, the state (ON or OFF) of the memory transistor Tr1 is determined according to the threshold voltage of the memory transistor Tr1, and the conductive state (conductive or nonconductive) between the source line S1 and the bit line B1 is determined. Data stored in Tr1 can be read from bit line B1.
[0077]
The predetermined voltage is a threshold voltage in an erased state (a state in which electrons are not accumulated in the floating gate electrode) and a threshold voltage in a written state (a state in which electrons are accumulated in the floating gate electrode). What is necessary is just to set between voltages. For example, when the memory transistor in the erased state has a threshold voltage of −4V to −1V and the memory transistor in the written state has a threshold voltage of 1V to 4V, For example, 0V can be used as the voltage.
[0078]
The same applies to the case of reading data stored in the memory transistor Tr2. For example, the source line S1 is set to 0V, the first word line Wa1 is set to a voltage at which the memory transistor Tr2 is turned on (for example, −5V), and the second word line Wb1 is set to the predetermined voltage (for example, 0V). May be applied.
[0079]
Note that all the non-selected memory cells (1, 2) to (1, 32) in the same column as the memory cell (1, 1) to be selected need to be non-conductive. Assuming the above-described threshold voltage distribution, the threshold voltage of the memory transistor in the written state is 0 V or higher, so that the memory cell having the memory transistor in the written state becomes conductive, causing a malfunction. It becomes. As a method for suppressing such malfunction, when the memory transistor to be read is set to Tr1, for example, the source line S1 is set to -5V, the first word line Wa1 is set to -5V, and the second word line Wb1 is set to -10V. Good. In this case, if the threshold voltage of the memory transistor Tr1 or Tr2 is 5 V or less, no malfunction occurs. In addition, malfunctions at the time of reading can also be suppressed by a method such as providing a verify circuit as a peripheral circuit or a memory element having a split gate structure.
[0080]
Note that the potentials of the bit lines B2 to B32, the source lines S2 to Sn, the first word lines Wa2 to Wa32, and the second word lines Wb2 to Wb32 that are not selected in the above-described operation method are all 0V.
[0081]
Of course, the value of the operating voltage described above is an example, and is not limited to that value. The value of the operating voltage may be any value within a range that does not cause malfunction in the non-selected memory cell while maintaining the potential difference necessary for performing the write, read and erase operations in the selected memory cell. It does not matter.
[0082]
In addition, the nonvolatile memory of this embodiment can simultaneously erase or write a plurality of memory transistors. For example, erasing or writing can be performed simultaneously in units of one memory cell (having two memory transistors), one vertical column, one horizontal row, multiple vertical columns, multiple horizontal rows, all memory cells, and the like. For example, in the case where writing to two memory transistors Tr1 and Tr2 is performed simultaneously in one memory cell (1, 1), the source line S1 and the bit line B1 are set to −10 V, the first word line Wa1 and the second The word line Wb1 may be set to 10V. When erasing is simultaneously performed, the source line S1 and the bit line B1 may be set to 10V, and the first word line Wa1 and the second word line Wb1 may be set to −10V.
[0083]
(Example 2)
In this embodiment, as a nonvolatile memory according to the present invention, an example of a memory cell circuit diagram and a driving method different from those in Embodiment Mode and Embodiment 1 will be described.
[0084]
FIG. 7 is a circuit diagram of a memory cell constituting the nonvolatile memory of the present invention. In FIG. 7, the depression of the floating gate electrode represents an overlap region. For example, in FIG. 7A, the overlap region of the memory transistor Tr1 is provided between the floating gate electrode and the source region, and the overlap region of the memory transistor Tr2 is provided between the floating gate electrode and the drain region. In FIG. 7B, the overlap region of the memory transistor Tr1 is provided between the floating gate electrode and the drain region, and the overlap region of the memory transistor Tr2 is provided between the floating gate electrode and the source region. Similarly, in FIG. 7C, the overlap region of the memory transistor Tr1 and the overlap region of the memory transistor Tr2 are provided between the floating gate electrode and the drain region. Note that the memory cell included in the nonvolatile memory described in Embodiment Mode and Example 1 has the structure illustrated in FIG.
[0085]
In this embodiment, a nonvolatile memory having the memory cell structure shown in FIGS. 7B and 7C and a driving method thereof will be described. Since the difference between the three memory cells shown in FIG. 7 is only the position of the overlap region, the read operation, the write operation of the n-channel nonvolatile memory, and the erase operation of the p-channel nonvolatile memory are the same as in the embodiment and The same operation method as in Embodiment 1 can be used. For the erase operation of the n-channel non-volatile memory and the write operation of the p-channel non-volatile memory, for example, the operating voltage described below can be used according to the position of the overlap region.
[0086]
First, a circuit diagram of the memory cell illustrated in FIG. 7B is described. As an erase operation of the memory transistor Tr2 in the n-channel nonvolatile memory, for example, the source line S is 5V, the bit line B is 0V, the first word line Wa is 13V, and the second word line Wb is −15V. Good. As a result, a tunnel current flows in the overlap region of the memory transistor Tr2, and electrons accumulated in the floating gate electrode are emitted to the source region. When erasing the memory transistor Tr1, the source line S may be 0V, the bit line B may be 5V, the first word line Wa may be -15V, and the second word line Wb may be 13V.
[0087]
At this time, a non-selected memory cell in the same column as the selected memory cell needs to be in a non-conductive state because a potential difference is generated between the source line and the bit line. When the operation voltage described above is used, the threshold voltage of the memory transistor Tr1 or Tr2 needs to be 0 V or higher. In order to suppress the conduction of the non-selected memory cell, the memory transistor Tr2 is written. For example, the source line S is 7V, the bit line B is 2V, the first word line Wa is 15V, and the second word line Wb may be set to -13V. In this case, if the threshold voltage of the memory transistor Tr1 or Tr2 is −2 V or higher, the non-selected memory cell will not be conducted. Note that conduction of unselected memory cells can also be suppressed by a method such as providing a verify circuit as a peripheral circuit or a memory element having a split gate structure.
[0088]
As a write operation of the memory transistor Tr2 in the p-channel nonvolatile memory, for example, the source line S is −5V, the bit line B is 0V, the first word line Wa is −10V, and the second word line Wb is 15V. It is good to do. As a result, a tunnel current flows in the overlap region of the memory transistor Tr2, and electrons are injected from the source region to the floating gate electrode. When writing to the memory transistor Tr1, the source line S may be set to 0V, the bit line B may be set to -5V, the first word line Wa may be set to 15V, and the second word line Wb may be set to -10V.
[0089]
Note that a non-selected memory cell in the same column as the selected memory cell has a potential difference between the source line and the bit line, and thus needs to be in a non-conductive state. The threshold voltage of the memory transistor Tr1 or Tr2 needs to be 0V or less. In order to suppress the conduction of the non-selected memory cell, the memory transistor Tr2 is written. For example, the source line S is −10V, the bit line B is −5V, the first word line Wa is −15V, The word line Wb may be set to 10V. In this case, if the threshold voltage of the memory transistor Tr1 or Tr2 is 5 V or less, the non-selected memory cell will not be conducted. Note that conduction of unselected memory cells can also be suppressed by a method such as providing a verify circuit as a peripheral circuit or a memory element having a split gate structure.
[0090]
Next, a circuit diagram of the memory cell in FIG. In the circuit diagram of the memory cell in FIG. 7C, an overlap region is provided between the floating gate electrode and the drain region in both the memory transistors Tr1 and Tr2.
[0091]
The writing and erasing operations of the nonvolatile memory having the circuit diagram of the memory cell in FIG. 7C are the operation method of the memory transistor Tr2 in the memory cell in FIG. 7A and the memory in the memory cell in FIG. The operation method of the transistor Tr1 may be combined. That is, in the n-channel nonvolatile memory, when erasing the memory transistor Tr1, as in FIG. 7B, the source line S is 0V, the bit line B is 5V, and the first word line Wa is -15V. When the second word line Wb is set to 13V and the memory transistor Tr2 is erased, the source line S and the bit line B are set to 10V, and the first word line Wa is set to 0V, as in FIG. The second word line Wb is preferably set to −10V. In the p-channel nonvolatile memory, when writing to the memory transistor Tr1, the source line S is 0V, the bit line B is -5V, and the first word line Wa is 15V, as in FIG. 7B. When the second word line Wb is set to −10V and the memory transistor Tr2 is written, the source line S and the bit line B are set to −10V and the first word line Wa is written as in FIG. May be set to 0V, and the second word line Wb may be set to 10V.
[0092]
With the circuit configuration of the memory cell as shown in FIG. 7C, variation in the size of the overlap region due to misalignment can be suppressed. In the circuit configuration of the memory cell in FIGS. 7A and 7B, when an alignment shift occurs in the manufacturing process of the overlap region, the overlap region of the memory transistor Tr1 and the overlap region of the memory transistor Tr2 have different sizes. Become. As a result, there arises a problem that the writing speed and the erasing speed vary. Such a problem does not occur in the circuit configuration of the memory cell as shown in FIG.
[0093]
Although not shown, the memory cells shown in FIGS. 7A and 7B are the memory cells in which the overlap region is provided between the floating gate electrode and the source region in both the memory transistors Tr1 and Tr2. Writing and erasing operations can be performed by combining the above operating methods.
[0094]
Further, the overlap region may be provided on both sides of the source region side and the drain region side. In this case, the operation methods in FIGS. 7A and 7B can be freely combined. By providing the overlap regions on both sides, the tunnel current flowing in one overlap region can be reduced, and deterioration of the memory transistor due to the tunnel current can be suppressed.
[0095]
Further, the overlap region need not be provided. In this case, a higher voltage write operation and erase operation are required as compared with the case where a tunnel current is passed through the overlap region.
[0096]
Of course, the value of the operating voltage described above is an example, and is not limited to that value. The value of the operating voltage may be any value within a range that does not cause malfunction in the non-selected memory cell while maintaining the potential difference necessary for performing the write, read and erase operations in the selected memory cell. It does not matter.
[0097]
(Example 3)
In this embodiment, a top structure of a memory cell constituting the nonvolatile memory of the present invention will be described. FIG. 2 is an example of a top view of four memory cells. For example, it can be considered that a part of the memory cell array constituting the nonvolatile memory described in the embodiment and Examples 1 and 2 is illustrated.
[0098]
The description will be made only for the upper left memory cell. First, the region 201 is a semiconductor active region. The semiconductor active region refers to a semiconductor active region formed on a silicon substrate and a semiconductor active layer formed on a substrate having an insulating surface or an SOI substrate. Regions 204 and 205 are floating gate electrodes, and wirings 206 and 207 are a source line and a bit line, respectively. In the drawing, the blacked-out portion indicates that the lower wiring or the semiconductor layer is in contact. The first word line 202 and the second word line 203 are wired so as to cover the floating gate electrodes 204 and 205, respectively, and also serve as control gate electrodes.
[0099]
In FIG. 2, the source line 206 and the bit line 207 are provided so as not to overlap with the semiconductor active region, but the source line 206 and the bit line 207 may overlap with the semiconductor active region. By doing so, the distance between the source line and the bit line can be further reduced, and the memory cell area can be reduced.
[0100]
Of course, the upper surface structure of the memory cell constituting the nonvolatile memory of the present invention is not limited to FIG. Any other top view may be used as long as it is a circuit diagram shown in the embodiment and Examples 1 and 2.
[0101]
Note that the cross-sectional structure shown in the embodiment (FIG. 3) can be considered as the cross-sectional structure related to the line segment AB in the top view of the memory cell shown in FIG. 2, for example.
[0102]
【Example】
Example 4
In this example, a method for manufacturing a nonvolatile memory of the present invention over a substrate having an insulating surface will be described with reference to FIGS. As TFTs constituting a non-volatile memory, two memory TFTs (n-channel TFTs) constituting a memory cell, and two TFTs constituting a typical CMOS circuit as a memory cell driving circuit and other peripheral circuits (p A channel type TFT and an n channel type TFT) will be described as an example.
[0103]
According to the manufacturing method described below, it is understood that the nonvolatile memory of the present invention can be integrally formed with any part of a semiconductor device that can be manufactured using thin film technology.
[0104]
In addition, the nonvolatile memory and the semiconductor device including the nonvolatile memory of the present invention are preferably constituted by a TFT having a semiconductor active layer having excellent crystallinity, and a TFT having an amorphous semiconductor active film Is often insufficient. This is because a good gate insulating film is required from the viewpoint of the reliability of the nonvolatile memory, the good gate insulating film is formed on a semiconductor active layer having excellent crystallinity, and peripheral circuits and others. This is because the TFTs constituting these semiconductor parts are required to have good characteristics in mobility, threshold voltage and the like. The TFT obtained by the manufacturing method of this example has a semiconductor active layer with excellent crystallinity and has sufficient performance to constitute the nonvolatile memory and the semiconductor device of the present invention.
[0105]
First, a quartz substrate 801 is prepared as a substrate having an insulating surface (FIG. 8A). Instead of the quartz substrate, a quartz substrate formed with a silicon nitride film as an insulating film, a silicon substrate formed with a thermal oxide film, a ceramic substrate, or the like may be used.
[0106]
Next, an amorphous silicon film 802 having a thickness of 55 nm is formed by a known film formation method (FIG. 8A). Note that it is not necessary to limit the amorphous silicon film, and any amorphous semiconductor film (including a microcrystalline semiconductor film and a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film) may be used. .
[0107]
Next, a crystallization process of the amorphous silicon film 802 is performed. JP-A-10-247735 filed by the present applicant can be referred to for the process from here to FIG. 8C. This publication discloses a technique related to a method for crystallizing a semiconductor film using an element such as Ni as a catalyst.
[0108]
First, protective films 811 to 813 having openings 815 and 816 (a silicon oxide film having a thickness of 150 nm in this embodiment) are formed. Then, a layer (referred to as a Ni-containing layer) 814 containing nickel (Ni) is formed on the protective films 811 to 813 by spin coating. Note that an ion implantation method using a resist mask, a plasma doping method, or a sputtering method may be used.
[0109]
In addition to nickel as catalyst elements, cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb) Indium (In) or the like can be used.
[0110]
Next, as shown in FIG. 8C, a heat treatment is performed at 570 ° C. for 14 hours in an inert atmosphere to crystallize the amorphous silicon film 802. At this time, the crystallization proceeds approximately in parallel with the substrate starting from regions where Ni is in contact (referred to as Ni-added regions) 821 and 822. The crystalline silicon film 823 formed in this manner has an advantage of excellent overall crystallinity because individual crystals are gathered in a relatively uniform state. Note that the heat treatment temperature is preferably 500 to 700 ° C. (typically 550 to 650 ° C.), and the treatment time is preferably 4 to 24 hours.
[0111]
Next, as shown in FIG. 8D, an element belonging to Group 15 (preferably phosphorus) is added to the Ni-added regions 821 and 822 using the protective films 811 to 813 as masks. Thus, regions (referred to as phosphorus-added regions) 831 and 832 to which phosphorus is added at a high concentration are formed.
[0112]
Then, as shown in FIG. 8D, heat treatment is performed at 600 ° C. for 12 hours in an inert atmosphere. This heat treatment is a gettering step of a metal element (Ni in this embodiment) by phosphorus. Finally, almost all Ni is trapped in the phosphorus-added regions 831 and 832 as indicated by arrows. The concentration of Ni remaining in the crystalline silicon film 833 by this step is at least 2 × 10 as measured by SIMS (mass secondary ion analysis). ¹⁷ atoms / cm ^Three Reduced to
[0113]
Thus, a crystalline silicon film 833 that is crystallized using a catalyst and reduced to a level at which the catalyst does not hinder the operation of the TFT is obtained. Thereafter, the protective films 811 to 813 are removed, and island-like semiconductor layers (hereinafter referred to as semiconductor active layers) 901 to 903 using only the crystalline silicon film 833 that do not include the phosphorus-added regions 831 and 832 are formed by a patterning process. (FIG. 9A).
[0114]
Next, as shown in FIG. 9B, a region of the semiconductor active layer 901 excluding a region that later becomes an overlap region of the memory TFT and a part of a region that becomes a source / drain region is a resist mask. An impurity element which is covered with 911 to 913 and imparts n-type conductivity (also referred to as an n-type impurity element) is added (FIG. 9B). In the n-type impurity regions 914 and 915 formed by this process, an n-type impurity element is 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ) Adjust the dose so that it is included at the concentration of As the n-type impurity element, phosphorus (P) or arsenic (As) may be used, and phosphorus (P) is used in this embodiment.
[0115]
After that, the resist masks 911 to 913 are removed, and a first gate insulating film 921 made of an insulating film containing silicon is formed (FIG. 9C). The thickness of the first gate insulating film 921 may be adjusted within a range of 10 to 250 nm in consideration of an increase due to a later thermal oxidation process. Note that the thickness of the first gate insulating film forming the memory TFT may be 10 to 50 nm, and the thickness of the first gate insulating film forming other elements may be 50 to 250 nm. As a film formation method, a known vapor phase method (plasma CVD method, sputtering method, or the like) may be used. In this embodiment, a silicon nitride oxide film having a thickness of 40 nm is formed by a plasma CVD method.
[0116]
Next, heat treatment is performed in an oxidizing atmosphere at 950 ° C. for 1 hour to perform a thermal oxidation process. In this thermal oxidation process, oxidation proceeds at the interface between the active layer and the silicon nitride oxide film, and the film thickness of the semiconductor active layer is finally 40 nm. Note that the oxidizing atmosphere may be an oxygen atmosphere or an oxygen atmosphere to which a halogen element is added. When the thermal oxide film is formed in this way, a semiconductor / insulating film interface with very few interface states can be obtained. In addition, there is an effect of preventing formation defects (edge thinning) of the thermal oxide film at the end portion of the active layer.
[0117]
Next, a conductive film with a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 922 to 925 (FIG. 9C). At this time, the gate electrodes 922 and 923 (which will become floating gate electrodes later) of the memory TFT are formed so as to partially overlap the n-type impurity regions 914 and 915 with the gate insulating film 921 interposed therebetween. This overlapped area becomes an overlap area of the memory TFT.
[0118]
Note that although the gate electrode may be formed of a single-layer conductive film, it is preferably a stacked film of two layers or three layers as necessary. A known conductive film can be used as the material of the gate electrode. Specifically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a nitride of the element. A film (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film (typically a Mo—W alloy or a Mo—Ta alloy), or a silicide film of the element. (Typically, a tungsten silicide film or a titanium silicide film) can be used.
[0119]
In this embodiment, a stacked film including a tungsten nitride (WN) film having a thickness of 50 nm and a tungsten (W) film having a thickness of 350 nm is formed by a sputtering method. Note that when an inert gas such as xenon (Xe) or neon (Ne) is added as a sputtering gas, film peeling due to stress can be prevented.
[0120]
Next, an impurity element adding step for imparting one conductivity is performed. As the impurity element, phosphorus (P) or arsenic (As) may be used for n-type, and boron (B), gallium (Ga), indium (In), or the like may be used for p-type.
[0121]
First, as shown in FIG. 9D, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 922 to 925 as masks, and a low-concentration impurity region (n− region) 931-1 is added. 935 is formed. This low concentration impurity region has a phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ^Three ~ 1x10 ¹⁹ atoms / cm ^Three Adjust so that
[0122]
Next, as shown in FIG. 10A, resist masks 1005 and 1006 are formed so as to cover the entire p-channel TFT and a part of the n-channel TFT, and an n-type impurity element (in this embodiment, Impurity regions 1007 to 1011 containing phosphorus at a high concentration are formed by adding phosphorus. At this time, the concentration of the n-type impurity element is 1 × 10. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ).
[0123]
By this step, source / drain regions 1007 and 1009 of the memory TFT, source / drain regions 1010 and 1011 of the n-channel TFT constituting the CMOS, and an LDD region 1012 are formed.
[0124]
Next, as shown in FIG. 10B, the resist masks 1005 and 1006 are removed, and new resist masks 1013 and 1014 are formed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 1015 and 1016 containing boron at a high concentration. Here, diborane (B ₂ H ₆ 1 × 10 by ion doping method using ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three Boron is added so that the concentration of In this way, source / drain regions 1015 and 1016 of the p-channel TFT are formed (FIG. 10B).
[0125]
Next, after removing the resist masks 1013 and 1014 and etching the gate insulating film 921 by a dry etching method using the gate electrodes 922 to 924 as masks, an insulating film 1021 containing silicon is formed (FIG. 10C). The insulating film 1021 becomes a second gate insulating film between the floating gate electrode and the control gate electrode in the memory TFT. The thickness of the insulating film 1021 may be 10 to 250 nm. As a film formation method, a known vapor phase method (plasma CVD method, sputtering method, or the like) may be used. In this embodiment, a silicon nitride oxide film having a thickness of 70 nm is formed by a plasma CVD method.
[0126]
Thereafter, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, lamp annealing, or a combination thereof may be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours. At this time, damage to the active layer received in the addition process is also repaired.
[0127]
Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form control gate electrodes 1022 and 1023 (FIG. 10C). The control gate electrodes 1022 and 1023 are formed so as to overlap a part or the whole of the floating gate electrode with the insulating film 1021 interposed therebetween.
[0128]
Note that the control gate electrodes 1022 and 1023 may be formed of a single-layer conductive film, but it is preferable that the control gate electrodes 1022 and 1023 be a stacked film of two layers or three layers as necessary. A known conductive film can be used as the material of the gate electrode. In this embodiment, a laminated film including a tungsten nitride (WN) film having a thickness of 50 nm and a tungsten (W) film having a thickness of 350 nm is formed by a sputtering method. When an inert gas such as xenon (Xe) or neon (Ne) is added as a sputtering gas, film peeling due to stress can be prevented.
[0129]
Next, an interlayer insulating film 1031 is formed (FIG. 10D). As the interlayer insulating film 1031, an insulating film containing silicon, an organic resin film, or a stacked film including a combination thereof may be used. The film thickness may be 400 nm to 1500 nm. In this embodiment, a silicon nitride oxide film having a thickness of 500 nm is used.
[0130]
Next, as shown in FIG. 10D, contact holes are formed in the interlayer insulating film 1031 and the insulating film 1021, and source / drain wirings 1032 to 1036 are formed. In this embodiment, the Ti film is a laminated film having a three-layer structure in which the Ti film is 100 nm, the aluminum film containing Ti is 300 nm, and the Ti film 150 nm is continuously formed by sputtering. Of course, other known conductive films may be used.
[0131]
Finally, hydrogenation is performed by heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. In this embodiment, hydrogenation is performed by performing heat treatment for 2 hours in a hydrogen atmosphere at 350 ° C. Further, plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation.
[0132]
Through the above steps, a TFT having a cross-sectional structure as shown in FIG. 10D can be manufactured. In addition, this embodiment can be combined with any of the configurations of Embodiments 1 to 3 by changing the position where the overlap region is formed as necessary.
[0133]
(Example 5)
The non-volatile memory of the present invention can provide a multifunctional, high-functional and small-sized semiconductor device by being integrally formed with a component of a semiconductor device including a TFT formed over a substrate having an insulating surface. it can. In this embodiment, as such an example, an electro-optical device (typically, a liquid crystal display device and an EL) including the nonvolatile memory of the present invention, a pixel portion, a driving circuit for the pixel portion, and a γ (gamma) correction circuit. Display device).
[0134]
The γ correction circuit is a circuit for performing γ correction. The γ correction is a correction for creating a linear relationship between the voltage applied to the pixel electrode and the transmitted light intensity of the liquid crystal or EL layer thereon by applying an appropriate voltage to the image signal.
[0135]
FIG. 11 is a block diagram of the electro-optical device. The nonvolatile memory 1102 of the present invention, the pixel portion 1105, the gate signal side drive circuit 1103 and the source signal side drive circuit 1104 which are drive circuits for the pixel portion, and a γ (gamma) correction circuit 1101. In addition, an image signal, a clock signal, a synchronization signal, or the like is sent via an FPC (flexible printed circuit) 1106.
[0136]
In addition, the electro-optical device according to the present embodiment can be integrally formed on a substrate having an insulating surface by the manufacturing method according to Embodiment 4, for example. Note that a known method may be used for the steps after the TFT formation including the formation of the liquid crystal or the EL layer.
[0137]
In addition, a known circuit structure may be used for the pixel portion 1105, the driver circuits 1103 and 1104 for the pixel portion, and the γ (gamma) correction circuit 1101.
[0138]
In the electro-optical device of this embodiment, the nonvolatile memory 1102 stores (stores) correction data for applying γ correction to an image signal transmitted from a personal computer main body, a television receiving antenna, or the like. The γ correction circuit 1101 performs γ correction on the image signal with reference to the correction data.
[0139]
Data for γ correction may be stored once before the electro-optical device is shipped, but the correction data can be rewritten periodically. In addition, even an electro-optical device manufactured in the same manner may have slightly different optical response characteristics (such as the relationship between the transmitted light intensity and the applied voltage). Also in this case, in this embodiment, different γ correction data can be stored for each electro-optical device, so that the same image quality can always be obtained.
[0140]
Furthermore, by storing a plurality of correction data in the nonvolatile memory and adding a new control circuit, it is possible to freely select a plurality of color tones based on the correction data.
[0141]
When storing correction data for γ correction in the nonvolatile memory 1102, it is preferable to use the means described in Japanese Patent Application No. 11-143379 by the present applicant. Further, the application regarding the γ correction is also made in the same application. Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.
[0142]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-4.
[0143]
(Example 6)
An example of a semiconductor device including the nonvolatile memory of the present invention, which is different from the semiconductor device shown in Embodiment 5, will be described with reference to FIG.
[0144]
FIG. 12 is a block diagram of the electro-optical device (typically, a liquid crystal display device and an EL display device) of this embodiment. The electro-optical device of this embodiment includes a nonvolatile memory 1203, an SRAM 1202, a pixel portion 1206, a gate signal side driving circuit 1204 and a source signal side driving circuit 1205, which are driving circuits for the pixel portion, and a memory. A controller circuit 1201 is provided. Further, an image signal, a clock signal, a synchronization signal, or the like is sent via an FPC (flexible printed circuit) 1207.
[0145]
The memory controller circuit 1201 in this embodiment is a control circuit for controlling operations such as storing and reading image data in the SRAM 1202 and the nonvolatile memory 1203.
[0146]
The SRAM 1202 is provided for writing data at high speed. A DRAM may be provided instead of the SRAM, and the SRAM may not be provided as long as it is a non-volatile memory capable of high-speed writing.
[0147]
The electro-optical device of the present embodiment can be integrally formed on a substrate having an insulating surface by the manufacturing method of Embodiment 4, for example. In addition, what is necessary is just to produce using the well-known method about the process after TFT formation including formation of a liquid crystal or EL layer. The SRAM 1202, the pixel portion 1206, the gate signal side driver circuit 1204, the source signal side driver circuit 1205, and the memory controller circuit 1201 may have a known circuit structure.
[0148]
In the electro-optical device of this embodiment, an image signal sent from a personal computer main body, a television receiving antenna, or the like is stored (stored) in the SRAM 1202 for each frame, and the image signal is sequentially applied to the pixel unit 1206 by the memory controller circuit 1201. Is input and displayed. The SRAM 1202 stores image information for at least one frame displayed on the pixel portion 1206. For example, when a 6-bit digital signal is sent as an image signal, a memory capacity corresponding to at least the number of pixels × 6 bits is required. Further, the memory controller circuit 1201 stores the image signal stored in the SRAM 1202 in the nonvolatile memory 1203 or inputs the image signal stored in the nonvolatile memory 1203 to the pixel unit 1206 for display as necessary. can do.
[0149]
Note that since the image data stored in the SRAM 1202 and the nonvolatile memory 1203 is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.
[0150]
In the configuration of this embodiment, the image displayed on the pixel portion 1206 is always stored in the SRAM 1202, and the image can be easily paused. Further, by storing the image signal stored in the SRAM 1202 in the nonvolatile memory 1203 or inputting the image signal stored in the nonvolatile memory 1203 to the pixel portion, operations such as image recording and reproduction can be easily performed. it can. The television broadcast can be freely paused, recorded and played back without being recorded on a video deck or the like.
[0151]
The amount of information of images that can be recorded and reproduced depends on the storage capacity of the SRAM 1202 and the nonvolatile memory 1203. By storing an image signal for at least one frame, a still image can be recorded and reproduced. Furthermore, if the memory capacity of the non-volatile memory 1203 can be increased to such an extent that image information such as several hundred frames or thousands of frames can be stored, it is possible to reproduce (replay) images several seconds or minutes ago. .
[0152]
In addition, the structure of a present Example can be implemented in combination with any structure of Examples 1-5 freely.
[0153]
(Example 7)
The non-volatile memory of the present invention can provide a multi-function, high-function and small-sized electro-optical device as shown in the fifth and sixth embodiments by being integrally formed with the components of the semiconductor device composed of TFTs. It becomes. Examples of the semiconductor device which is integrally formed with the nonvolatile memory of the present invention include an active matrix type or passive matrix type liquid crystal display device, an active matrix type or passive matrix type EL display device, and the like. In this embodiment, an active matrix liquid crystal display device will be described.
[0154]
FIG. 13A is a circuit diagram of an active matrix liquid crystal display device. In FIG. 13A, an active matrix liquid crystal display device includes a pixel portion 1301 in which pixels 1304 are arranged in a matrix, a source signal side driver circuit 1302, and a gate signal side driver circuit 1303.
[0155]
An enlarged view of the pixel 1304 included in the pixel portion 1301 is shown in FIG. The pixel 1304 includes a switching TFT 1311, a liquid crystal element 1314, and a capacitor 1315. The gate electrode of the switching TFT 1311 is connected to the gate signal line 1312 and either the source electrode or the drain electrode is connected to the source signal line 1313. . The other one of the source electrode and the drain electrode of the switching TFT 1311 is connected to the liquid crystal 1314 and the capacitor 1315. A predetermined potential is applied to the remaining electrode of the liquid crystal element 1314 and the capacitor 1315.
[0156]
Note that one of the electrodes of the capacitor 1315 may be connected not to the wiring 1316 but to a dedicated power supply line. Further, the capacitor 1315 is not necessarily provided. The switching TFT 1311 may be an n-channel TFT or a p-channel TFT.
[0157]
When the nonvolatile memory of the present invention is formed integrally with the active matrix liquid crystal display device of this embodiment, any of the configurations of Embodiments 1 to 6 may be combined.
[0158]
(Example 8)
In this embodiment, an active matrix EL display device will be described as an example of a semiconductor device which is integrally formed with the nonvolatile memory of the present invention.
[0159]
FIG. 14A is a circuit diagram of an active matrix EL display device. 14A, the active matrix EL display device includes a pixel portion 1401 in which pixels 1404 are arranged in a matrix, a source signal driver circuit 1402, and a gate signal driver circuit 1403.
[0160]
An enlarged view of the pixel 1404 included in the pixel portion 1401 is shown in FIG. The pixel 1404 includes a switching TFT 1411, an EL driving TFT 1414, and an EL element 1416. The gate electrode of the switching TFT 1411 is connected to the gate signal line 1412, and either the source electrode or the drain electrode is connected to the source signal line 1413. ing. The other one of the source electrode and the drain electrode of the switching TFT 1411 is connected to the gate electrode of the EL driving TFT 1414. In addition, a source electrode of the EL driving TFT 1414 is connected to the power supply line 1415 and a drain electrode is connected to the EL element 1416. A predetermined potential is applied to the other electrode of the EL element 1416.
[0161]
Note that a capacitor may be provided between the gate electrode of the EL driving TFT 1414 and the power supply line 1415. An n-channel TFT is used as the EL driving TFT. The switching TFT 1411 may be an n-channel TFT or a p-channel TFT.
[0162]
When the nonvolatile memory according to the present invention is integrally formed in the active matrix EL display device of this embodiment, any configuration of Embodiments 1 to 6 may be combined.
[0163]
Example 9
The nonvolatile memory of the present invention has various uses. In this embodiment, an electronic device using the nonvolatile memory of the present invention will be described.
[0164]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays, goggles type displays, game consoles, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or Electronic books, etc.). Examples of these are shown in FIGS.
[0165]
FIG. 15A illustrates a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like. The nonvolatile memory of the present invention may be integrally formed with the display portion 2003 and other signal control circuits.
[0166]
FIG. 15B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The nonvolatile memory of the present invention may be integrally formed with the display portion 2102 and other signal control circuits.
[0167]
FIG. 15C shows a part (right side) of the head mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, a display portion 2204, an optical system 2205, a display device 2206, and the like. The nonvolatile memory of the present invention may be integrally formed with the display device 2206 and other signal control circuits.
[0168]
FIG. 15D shows an image reproduction device (specifically, a DVD reproduction device) provided with a recording medium, which includes a main body 2301, a recording medium 2302, operation switches 2303, display portions 2304 and 2305, and the like. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The nonvolatile memory of the present invention may be integrally formed with the display portion 2304 and other signal control circuits.
[0169]
FIG. 15E illustrates a goggle type display, which includes a main body 2401, a display portion 2402, and an arm portion 2403. The nonvolatile memory of the present invention may be integrally formed with the display portion 2402 and other signal control circuits.
[0170]
FIG. 15F illustrates a personal computer which includes a main body 2501, a housing 2502, a display portion 2503, a keyboard 2504, and the like. The nonvolatile memory of the present invention may be integrally formed with the display portion 2503 and other signal control circuits.
[0171]
FIG. 16A illustrates a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, an antenna 2606, and the like. The nonvolatile memory of the present invention may be integrally formed with the display portion 2604 and other signal control circuits.
[0172]
FIG. 16B shows a sound reproducing device, specifically a car audio, which includes a main body 2701, a display portion 2702, operation switches 2703, 2704, and the like. The nonvolatile memory of the present invention may be integrally formed with the display portion 2702 and other signal control circuits. Moreover, although the vehicle-mounted audio is shown in the present embodiment, it may be used for a portable or household sound reproducing device.
[0173]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0174]
【The invention's effect】
The nonvolatile memory according to the present invention has the same memory while maintaining the same function as a conventional full-function EEPROM in which the memory cell is configured by one memory transistor and one selection transistor by configuring the memory cell by two memory transistors. It is possible to realize twice the memory capacity in terms of cell area.
[0175]
As a result, it is possible to provide a full-function EEPROM that has a high integration density and is therefore small and low-cost.
[0176]
In addition, by forming the nonvolatile memory of the present invention integrally with another semiconductor component composed of TFTs on a substrate having an insulating surface, it is possible to provide a highly functional or multi-functional and small semiconductor device. .
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a nonvolatile memory according to the present invention.
FIG. 2 is a top view of a memory cell constituting the nonvolatile memory of the present invention.
FIG. 3 is a cross-sectional view of a memory cell constituting the nonvolatile memory of the present invention.
FIG. 4 is a diagram showing a circuit configuration of a conventional nonvolatile memory.
FIG. 5 is a cross-sectional view of a memory cell constituting a conventional nonvolatile memory.
FIG. 6 is a diagram showing a circuit configuration of a nonvolatile memory according to the present invention.
FIG. 7 is a circuit diagram of a memory cell constituting the nonvolatile memory of the present invention.
FIG. 8 is a diagram showing a manufacturing process of a nonvolatile memory according to the present invention.
FIG. 9 is a diagram showing a manufacturing process of the nonvolatile memory of the present invention.
10 is a diagram showing a manufacturing process of a nonvolatile memory according to the present invention; FIG.
FIG. 11 is a block diagram of an electro-optical device using a nonvolatile memory according to the present invention.
FIG. 12 is a block diagram of an electro-optical device using the nonvolatile memory of the present invention.
FIG. 13 illustrates a structure of an active matrix liquid crystal display device.
FIG 14 illustrates a structure of an active matrix EL display device.
FIG. 15 shows an electronic device using the nonvolatile memory of the present invention.
FIG. 16 shows an electronic device using the nonvolatile memory of the present invention.
[Explanation of symbols]
101 X address decoder
102 Y address decoder
103, 104 peripheral circuit
105 Memory cell array
201 Semiconductor active layer
202 first word line
203 second word line
204, 205 Floating gate electrode
206 Source line
207 bit line

Claims (5)

A plurality of memory cells including a first memory transistor and a second memory transistor;
A first control gate of the first memory transistor is electrically connected to a first wiring;
A second control gate of the second memory transistor is electrically connected to a second wiring;
One of a source and a drain of the first memory transistor is electrically connected to a third wiring;
The other of the source and drain of the first memory transistor is electrically connected to one of the source and drain of the second memory transistor;
The other of the source and the drain of the second memory transistor is electrically connected to a fourth wiring;
The first memory transistor has a first overlap region for flowing a first tunnel current in an erasing operation at a position where the first floating gate and the other of the source or drain of the first memory transistor overlap. Have
The second memory transistor has a second overlap region for flowing a second tunnel current in an erasing operation at a position where the second floating gate and the other of the source or drain of the second memory transistor overlap. A non-volatile memory comprising: In claim 1,
The first memory transistor and the second memory transistor are each formed by using an SOI substrate. In claim 1 or claim 2,
The nonvolatile memory, wherein each of the first memory transistor and the second memory transistor stores data of 2 bits or more. In any one of Claims 1 thru | or 3,
The nonvolatile memory, wherein each of the first memory transistor and the second memory transistor has two or more threshold voltages. In any one of Claims 1 thru | or 4,
A drive circuit for driving the memory cell;
The nonvolatile memory, wherein the memory cell and the driving circuit are integrally formed.

Images