JP4223214B2 - Semiconductor device, image display device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a sense amplifier used in a semiconductor device including a thin film transistor.
[0002]
[Prior art]
In a semiconductor memory device, a sense amplifier is used in the process of reading stored data. The configuration and operation of an example of a conventional sense amplifier will be described with reference to FIG. In FIG. 27, the gates of NMOS transistors MN1 and MN2 are connected to the first input terminal IN1 and the second input terminal IN2 corresponding to the paired bit lines, respectively. The sources of the PMOS load transistors MP1 and MP2 are both connected to the power supply VDD, the gates are common, and are further connected to the drain of MP1. The drain of MP1 is connected to the drain of MN1, and the drain of MP2 is connected to the drain of MN2 and the output terminal OUT. The sources of MN1 and MN2 are common, and are connected to the drain of an NMOS transistor MN3 that functions as a direct current source. The gate of MN3 is connected to the bias power supply V # BIAS, and the source is connected to the power supply GND. The sense amplifier shown in FIG. 27 constitutes a current mirror type differential amplifier.
[0003]
In the semiconductor memory device, when the stored data is read, a high and low potential difference is generated between the paired bit lines depending on whether the data is “Hi” or “Lo”. The sense amplifier shown in FIG. 27 detects a slight potential difference between the bit line signals sent to the first input terminal IN1 and the second input terminal IN2, and amplifies and outputs the result. That is, when the potential of IN2 is higher than the potential of IN1, the output terminal OUT outputs “Lo”, and conversely, when the potential of IN2 is smaller than the potential of IN1, the output terminal OUT outputs “Hi”. Thus, the sense amplifier is used for reading data stored in the semiconductor memory device.
[0004]
[Problems to be solved by the invention]
In recent years, an image display device in which a semiconductor thin film is formed on a glass substrate, in particular, an active matrix image display device using a thin film transistor (hereinafter referred to as TFT) has become widespread. An active matrix image display device using TFTs (hereinafter referred to as an image display device) has hundreds of thousands to millions of TFTs arranged in a matrix and controls the charge of each pixel. Furthermore, as a recent technology, TFT technology that realizes so-called system-on-glass, in which not only the pixel TFT that constitutes the pixel but also the drive circuit, further memory circuit, control circuit, and CPU are simultaneously formed using the TFT (polypoly). Silicon TFT technology and the like are being developed.
[0005]
However, the current TFT technology has a problem that the characteristic variation of transistors is larger than that of a transistor technology formed on a single crystal Si substrate. This indicates that it is difficult to use the conventional circuit shown in FIG. 27 with the current TFT technology. For example, it is assumed that the threshold values of the NMOS transistors MN1 and MN2 are 1.0 [V] and 1.5 [V], respectively, and there is a difference of 0.5V. If the potential of the second input terminal IN2 is 0.2 [V] larger than the potential of the first input terminal IN1, the output OUT should be “Hi” where it should be “Lo”, which causes a malfunction. This is a fatal injury when used in a dynamic random access memory (DRAM) read circuit.
[0006]
Also, if used in a static random access memory (SRAM) readout circuit, the potential difference between the input terminals increases with time and eventually absorbs variations in threshold values of the NMOS transistors MN1 and MN2 and malfunctions. The possibility is reduced. However, it takes time to increase the input potential difference until the variation in threshold value is absorbed, and the disadvantage that the readout time becomes long cannot be wiped out.
[0007]
In view of the above problems, an object of the present invention is to provide a sense amplifier in which the influence of threshold variation is suppressed. It is another object of the present invention to provide a sense amplifier including a TFT having good characteristics.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the sense amplifier of the present invention has the following configuration.
[0009]
The sense amplifier of the present invention for detecting a potential difference between signals input to the first input terminal and the second input terminal has the first and second voltages applied to the gate-source voltages of the first and second transistors. A first means for applying a voltage corresponding to the threshold value of each of the transistors, and signals input to the first and second input terminals to the gates of the first and second transistors, respectively. And a second means for correcting a variation in threshold values of the first and second transistors.
[0010]
The sources of the first and second transistors are common, and are connected to a first power supply via a first switch.
[0011]
The drains of the first and second transistors may be connected to a second power source via second and third switches, respectively.
[0012]
The drain of the first transistor is connected to a second power source via a second switch and a first resistor, and the drain of the second transistor is connected to a third switch and a second resistor. The second power source may be connected via an element.
[0013]
The drain of the first transistor is connected to a second power source via a second switch and a third transistor, and the drain of the second transistor is connected to the third switch and the fourth transistor. The gates of the third and fourth transistors may be connected to the third drain.
[0014]
The first means includes first switching means for controlling conduction / non-conduction between the gates and drains of the first and second transistors, and each of the first and second transistors. And second switching means for controlling the inflow or discharge of charges to the drain and third switching means for controlling the inflow or discharge of charges to the sources of the first and second transistors.
[0015]
Further, the second means is achieved by interposing a capacitive element between the first and second input terminals and the gates of the first and second transistors, respectively.
[0016]
Further, the second means includes a capacitor element and a switch connected in series between the first and second input terminals and the gates of the first and second transistors, respectively. This is achieved by having the fourth and fifth switches for controlling the connection to the third power source at the connection node between the capacitive element and the switch in the set, respectively.
[0017]
The sense amplifier is formed of a thin film transistor, and the semiconductor film forming the semiconductor active layer of the thin film transistor is crystallized by laser annealing using continuous wave laser light.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In order to facilitate comparison with the conventional example, the same reference numerals are used for the transistors and the like corresponding to the respective parts of the conventional example in the following description of the embodiment.
[0019]
[Embodiment 1]
In the present embodiment, the sense amplifier shown in FIG. 1 will be described. First, the configuration of the present embodiment will be described. The present embodiment shown in FIG. 1 is different from the conventional example shown in FIG. 27 in that a switch and a capacitive element are added. In other words, the connection of the drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 is controlled via the first switch SW1, and similarly the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are connected via the second switch SW2. Is controlled. The connection of the drain and gate of the NMOS transistor MN1 is controlled through the third switch SW3, and similarly, the connection of the drain and gate of the NMOS transistor MN2 is controlled through the fourth switch SW4. The first input terminal IN1 and the gate of the NMOS transistor MN1 are node-separated by the fifth switch SW5 and the capacitive element C1, that is, the first input terminal IN1 is connected to the node N1 through the fifth switch SW5, C1 is added between the node N1 and the gate of the NMOS transistor MN1. Similarly, the second input terminal IN2 and the gate of the NMOS transistor MN2 are node-separated by the sixth switch SW6 and the capacitive element C2, that is, the second input terminal IN2 is connected to the node N2 via the sixth switch SW6. Then, C2 is added between the node N2 and the gate of the NMOS transistor MN2. Further, the connection of the node N1 with the power supply GND is controlled through the seventh switch SW7, and similarly the connection of the node N2 with the power supply GND is controlled through the eighth switch SW8. A capacitive element C3 is added between the source and gate of the NMOS transistor MN1, and similarly, a capacitive element C4 is added between the source and gate of the NMOS transistor MN2. Finally, the common source of the NMOS transistors MN1 and MN2 is connected to the power supply GND via the ninth switch SW9. The control signals (WE1, WE2, WE3, PR1, PR2) control corresponding switches as summarized in the table in FIG.
[0020]
Next, the operation of the present embodiment will be described with reference to FIG. 2 showing the operation timing and FIG. 3 showing the switch connection state at the main timing. For convenience of explanation, it is assumed below that the corresponding switch is conductive when each control signal is “Hi” and non-conductive when it is “Lo”. Further, only the left half of the circuit of FIG. 1 is extracted and shown in FIG. 3 from the contrast of circuit configuration and circuit operation.
[0021]
First, a period T1 in which the control signals WE2, PR1, and PR2 are “Hi” is provided from the state where all the control signals are “Lo” and all the switches are non-conductive. The state of each switch in the period T1 is as shown in FIG. In a period T1, the gate potential of the NMOS transistor MN1 (MN2) is given a high potential by a voltage corresponding to the threshold value of the PMOS transistor MP1 (MP2) from the power supply VDD.
[0022]
Next, a period T2 in which the control signal WE2 is “Lo” and WE3 is “Hi” is provided. The state of each switch in the period T2 is as shown in FIG. In the period T2, the charge charged in the gate of the NMOS transistor MN1 (MN2) in the period T1 is discharged so that the gate-source voltage of the MN1 (MN2) becomes a voltage corresponding to the threshold value of the MN1 (MN2). To. This period T2 serves to store the respective threshold values in the gate-source voltage in the NMOS transistors MN1 and MN2.
[0023]
Finally, a period T3 in which the control signals WE1, WE2, and WE3 are “Hi” and the control signals PR1 and PR2 are “Lo” is provided. The state of each switch in the period T3 is as shown in FIG. In the period T3, the gate potential of the NMOS transistor MN1 (MN2) plays a role of adding a potential corresponding to the input IN1 (IN2) to the gate potential determined in the period T2. Since the respective threshold values are already written in the gate-source voltages of the NMOS transistors MN1 and MN2 in the period T2, the added potential difference in the period T3 remains as it is as the difference in driving capability between the NMOS transistors MN1 and MN2. Appear in
[0024]
In this way, it is possible to accurately detect the magnitude of the potentials of the input signals IN1, IN2 even if the threshold values of the NMOS transistors MN1 and MN2 are different. In addition, since accurate detection can be performed when the potential difference between the inputs IN1 and IN2 is small, the output can be determined in a short time and high-speed reading can be performed.
[0025]
[Embodiment 2]
In the present embodiment, the sense amplifier shown in FIG. 4 will be described. In this embodiment, as shown in FIG. 4, the fifth switch SW5 to the eighth switch SW8 are removed from the circuit diagram of FIG. 1 which is the first embodiment, and the input terminals IN1, IN2 are directly connected to the capacitive elements C1, C2. It takes the form which is connected to. Therefore, the input signals input from the input terminals IN1 and IN2 are different from those in the first embodiment, as shown in FIG. 5, before the period T3, the input signals are both at the “Lo” level having the same potential (the first embodiment). In the period T3, it is necessary to change from the “Lo” level to a desired potential level. By doing so, it is possible to enjoy functions equivalent to those of the first embodiment while reducing the number of switches.
[0026]
[Embodiment 3]
In the present embodiment, the sense amplifier shown in FIG. 6 will be described. As shown in FIG. 6, the present embodiment is different from the circuit diagram of FIG. 1 of the first embodiment in that the PMOS transistors MP1 and MP2 are replaced with resistance elements R1 and R2, respectively. FIG. 2 can also be applied to the operation timing of this embodiment. Although this embodiment is inferior in operation to the first embodiment, it is superior in comparison with the conventional example in that it does not affect the threshold variation by the threshold correction function.
[0027]
[Embodiment 4]
In the present embodiment, the sense amplifier shown in FIG. 7 will be described. As shown in FIG. 7, the present embodiment is different from the circuit diagram of FIG. 4 of the second embodiment in that the PMOS transistors MP1 and MP2 are replaced with resistance elements R1 and R2, respectively. FIG. 5 can be applied to the operation timing of this embodiment. Although this embodiment is inferior in operation to the first embodiment, it is superior in comparison with the conventional example in that it does not affect the threshold variation by the threshold correction function.
[0028]
[Embodiment 5]
In the present embodiment, the sense amplifier shown in FIG. 8 will be described. In this embodiment, as shown in FIG. 8, in the circuit diagram of FIG. 1 which is Embodiment 1, the PMOS transistors MP1 and MP2 are deleted, and the first switch SW1 and the second switch SW2 are replaced by the PMOS transistors MP1 and MP2. The point that moved to the original position is different. In addition, this embodiment can be said to have the role of the resistance element R1 in the third embodiment as well as the switching function of the first switch SW1. The same applies to the second switch SW2. FIG. 2 can also be applied to the operation timing of this embodiment. Although this embodiment is inferior in operation to the first embodiment, it is superior in comparison with the conventional example in that it does not affect the threshold variation by the threshold correction function.
[0029]
[Embodiment 6]
In the present embodiment, the sense amplifier shown in FIG. 9 will be described. In this embodiment, as shown in FIG. 9, in the circuit diagram of FIG. 4 which is Embodiment 2, the PMOS transistors MP1 and MP2 are deleted, and the first switch SW1 and the second switch SW2 are replaced by the PMOS transistors MP1 and MP2. The point that moved to the original position is different. FIG. 5 can also be applied to the operation timing of this embodiment. Although this embodiment is inferior in operation to the first embodiment, it is superior in comparison with the conventional example in that it does not affect the threshold variation by the threshold correction function.
[0030]
In the above first to sixth embodiments, the description has been made with the transistor conductivity type fixed, but the power supply system may be inverted to invert the transistor conductivity type.
[0031]
【Example】
Now, embodiments of the present invention will be described with reference to the drawings.
[0032]
[Example 1]
This example shown in FIG. 10 is an example in which each switch is specifically configured with an NMOS transistor in the sense amplifier (FIG. 1) of the first embodiment. In this embodiment, an NMOS transistor is used for each switch, but a PMOS transistor or a CMOS transistor may be used. Further, a combination of NMOS, PMOS, and CMOS may be used.
[0033]
This example is an example in which each switch of the sense amplifier (FIG. 1) of the first embodiment is configured by an NMOS transistor, but it goes without saying that each switch of the sense amplifier of the second to sixth embodiments can be configured by an NMOS transistor. Yes. Each switch may be an arbitrary combination of NMOS, PMOS, and CMOS.
[0034]
[Example 2]
This embodiment shown in FIG. 11 shows a part of a semiconductor memory device including memory cells for one column, and is an example in which the sense amplifier described in the first to sixth embodiments is incorporated in a semiconductor memory device. is there. In this embodiment, a precharge circuit, a memory cell array composed of memory cells, a pair of data lines D and / D, a word line W (W_1, W_2,..., W_n), a plurality of control signal lines CSL, and a sense It consists of an amplifier.
[0035]
A data read operation will be briefly described. First, the paired data lines D and / D are set to the same potential by the precharge circuit. Next, one of the word lines has an active potential and a corresponding memory cell is selected. When the memory cell is selected, a potential difference is generated between the paired data lines D and / D depending on the stored data, and this is detected by the sense amplifier to read the data. As described above, the sense amplifiers described in Embodiments 1 to 6 can be used in a semiconductor memory device.
[0036]
[Example 3]
This embodiment shown in FIG. 12 shows a block diagram of a semiconductor memory device including matrix-like memory cells, and another implementation in which the sense amplifier described in the first to sixth embodiments is incorporated in the semiconductor memory device. It is an example. This embodiment is composed of a precharge circuit, a memory cell array composed of memory cells, a pair of data lines, a word line group, a write circuit, and a read circuit. The sense amplifiers described in the first to sixth embodiments constitute a part of the readout circuit.
[0037]
A data read operation will be briefly described. First, the pair of data lines are set to the same potential by the precharge circuit. Next, one of the word lines takes an active potential and a corresponding memory cell row is selected by the row decoder. As a result, a potential difference is generated between each pair of data lines depending on the data stored in each memory cell of the selected memory cell row. Further, one of the paired data lines is selected by the column decoder, and this is detected by the sense amplifier of the read circuit, and the data in the desired memory cell is read by reading the data. As described above, the sense amplifiers described in Embodiments 1 to 6 can be used in a semiconductor memory device. In addition, Example 2 respond | corresponds to what extracted one part of the present Example.
[0038]
[Example 4]
13 is a block diagram of a semiconductor device including a system and a display portion, and is another example in which the sense amplifier described in Embodiments 1 to 6 is incorporated in a semiconductor device.
[0039]
In FIG. 13, a semiconductor device 201 is a device that captures or creates image data, processes the image data, converts the format, and displays an image. As the semiconductor device 201, for example, a game machine, a video camera, a car navigation system, a personal computer, or the like can be considered.
[0040]
The semiconductor device 201 includes an input terminal 211, a first control circuit 212, a second control circuit 213, a CPU 214, a first storage circuit unit 215, a second storage circuit unit 216, a signal line driver circuit 217, and a scanning line. The semiconductor display portion 202 includes a driver circuit 218 and a pixel portion 219. Conventionally, only the semiconductor display unit 202 is formed on a substrate having an insulating surface such as glass, quartz, or plastic. However, in this embodiment, all other circuit blocks are formed on the substrate having the insulating surface. The
[0041]
From the input terminal 211, data serving as a basis of image data is input in accordance with each electronic device. For example, it is input data from an antenna in a broadcast receiver, and input data from a CCD in a video camera. It may be input data from a DV tape or a memory card. Data input from the input terminal 211 is converted into an image signal by the first control circuit 212. The first control circuit 212 performs image signal processing such as decoding processing of image data compression-encoded according to the MPEG standard, tape format, etc., image interpolation and resizing. The image signal output from the first control circuit 212 and the image signal created or processed by the CPU 214 are input to the second control circuit 213 and converted into a format suitable for the semiconductor display unit 202 (for example, a scanning format). Is done. The second control circuit 213 outputs a format-converted image signal and control signal.
[0042]
The CPU 214 efficiently controls signal processing in the first control circuit 212, the second control circuit 213, and other interface circuits. Also, image data is created or processed. The first storage circuit unit 215 stores a memory area for storing image data output from the first control circuit 212 and image data output from the second control circuit 213, and a work memory area for control by the CPU. Used as a work memory area when image data is created by the CPU. As the first memory circuit portion 215, a DRAM or an SRAM is used, and the sense amplifier described in the first to sixth embodiments is used in the first memory circuit portion 215. The second storage circuit unit 216 is a memory area for storing color data and character data necessary for creating or processing image data by the CPU 214, and is configured by a mask ROM or EPROM.
[0043]
The signal line driver circuit 217 receives image signals and control signals (clock signal, start pulse, etc.) from the second control circuit 213, and the scanning line driver circuit 218 receives control signals (clock signal, start pulse, etc.) from the second control circuit 213. ) And display an image in the pixel portion 219.
[0044]
In addition, as a semiconductor display part, a liquid crystal display and an EL display can be considered, for example. Further, as in the case of a high-performance game machine, when the burden on the CPU is too large in the architecture shown in FIG. 13, a configuration may be adopted in which a new processor for image processing is provided to reduce the load on the CPU.
[0045]
As described above, the sense amplifiers described in Embodiments 1 to 6 can be used for a semiconductor device.
[0046]
[Example 5]
In this embodiment, an example of a technique for crystallizing a semiconductor film will be described in manufacturing a semiconductor active layer of a TFT included in a semiconductor device of the present invention.
[0047]
A silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) 400 nm was formed as a base film on a glass substrate by a plasma CVD method. Subsequently, an amorphous silicon film having a thickness of 150 nm was formed as a semiconductor film on the base film by a plasma CVD method. Then, heat treatment was performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film, and then the semiconductor film was crystallized by laser annealing.
[0048]
The laser used in the laser annealing method is a continuous wave YVO. _Four A laser was used. The conditions of the laser annealing method are YVO as laser light. _Four The second harmonic of the laser (wavelength 532 nm) was used. The semiconductor film formed on the substrate surface was irradiated with laser light as a beam having a predetermined shape by an optical system.
[0049]
Note that the shape of the beam irradiated onto the substrate can be changed depending on the type of laser and the optical system. Thus, the aspect ratio and energy density distribution of the beam irradiated on the substrate can be changed. For example, the shape of the beam irradiated onto the substrate can be various shapes such as a linear shape, a rectangular shape, and an elliptical shape. In this embodiment, YVO _Four The second harmonic of the laser was made into an elliptical shape of 200 μm × 50 μm by an optical system, and the semiconductor film was irradiated.
[0050]
Here, FIG. 14 shows a schematic diagram of an optical system used when irradiating a semiconductor film formed on the substrate surface with laser light.
[0051]
Laser light emitted from the laser 101 (YVO _Four The second harmonic of the laser enters the convex lens 103 via the mirror 102. The laser light is incident on the convex lens 103 at an angle. By doing so, the focal position shifts due to aberrations such as astigmatism, and the elliptical beam 106 can be formed at or near the irradiated surface.
[0052]
Then, while irradiating the elliptical beam 106 formed in this way, the glass substrate 105 was moved in a direction indicated by 107 or a direction indicated by 108, for example. In this way, the semiconductor film 104 formed on the glass substrate 105 was irradiated while moving the elliptical beam 106 relatively.
[0053]
The relative scanning direction of the elliptical beam 106 was a direction perpendicular to the major axis of the elliptical beam 106.
[0054]
In this embodiment, an elliptical beam of 200 μm × 50 μm is formed with an incident angle φ of the laser beam with respect to the convex lens 103 being about 20 °, and the glass substrate 105 is irradiated while moving at a speed of 50 cm / s, so that the semiconductor film Crystallization was performed.
[0055]
FIG. 15 shows the result of Secco-etching the thus obtained crystalline semiconductor film and observing the surface with SEM at a magnification of 3000 times. The Seco solution in Seco Etching is HF: H ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ It is produced using. FIG. 15 is obtained by relatively scanning laser light in the direction indicated by the arrow in the figure. It can be seen that large crystal grains are formed parallel to the scanning direction of the laser beam. That is, crystal growth is performed so as to extend in the scanning direction of the laser beam.
[0056]
As described above, large-sized crystal grains are formed in the semiconductor film crystallized using the method of this embodiment. Therefore, when a TFT is manufactured using the semiconductor film as a semiconductor active layer, the number of crystal grain boundaries included in the channel formation region of the TFT can be reduced. In addition, since the inside of each crystal grain has crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor using a single crystal semiconductor can be obtained.
[0057]
Furthermore, if the TFT is arranged so that the carrier moving direction is aligned with the direction in which the formed crystal grains extend, the number of times the carriers cross the crystal grain boundary can be extremely reduced. Therefore, variations in on-current value (drain current value that flows when the TFT is on), off-current value (drain current value that flows when the TFT is off), threshold voltage, S value, and field effect mobility Can be reduced, and the electrical characteristics are remarkably improved.
[0058]
Note that in order to irradiate the elliptical beam 106 over a wide area of the semiconductor film, a plurality of operations (hereinafter referred to as scanning) of irradiating the semiconductor film by scanning the elliptical beam 106 in a direction perpendicular to the major axis are performed. I'm going to go. Here, for each scan, the position of the elliptical beam 106 is shifted in a direction parallel to the major axis. In addition, the scanning direction is reversed between consecutive scans. Here, in two consecutive scans, one is called a forward scan, and the other is called a backward scan.
[0059]
The size of shifting the position of the elliptical beam 106 in the direction parallel to the major axis for each scan is expressed as a pitch d. In the forward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 106 in the region where the crystal grains having a large grain size as shown in FIG. 15 are formed is denoted as D1. In the return scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 106 in the region where the crystal grains having a large grain size as shown in FIG. 15 are formed is denoted as D2. Also, let D be the average value of D1 and D2.
[0060]
At this time, the overlap rate R _OL [%] Is defined by equation (1).
[0061]
R _OL = (1-d / D) × 100 (1)
[0062]
In this embodiment, the overlap rate R _OL Was 0%.
[0063]
[Example 6]
In this embodiment, an example different from that in Embodiment 5 is shown in the method of crystallizing a semiconductor film in manufacturing a semiconductor active layer of a TFT included in the semiconductor device of the present invention.
[0064]
The steps until the amorphous silicon film is formed as the semiconductor film are the same as those in the fifth embodiment. Thereafter, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (concentration in weight of 5 ppm, volume 10 ml) is applied onto the semiconductor film by spin coating, and in a nitrogen atmosphere at 500 ° C. Heat treatment was performed for 12 hours in a nitrogen atmosphere at 550 ° C. for 1 hour. Subsequently, the crystallinity of the semiconductor film was improved by laser annealing.
[0065]
The laser used in the laser annealing method is a continuous wave YVO. _Four A laser was used. The conditions of the laser annealing method are YVO as laser light. _Four Using the second harmonic of the laser (wavelength 532 nm), an elliptical beam of 200 μm × 50 μm was formed with the incident angle φ of the laser beam to the convex lens 103 in the optical system shown in FIG. 14 being about 20 °. While moving the glass substrate 105 at a speed of 50 cm / s, the elliptical beam was irradiated to improve the crystallinity of the semiconductor film.
[0066]
The relative scanning direction of the elliptical beam 106 was a direction perpendicular to the major axis of the elliptical beam 106.
[0067]
The crystalline semiconductor film thus obtained was subjected to seco etching, and the surface was observed with a SEM at a magnification of 3,000. The result is shown in FIG. FIG. 16 is obtained by relatively scanning the laser beam in the direction indicated by the arrow in the figure, and shows that large crystal grains are formed extending in the scanning direction. Recognize.
[0068]
As described above, since a large crystal grain is formed in the semiconductor film crystallized using the present invention, when a TFT is manufactured using the semiconductor film, a crystal included in the channel formation region is formed. The number of grain boundaries can be reduced. Further, since individual crystal grains have crystallinity that can be regarded as a single crystal, high mobility (field effect mobility) equivalent to that of a transistor including a single crystal semiconductor can be obtained.
[0069]
Furthermore, the formed crystal grains are aligned in one direction. Therefore, if the TFT is arranged so that the carrier moving direction is aligned with the extending direction of the formed crystal grains, the number of times the carriers cross the crystal grain boundary can be extremely reduced. Therefore, it is possible to reduce variations in the on-current value, off-current value, threshold voltage, S value, and field effect mobility, and the electrical characteristics are remarkably improved.
[0070]
Note that in order to irradiate the elliptical beam 106 over a wide range of the semiconductor film, the operation (scanning) of irradiating the semiconductor film by scanning the elliptical beam 106 in a direction perpendicular to the major axis is performed a plurality of times. Here, for each scan, the position of the elliptical beam 106 is shifted in a direction parallel to the major axis. In addition, the scanning direction is reversed between consecutive scans. Here, in two consecutive scans, one is called a forward scan, and the other is called a backward scan.
[0071]
The size of shifting the position of the elliptical beam 106 in the direction parallel to the major axis for each scan is expressed as a pitch d. In the forward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 106 in the region where the crystal grains having a large grain size as shown in FIG. 16 are formed is denoted as D1. In the backward scan, the length in the direction perpendicular to the scanning direction of the elliptical beam 106 in the region where the crystal grains having a large grain size as shown in FIG. 16 are formed is denoted as D2. Also, let D be the average value of D1 and D2.
[0072]
At this time, similar to the equation (1), the overlap rate R _OL Define [%]. In this embodiment, the overlap rate R _OL Was 0%.
[0073]
In addition, the results of Raman scattering spectroscopy of the semiconductor film obtained by the above crystallization technique (indicated as Improved CG-Silicon in the figure) are shown by thick lines in FIG. Here, for comparison, the results of Raman scattering spectroscopy of single crystal silicon (shown as ref. (100) Si Wafer in the figure) are shown by thin lines. In addition, after forming an amorphous silicon film, heat treatment is performed to release hydrogen contained in the semiconductor film, followed by crystallization using a pulsed excimer laser (indicated as excimer laser annealing in the figure). The results of Raman scattering spectroscopy of () are shown by dotted lines in FIG.
[0074]
The Raman shift of the semiconductor film obtained by the method of this example is 517.3 cm. ^-1 It has a peak. The half width is 4.96 cm. ^-1 It is. On the other hand, the Raman shift of single crystal silicon is 520.7 cm. ^-1 It has a peak. The half width is 4.44 cm. ^-1 It is. The Raman shift of the semiconductor film crystallized using a pulsed excimer laser is 516.3 cm. ^-1 It is. The half width is 6.16 cm. ^-1 It is.
[0075]
According to the result of FIG. 17, the crystallinity of the semiconductor film obtained by the crystallization method shown in this example is higher than that of the semiconductor film crystallized using a pulsed excimer laser. It can be seen that it is close to silicon.
[0076]
[Example 7]
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method shown in Embodiment 5 will be described with reference to FIGS.
[0077]
In this embodiment, a glass substrate is used as the substrate 20, and a silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) 50 nm and a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) 100 nm were stacked. Next, an amorphous silicon film 150 nm was formed as a semiconductor film 22 on the base film 21 by a plasma CVD method. Then, a heat treatment was performed at 500 ° C. for 3 hours to release hydrogen contained in the semiconductor film. (FIG. 18 (A))
[0078]
After that, continuous wave YVO as laser light _Four Using the second harmonic of the laser (wavelength: 532 nm, 5.5 W), an elliptical beam of 200 μm × 50 μm was formed with the incident angle φ of the laser beam with respect to the convex lens 103 in the optical system shown in FIG. 14 being about 20 °. The elliptical beam was relatively scanned at a speed of 50 cm / s to irradiate the semiconductor film 22 to obtain a crystallized semiconductor film 23. (Fig. 18B)
[0079]
And the 1st doping process was performed and the semiconductor film 24 was obtained. This is channel doping for controlling the threshold value. B as material gas ₂ H ₆ , Gas flow rate 30 sccm, current density 0.05 μA, acceleration voltage 60 keV, dose amount 1 × 10 ¹⁴ / Cm ² Went as. (Figure 18 (C))
[0080]
Subsequently, patterning is performed to etch the semiconductor film 24 into a desired shape, and then a silicon oxynitride film having a thickness of 115 nm is formed by plasma CVD as a gate insulating film 27 covering the etched semiconductor films 25 and 26. . Next, a TaN film 28 with a thickness of 30 nm and a W film 29 with a thickness of 370 nm are stacked on the gate insulating film 27 as conductive films. (Fig. 18D)
[0081]
A mask (not shown) made of resist is formed by photolithography, and the W film, TaN film, and gate insulating film are etched.
[0082]
Then, the resist mask is removed, a new mask 33 is formed, and a second doping process is performed to introduce an impurity element imparting n-type into the semiconductor film. In this case, the conductive layers 30 and 31 serve as a mask for the impurity element imparting n-type, and the impurity region 34 is formed in a self-aligning manner. In this embodiment, the second doping process is performed under two conditions because the thickness of the semiconductor film is as thick as 150 nm. In this embodiment, phosphine (PH _Three ) And a dose amount of 2 × 10 ¹³ / Cm ² And the acceleration voltage is 90 keV, and the dose is 5 × 10 5 ¹⁴ / Cm ² The acceleration voltage was 10 keV. (Figure 18 (E))
[0083]
Next, after removing the resist mask 33, a new resist mask 35 is formed and a third doping process is performed. By the third doping treatment, an impurity region 36 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor film that becomes the active layer of the p-channel TFT. Using the conductive layers 30 and 31 as a mask for the impurity element, an impurity element imparting p-type is added to form the impurity region 36 in a self-aligning manner. In this embodiment, the third doping process is also performed under two conditions because the semiconductor film is as thick as 150 nm. In this embodiment, diborane (B ₂ H ₆ ) And a dose amount of 2 × 10 ¹³ / Cm ² And the acceleration voltage is 90 keV, and the dose is 1 × 10 ¹⁵ / Cm ² The acceleration voltage was 10 keV. (Fig. 18 (F))
[0084]
Through the above steps, impurity regions 34 and 36 are formed in the respective semiconductor layers.
[0085]
Next, the resist mask 35 is removed, and a 50-nm-thick silicon oxynitride film (composition ratio Si = 32.8%, O = 63.7%, N) is formed as the first interlayer insulating film 37 by plasma CVD. = 3.5%).
[0086]
Next, the crystallinity of the semiconductor layers is restored and the impurity elements added to the respective semiconductor layers are activated by heat treatment. In this example, heat treatment was performed at 550 ° C. for 4 hours in a nitrogen atmosphere by a thermal annealing method using a furnace annealing furnace. (Figure 18 (G))
[0087]
Next, a second interlayer insulating film 38 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 37. In this example, a silicon nitride film having a thickness of 50 nm was formed by a CVD method, and then a silicon oxide film having a thickness of 400 nm was formed.
[0088]
And if it heat-processes, a hydrogenation process can be performed. In this example, heat treatment was performed in a nitrogen atmosphere at 410 ° C. for 1 hour using a furnace annealing furnace.
[0089]
Subsequently, wirings 39 that are electrically connected to the respective impurity regions are formed. In this example, a stacked film of a Ti film with a thickness of 50 nm, an Al—Si film with a thickness of 500 nm, and a Ti film with a thickness of 50 nm was formed by patterning. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti. For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed. (Fig. 18 (H))
[0090]
As described above, an n-channel TFT 51 and a p-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm were formed.
[0091]
The results of measuring these electrical characteristics are shown in FIG. The electrical characteristics of the n-channel TFT 51 are shown in FIG. 19A, and the electrical characteristics of the p-channel TFT 52 are shown in FIG. 19B. The measurement conditions of the electrical characteristics were set to two measurement points, a gate voltage Vg = −16 to 16V, and a drain voltage Vd = 1V and 5V. In FIG. 19, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by a dotted line.
[0092]
Since the semiconductor film crystallized using the present invention has large crystal grains, the number of crystal grain boundaries included in the channel formation region when a TFT is manufactured using the semiconductor film. Can be reduced. Furthermore, since the formed crystal grains are aligned in one direction, the number of times the carriers cross the crystal grain boundary can be extremely reduced. Therefore, a TFT having good electrical characteristics can be obtained as shown in FIG. In particular, the mobility is 524 cm in an n-channel TFT. ² / Vs, 205cm for p-channel TFT ² It turns out that it becomes / Vs. If a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.
[0093]
Although the case of the top gate structure has been described in this embodiment, a bottom gate structure or a dual gate structure may be used. In addition to the glass substrate, a substrate having an insulating surface such as a quartz substrate or a plastic substrate may be used as the substrate.
[0094]
[Example 8]
In this embodiment, an example in which a TFT is manufactured using a semiconductor film crystallized by the method shown in Embodiment 6 will be described with reference to FIGS. 14, 20 to 22, and 23.
[0095]
The steps until the amorphous silicon film is formed as the semiconductor film are the same as those in the seventh embodiment. The amorphous silicon film was formed with a thickness of 150 nm. (FIG. 20 (A))
[0096]
Thereafter, using the method described in JP-A-7-183540, a nickel acetate aqueous solution (weight-concentration concentration 5 ppm, volume 10 ml) is applied onto the semiconductor film by spin coating to form the metal-containing layer 41. To do. Then, heat treatment was performed in a nitrogen atmosphere at 500 ° C. for 1 hour and in a nitrogen atmosphere at 550 ° C. for 12 hours. Thus, the semiconductor film 42 was obtained. (Fig. 20 (B))
[0097]
Subsequently, the crystallinity of the semiconductor film 42 is improved by laser annealing.
[0098]
The conditions of the laser annealing method are as follows: _Four Using the second harmonic of the laser (wavelength: 532 nm, 5.5 W), an elliptical beam of 200 μm × 50 μm was formed with the incident angle φ of the laser beam with respect to the convex lens 103 in the optical system shown in FIG. 14 being about 20 °. The crystallinity of the semiconductor film 42 was improved by irradiating the elliptical beam while moving the substrate at a speed of 20 cm / s or 50 cm / s. In this way, a semiconductor film 43 was obtained. (Figure 20 (C))
[0099]
The process after crystallization of the semiconductor film in FIG. 20C is the same as the process in FIGS. 18C to 18H described in Embodiment 7. Thus, an n-channel TFT 51 and a p-channel TFT 52 having a channel length of 6 μm and a channel width of 4 μm were formed. These electrical characteristics were measured.
[0100]
The electrical characteristics of the TFT manufactured by the above process are shown in FIG. 21, FIG. 22, and FIG.
[0101]
FIGS. 21A and 21B show electrical characteristics of TFTs manufactured by moving the substrate at a speed of 20 cm / s in the laser annealing step of FIG. 20C. FIG. 21A shows electrical characteristics of the n-channel TFT 51. FIG. 21B shows electrical characteristics of the p-channel TFT 52. FIGS. 22A and 22B show electrical characteristics of TFTs manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. 20C. FIG. 22A shows electrical characteristics of the n-channel TFT 51. FIG. 22B shows electrical characteristics of the p-channel TFT 52.
[0102]
The electrical characteristics were measured under the conditions where the gate voltage Vg = −16 to 16V and the drain voltage Vd = 1V and 5V. 21 and 22, the drain current (ID) and the gate current (IG) are indicated by solid lines, and the mobility (μFE) is indicated by a dotted line.
[0103]
Since the semiconductor film crystallized using the present invention has large crystal grains, the number of crystal grain boundaries included in the channel formation region when a TFT is manufactured using the semiconductor film. Can be reduced. Furthermore, since the formed crystal grains are aligned in one direction and there are few grain boundaries formed in the direction intersecting the relative scanning direction of the laser beam, the number of times the carriers cross the crystal grain boundary is extremely small. Can be reduced.
[0104]
Therefore, a TFT having good electrical characteristics can be obtained as shown in FIGS. In particular, the mobility is 510 cm in the n-channel TFT in FIG. ² / Vs, 200cm for p-channel TFT ² / Vs, and 595 cm in the n-channel TFT in FIG. ² / Vs, 199 cm for p-channel TFT ² It can be seen that / Vs is very excellent. If a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.
[0105]
FIG. 23 shows electrical characteristics of a TFT manufactured by moving the substrate at a speed of 50 cm / s in the laser annealing step of FIG. FIG. 23A shows electrical characteristics of the n-channel TFT 51. FIG. 23B shows electrical characteristics of the p-channel TFT 52.
[0106]
The electrical characteristics were measured under the conditions where the gate voltage Vg = −16 to 16V and the drain voltage Vd = 0.1V and 5V.
[0107]
As shown in FIG. 23, a TFT having good electrical characteristics can be obtained. In particular, the mobility is 657 cm in the n-channel TFT shown in FIG. ² / Vs, 219 cm in the p-channel TFT shown in FIG. ² It can be seen that / Vs is very excellent. If a semiconductor device is manufactured using such a TFT, its operating characteristics and reliability can be improved.
[0108]
Although the case of the top gate structure has been described in this embodiment, a bottom gate structure or a dual gate structure may be used. In addition to the glass substrate, a substrate having an insulating surface such as a quartz substrate or a plastic substrate may be used as the substrate.
[0109]
[Example 9]
In this embodiment, electronic devices incorporating a semiconductor device using the sense amplifier of the present invention as described in Embodiment 4 will be described with reference to FIGS.
[0110]
Examples of such electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers, televisions, and the like. Examples of these are shown in FIGS.
[0111]
FIG. 24A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display portion 9004, operation switches 9005, and an antenna 9006. In the present invention, the display portion 9004 can be formed over the same substrate.
[0112]
FIG. 24B illustrates a video camera which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. In the present invention, the display portion 9102 can be formed over the same substrate.
[0113]
FIG. 24C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display portion 9205. In the present invention, the display portion 9205 can be formed over the same substrate.
[0114]
FIG. 24D illustrates a head mounted display which includes a main body 9301, a display portion 9302, and an arm portion 9303. In the present invention, the display portion 9302 can be formed over the same substrate.
[0115]
FIG. 24E illustrates a television set including a main body 9401, a speaker 9402, a display portion 9403, a receiving device 9404, an amplifying device 9405, and the like. In the present invention, the display portion 9403 can be formed over the same substrate.
[0116]
FIG. 24F illustrates a portable book, which includes a main body 9501, a display portion 9502, a storage medium 9504, operation switches 9505, and an antenna 9506, and is stored on a mini disc (MD) or DVD (Digital Versatile Disc). Data and data received by the antenna are displayed. In the present invention, the display portion 9502 can be formed over the same substrate.
[0117]
FIG. 25A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display portion 9603, and a keyboard 9604. In the present invention, the display portion 9603 can be formed over the same substrate.
[0118]
FIG. 25B shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 9701, a display device 9702, a speaker portion 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD, CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. In the present invention, the display portion 9702 can be formed over the same substrate.
[0119]
FIG. 25C illustrates a digital camera which includes a main body 9801, a display portion 9802, an eyepiece portion 9803, an operation switch 9804, and an image receiving portion (not shown). In the present invention, the display portion 9802 can be formed over the same substrate.
[0120]
FIG. 25D illustrates a one-eye head mounted display which includes a display portion 9901 and a head mount portion 9902. In the present invention, the display portion 9901 including an active matrix substrate can be formed over the same substrate.
[0121]
FIG. 26A illustrates a front type projector which includes a projection device 3601 and a screen 3602.
[0122]
FIG. 26B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704.
[0123]
Note that FIG. 26C is a diagram illustrating an example of the structure of the projection devices 3601 and 3702 in FIGS. 26A and 26B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display unit 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but the present invention is not limited to this. For example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in an optical path indicated by an arrow in FIG. Good. The present invention can be integrally formed with the liquid crystal display portion 3808 on the same substrate.
[0124]
FIG. 26D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 26D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0125]
As described above, the applicable range of the present invention is so wide that the present invention can be applied to electronic devices in various fields.
[0126]
【The invention's effect】
According to the sense amplifier of the present invention, it is possible to accurately detect a potential difference between two input signals and reduce malfunctions as much as possible even in a transistor technology with a large threshold variation. In addition, since detection is possible even when the potential difference between the input signals is very small, there is an effect of improving the detection speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of the present invention.
FIG. 2 is an operation timing chart for the first embodiment.
FIG. 3 is a circuit diagram showing connections in main periods with respect to the first embodiment.
FIG. 4 is a circuit diagram of Embodiment 2 of the present invention.
FIG. 5 is an operation timing chart for the second embodiment.
FIG. 6 is a circuit diagram of Embodiment 3 of the present invention.
FIG. 7 is a circuit diagram of Embodiment 4 of the present invention.
FIG. 8 is a circuit diagram according to a fifth embodiment of the present invention.
FIG. 9 is a circuit diagram of Embodiment 6 of the present invention.
FIG. 10 is a circuit diagram of Embodiment 1 of the present invention.
FIG. 11 is a circuit diagram of Embodiment 2 of the present invention.
FIG. 12 is a circuit diagram of Embodiment 3 of the present invention.
FIG. 13 is a circuit diagram of Embodiment 4 of the present invention.
14 is a schematic diagram of an optical system used in Example 5. FIG.
15 is a SEM photograph of the crystalline semiconductor film prepared according to Example 5. FIG.
16 is a SEM photograph of a crystalline semiconductor film prepared according to Example 6. FIG.
FIG. 17 is a result of Raman scattering spectroscopy of the crystalline semiconductor film prepared according to Example 6.
18 is a drawing showing a manufacturing process of a TFT according to Example 7. FIG.
FIG. 19 is a result of electrical characteristics of the TFT fabricated by Example 7.
20 is a drawing showing a manufacturing process of a TFT according to Example 8. FIG.
FIG. 21 is a result of electrical characteristics of the TFT fabricated by Example 8.
22 shows the electrical characteristics results of the TFT manufactured according to Example 8. FIG.
FIG. 23 shows the electrical characteristic results of the TFT manufactured according to Example 8.
FIG. 24 is a diagram illustrating an example of an image display device.
FIG. 25 is a diagram illustrating an example of an image display device.
FIG. 26 is a diagram showing a configuration of a projection type liquid crystal display device.
FIG. 27 is a diagram illustrating an example of a conventional sense amplifier.
[Explanation of symbols]
21 Underlayer
22-26 Semiconductor film
27 Gate insulation film
28 TaN film
29 W film
30, 31 Conductive layer
32 Gate insulation film
33 Mask
34 Impurity region
35 mask
36 Impurity region
37 First interlayer insulating film
38 Second interlayer insulating film
39 Wiring
41 Metal-containing layer
42, 43 Semiconductor film
51 n-channel TFT
52 p-channel TFT
101 laser
102 mirror
103 Convex lens
104 Semiconductor film
105 Glass substrate
106 Elliptical beam
107 Moving direction of glass substrate
108 Moving direction of glass substrate

Claims (12)

First and second PMOS transistors, first and second NMOS transistors, a first input terminal, a second input terminal, an output terminal, first to fourth capacitive elements, and a first To ninth switch,
The first PMOS transistor has a gate electrically connected to a drain of the first PMOS transistor, a gate of the second PMOS transistor, and one terminal of the first switch;
The second PMOS transistor has a drain electrically connected to one terminal of the second switch and the output terminal;
The first NMOS transistor has a source electrically connected to one terminal of the ninth switch and one terminal of the third capacitor, and a gate connected to one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
In the second NMOS transistor, a source is electrically connected to one terminal of the ninth switch and one terminal of the fourth capacitor element, and a gate is one terminal of the second capacitor element, The other terminal of the fourth capacitor element is electrically connected to one terminal of the fourth switch, and the drain is connected to the other terminal of the second switch and the other terminal of the fourth switch. Electrically connected,
The other terminal of the first capacitive element is electrically connected to one terminal of the fifth switch and one terminal of the seventh switch,
The other terminal of the fifth switch is electrically connected to the first input terminal;
The other terminal of the second capacitor element is electrically connected to one terminal of the sixth switch and one terminal of the eighth switch,
The other terminal of the sixth switch is electrically connected to the second input terminal;
A first potential is supplied to the sources of the first and second PMOS transistors,
Wherein the seventh to the other terminal of the ninth switch, the second potential is respectively supplied,
At least one of the first and second switches or the ninth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . 4. The semiconductor device according to claim 1 , wherein each of the first to ninth switches uses an NMOS transistor. First and second PMOS transistors, first and second NMOS transistors, a first input terminal, a second input terminal, an output terminal, first to fourth capacitive elements, and a first To fifth switch,
The first PMOS transistor has a gate electrically connected to a drain of the first PMOS transistor, a gate of the second PMOS transistor, and one terminal of the first switch;
The second PMOS transistor has a drain electrically connected to one terminal of the second switch and the output terminal;
In the first NMOS transistor, a source is electrically connected to one terminal of the fifth switch and one terminal of the third capacitor, and a gate is one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
The second NMOS transistor has a source electrically connected to one terminal of the fifth switch and one terminal of the fourth capacitor element, and a gate connected to one terminal of the second capacitor element, The other terminal of the fourth capacitor element is electrically connected to one terminal of the fourth switch, and the drain is connected to the other terminal of the second switch and the other terminal of the fourth switch. Electrically connected,
The other terminal of the first capacitive element is electrically connected to the first input terminal;
The other terminal of the second capacitive element is electrically connected to the second input terminal,
A first potential is supplied to the sources of the first and second PMOS transistors,
A second potential is supplied to the other terminal of the fifth switch ,
At least one of the first and second switches or the fifth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . First and second resistance elements, first and second NMOS transistors, a first input terminal, a second input terminal, an output terminal, first to fourth capacitance elements, and a first To ninth switch,
Said first resistive element, the first potential is supplied to one, the other is the electrical connection to one terminal of the first switch,
The second resistor element, one of the first potential is supplied to, the other is the electrical connection to one terminal and the output terminal of said second switch,
The first NMOS transistor has a source electrically connected to one terminal of the ninth switch and one terminal of the third capacitor, and a gate connected to one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
In the second NMOS transistor, a source is electrically connected to one terminal of the ninth switch and one terminal of the fourth capacitor element, and a gate is one terminal of the second capacitor element, The other terminal of the fourth capacitor element is electrically connected to one terminal of the fourth switch, and the drain is connected to the other terminal of the second switch and the other terminal of the fourth switch. Electrically connected,
The other terminal of the first capacitive element is electrically connected to one terminal of the fifth switch and one terminal of the seventh switch,
The other terminal of the fifth switch is electrically connected to the first input terminal;
The other terminal of the second capacitor element is electrically connected to one terminal of the sixth switch and one terminal of the eighth switch,
The other terminal of the sixth switch is electrically connected to the second input terminal;
A second potential is supplied to each of the other terminals of the seventh to ninth switches ,
At least one of the first and second switches or the ninth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . First and second resistance elements, first and second NMOS transistors, a first input terminal, a second input terminal, an output terminal, first to fourth capacitance elements, and a first To fifth switch,
One of the first resistance elements is supplied with a first potential, and the other is electrically connected to one terminal of the first switch,
One of the second resistance elements is supplied with the first potential, and the other is electrically connected to one terminal and the output terminal of the second switch,
In the first NMOS transistor, a source is electrically connected to one terminal of the fifth switch and one terminal of the third capacitor, and a gate is one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
The second NMOS transistor has a source electrically connected to one terminal of the fifth switch and one terminal of the fourth capacitor element, and a gate connected to one terminal of the second capacitor element, The other terminal of the fourth capacitor element is electrically connected to one terminal of the fourth switch, and the drain is connected to the other terminal of the second switch and the other terminal of the fourth switch. Electrically connected,
The other terminal of the first capacitive element is electrically connected to the first input terminal;
The other terminal of the second capacitive element is electrically connected to the second input terminal,
A second potential is supplied to the other terminal of the fifth switch ,
At least one of the first and second switches or the fifth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . A first and second NMOS transistor; a first input terminal; a second input terminal; an output terminal; first to fourth capacitive elements; and first to ninth switches. ,
It said first and second switches, the first potential is supplied to one terminal,
The first NMOS transistor has a source electrically connected to one terminal of the ninth switch and one terminal of the third capacitor, and a gate connected to one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
In the second NMOS transistor, a source is electrically connected to one terminal of the ninth switch and one terminal of the fourth capacitor element, and a gate is one terminal of the second capacitor element, The other terminal of the fourth capacitive element and one terminal of the fourth switch are electrically connected, the drain is the other terminal of the second switch, the other terminal of the fourth switch, And electrically connected to the output terminal,
The other terminal of the first capacitive element is electrically connected to one terminal of the fifth switch and one terminal of the seventh switch,
The other terminal of the fifth switch is electrically connected to the first input terminal;
The other terminal of the second capacitor element is electrically connected to one terminal of the sixth switch and one terminal of the eighth switch,
The other terminal of the sixth switch is electrically connected to the second input terminal;
Wherein the seventh to the other terminal of the ninth switch, the second potential is respectively supplied,
At least one of the first and second switches or the ninth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . A first and second NMOS transistor; a first input terminal; a second input terminal; an output terminal; first to fourth capacitive elements; and first to fifth switches. ,
It said first and second switches, the first potential is supplied to one terminal,
In the first NMOS transistor, a source is electrically connected to one terminal of the fifth switch and one terminal of the third capacitor, and a gate is one terminal of the first capacitor, The other terminal of the third capacitive element and one terminal of the third switch are electrically connected, and the drain is connected to the other terminal of the first switch and the other terminal of the third switch. Electrically connected,
The second NMOS transistor has a source electrically connected to one terminal of the fifth switch and one terminal of the fourth capacitor element, and a gate connected to one terminal of the second capacitor element, the other terminal of the fourth capacitor element, and is electrically connected to one terminal of the fourth switch, the drain and the other terminal of the second switch, the other terminal of said fourth switch, And electrically connected to the output terminal,
The other terminal of the first capacitive element is electrically connected to the first input terminal;
The other terminal of the second capacitive element is electrically connected to the second input terminal,
A second potential is supplied to the other terminal of the fifth switch ,
At least one of the first and second switches or the fifth switch is off during a period other than detecting a potential difference between signals input to the first and second input terminals. A semiconductor device . 7. The fifth and sixth switches according to claim 1, wherein the fifth and sixth switches are turned on in a period for detecting a potential difference between signals input to the first and second input terminals. Semiconductor device. Transistor according to any one of claims 1 to 8, wherein a is a thin film transistor. The semiconductor device according to any one of claims 1 to 9, the image display apparatus characterized by being provided over a substrate having an insulating surface over which the pixel portion is provided. Electronic apparatus, characterized in that the semiconductor device according to any one of claims 1 to 9 is incorporated. 12. The electronic device according to claim 11 , wherein the electronic device is any one of an electronic notebook, a mobile computer, a mobile phone, a video camera, a still camera, a personal computer, a television, a front projector, and a rear projector. .

Images