JP6114796B1 - Sense circuit for nonvolatile memory device and nonvolatile memory device - Google Patents

Abstract

A data value is accurately sensed even when a variation in threshold voltage of a MOS transistor increases. In a sense circuit 30A for sensing data, a first signal is provided in a page buffer PBn including a latch L1 for temporarily storing data when data is written to or read from a memory cell of a nonvolatile memory device. Between the first switch element N1 and the stacked gate type control element N1 connected in series between the line B and the first terminal SLS1 of the latch, and between the first switch element and the stacked gate type control element And a second switch element N2 connected to. Before the start of sensing when the first switch element is turned on by the sense enable signal SW, the voltage of the floating gate of the stacked gate type control element is set to a threshold voltage seen from the floating gate of the stacked gate type control element. After the voltage value is set to the sum of the voltages, the memory cell data is sensed. [Selection] Figure 7

Description

  The present invention relates to a sense circuit and a nonvolatile memory device for an electrically rewritable nonvolatile semiconductor memory device (EEPROM) such as a flash memory.

  2. Description of the Related Art A NAND-type nonvolatile semiconductor memory device is known in which a NAND string is configured by connecting a plurality of memory cell transistors (hereinafter referred to as memory cells) in series between a bit line and a source line to realize high integration. (For example, refer to Patent Document 1).

  FIG. 1A is a block diagram showing an entire configuration of a NAND flash EEPROM according to a conventional example. FIG. 1B is a circuit diagram showing the configuration of the memory cell array 10 of FIG. 1A and its peripheral circuits.

  1A, a NAND flash EEPROM according to a conventional example includes a memory cell array 10, a control circuit 11 for controlling the operation thereof, a row decoder 12, a high voltage generation circuit 13, and a page buffer including a data rewrite / read circuit. The circuit 14, column decoder 15, command register 17, address register 18, operation logic controller 19, data input / output buffer 50, and data input / output terminal 51 are configured.

  As shown in FIG. 1B, the memory cell array 10 includes, for example, 16 stacked gate structure electrically rewritable nonvolatile memory cells MC0 to MC15 connected in series to form NAND cell units NU (NU0, NU1,...). Composed. Each NAND cell unit NU has a drain side connected to the bit line BL via the selection gate transistor SG1, and a source side connected to the common source line CELSRC via the selection gate transistor SG2. The control gates of the memory cells MC arranged in the row direction are commonly connected to the word line WL, and the gate electrodes of the selection gate transistors SG1 and SG2 are connected to selection gate lines SGD and SGS arranged in parallel with the word line WL. The A range of memory cells selected by one word line WL is one page as a unit of writing and reading. A range of a plurality of NAND cell units NU in one page or an integral multiple of one page is one block as a data erasing unit. The page buffer circuit 14 includes a sense amplifier circuit (SA) and a latch circuit (DL) provided for each bit line in order to write and read data in page units.

  The memory cell array 10 of FIG. 1B has a simplified configuration, and a page buffer may be shared by a plurality of bit lines. In this case, the number of bit lines selectively connected to the page buffer at the time of data write or read operation is a unit of one page. FIG. 1B shows a range of the cell array in which data is input / output to / from one input / output terminal 51. In order to select a word line WL and a bit line BL of the memory cell array 10, a row decoder 12 and a column decoder 15 are provided, respectively. The control circuit 11 performs sequence control of data writing, erasing and reading. The high voltage generation circuit 13 controlled by the control circuit 11 generates a boosted high voltage or intermediate voltage used for data rewriting, erasing, and reading.

  The input / output buffer 50 is used for data input / output and address signal input. That is, data is transferred between the input / output terminal 51 and the page buffer circuit 14 via the input / output buffer 50 and the data signal line 52. An address signal input from the data input / output terminal 51 is held in the address register 18 and sent to the row decoder 12 and the column decoder 15 to be decoded. An operation control command is also input from the data input / output terminal 51. The input command is decoded and held in the command register 17, whereby the control circuit 11 is controlled. External control signals such as a chip enable signal CEB, command latch enable CLE, address latch enable signal ALE, write enable signal WEB, and read enable signal REB are taken into the operation logic controller 19, and an internal control signal is generated according to the operation mode. The The internal control signal is used for control such as data latch and transfer in the input / output buffer 50, and is further sent to the control circuit 11 for operation control.

  The page buffer circuit 14 includes two latch circuits 14a and 14b, and is configured to be able to switch between a multi-value operation function and a cache function. That is, a cache function is provided when 1-bit binary data is stored in one memory cell, and a cache function is provided when 2-bit quaternary data is stored in one memory cell. However, the cache function can be enabled.

  FIG. 1C is a block diagram showing a configuration example of the page buffer circuit 14 and the program end detection circuit 16 in the NAND flash EEPROM of FIG. 1A. In FIG. 1C, the program end detection circuit 16 detects the end of the program based on the judgment control signal from the page buffer PBn (n = 0, 1, 2,..., N). Hereinafter, the program (data writing) and verify determination and the fail bit count will be described.

  In the NAND flash EEPROM, one page of data is written into a memory cell at a time. Here, in order to check whether or not all bits have been written, a program verify process for each bit (hereinafter, program verify is also referred to as “verify”) is employed. Basically, the verify process is completed assuming that all bits have passed after all bits have exceeded a predetermined threshold voltage Vth. However, in the recent flash memory, even if some fail bits remain, the pass state is set. This is called “pseudo-pass processing” and is used to set a path in the user mode. This is used when a large number of bits are operating under the ECC (Error Checking and Correction) function, and because of the ECC function of many bits, a few bits at the time of data writing are pseudo-passed. But it doesn't matter as a whole. When program characteristics or failure analysis is performed, the time can be shortened and the efficiency can be improved by evaluating by increasing or decreasing the number of bits of the pseudo pass.

  FIG. 2 is a circuit diagram showing a detailed configuration example of the program end detection circuit 16 of FIG. 1C. FIG. 3 is a circuit diagram showing a configuration example of the page buffer PBn and the program end determination unit 29-n in FIG.

  In FIG. 2, the power supply voltage VDD is grounded via MOS transistors 21 and 22, and the connection point of the MOS transistors 21 and 22 is connected via a signal line A (PBPUP) which is a signal output line for outputting a determination result and an inverter 23. A state signal STB indicating whether or not the state is a pass state is generated. The determination enable signal JENB is applied to the gate of the MOS transistor 21, and the determination reset signal JRST is applied to the gate of the MOS transistor 22. The signal line A (PBPUP) is grounded via the MOS transistor TJn connected to each page buffer PBn and the MOS transistor TJEn to which the verify determination switching signal JDG_SW is applied to the gate (n = 0, 1,..., N ). Each of the MOS transistors TJn and TJEn constitutes a program end determination unit 29-n, and constitutes a program end determination circuit 27 as a whole.

  In FIG. 3, the gate of the MOS transistor Tjn is connected to the node SLS1 of the latch L1 of the page buffer PBn. The page buffer PBn includes a latch L1 composed of two inverters 61 and 62, a latch L2 composed of two inverters 63 and 64, a verifying capacitor 70, a precharging transistor 71, and a verifying transistor. Transistors 72 to 74, column gate transistors 81 and 82, transfer switch transistors 83 to 85, 88, and 89, bit line selection transistors 86 and 87, and a reset transistor 90 are included.

  In FIG. 3, two bit lines BLe and BLo are selectively connected to the page buffer PBn. In this case, the bit line selection transistor 86 or 87 is turned on by the bit line selection signal BLSE or BLSO, and either the bit line BLe or the bit line BLo is selectively connected to the page buffer PBn. While one bit line is selected, the other bit line that is in the non-selected state is set to a fixed ground potential or power supply voltage potential by the bit line non-selection signal YBLE or YBLO. Reduce noise.

  The page buffer PBn in FIG. 3 includes a first latch L1 and a second latch L2. The page buffer PBn mainly contributes to read and write operations by predetermined operation control. The second latch L2 is a secondary latch circuit that realizes a cache function in the binary operation, and supplementarily contributes to the operation of the page buffer PBn when the cache function is not used. Realize multi-valued operation.

  The latch L1 is configured by connecting clocked inverters 61 and 62 in antiparallel. The bit lines BLe and BLo of the memory cell array 10 are connected to the sense node SNS via the transfer switch transistor 85, and the sense node SNS is further connected to the data holding node SLR1 of the latch L1 via the transfer switch transistor 83. A precharge transistor 71 is provided in the sense node SNS. Node SLR1 is connected to temporary storage node N3 for temporarily storing data of node SLR1 via transfer switch transistor 74. The node N3 is connected to the gate of the transistor 72, the drain of the transistor 72 is connected to the voltage V2, the source is connected to the sense node SNS via the switch transistor 73, and the sense node is determined by the signal REG of the switch transistor 73 and the voltage value of the node N3. Connection or disconnection of the SNS and the voltage V2 is controlled. Further, a precharge transistor 71 for precharging the voltage V1 with respect to the bit lines BLe and BLo is also connected to the sense node SNS. A capacitor 70 for maintaining the level is connected to the sense node SNS. The other end of the capacitor 70 is grounded.

  Similarly to the first latch L1, the second latch L2 is configured by connecting clocked inverters 63 and 64 in antiparallel. The two data nodes SLR2 and SLS2 of the latch L2 are connected to a data signal line 52 connected to the data input / output buffer 50 via column gate transistors 81 and 82 controlled by a column selection signal CSL. The node SLR2 is connected to the sense node SNS through the transfer switch transistor 84.

  FIG. 1B shows a connection relationship between the memory cell array 10, the page buffer PBn, and the data input / output buffer 50. The processing unit for reading and writing of the NAND flash EEPROM is a capacity for one page (for example, 512 bytes) selected simultaneously at a certain row address. Since there are eight data input / output terminals 51, one data input / output terminal 51 has, for example, 512 bits, and FIG. 1B shows a configuration for 512 bits.

  When data is written to the memory cell, the write data is fetched from the data signal line 52 into the second latch L2. In order to start the write operation, the write data must be in the first latch L1, and then the data held in the latch L2 is transferred to the latch circuit L1. In the read operation, in order to output data to the data input / output terminal 51, since the read data must be in the latch L2, the data read by the latch L1 needs to be transferred to the latch L2. Accordingly, the transfer switch transistors 83 and 84 are turned on so that data can be transferred between the latch L1 and the latch L2. At this time, the data is transferred after the transfer destination latch circuit is deactivated, and then the transfer destination latch circuit is returned to the active state to hold the data.

  Next, the operation of the program end detection circuit 16 shown in FIGS. 2 and 3 will be described below.

  First, data “1” is set in the latch L1 of the page buffer PBn corresponding to the memory cell not to be programmed, and the voltage of the node SLR1 becomes high level, and is excluded from the target of the verify determination process. When the program-verify fail is performed on the memory cell to be programmed, the data “0” remains set in the latch L1 of the page buffer PBn, and the voltage of the node SLR1 becomes low level. In the program verify pass, data “1” is set in the latch L1 of the page buffer PBn, and the voltage of the node SLR1 becomes high level. The state of these latches L1 is reflected in the on / off state of the MOS transistor TJn and used for the verify determination process. As shown in FIG. 2, the MOS transistors TJn (n = 0, 1,..., N) are connected to a signal line A (PBPUP) that performs a NOR operation. If the programming is completed for all the memory cells in one page and all the nodes SLR1 become high level, all the MOS transistors TJn are turned off. At that time, the signal line A (PBPUP) becomes high level, and the status signal STB becomes low level, so that it can be known that the program is finished.

  Next, the “pseudo pass program” according to the prior art will be described below.

  FIG. 4 is a circuit diagram showing a configuration example of a program end detection circuit 16A for determining a pseudo path in the NAND flash EEPROM of FIG. 1A.

  On the left side of FIG. 4, the above-described program end determination circuit 27 including program end determination units 29-0 to 29-N is provided. The signal line A (PBPUP) is supplied from the power supply voltage VDD through the MOS transistor 24. A drain current n × Id that is an integer n times the drain current Id flows. Here, the integer n is the number of circuits 29 through which the drain current Id flows corresponding to the number of memory cells that have not passed program verification yet. On the other hand, the reference current generating circuit 28 on the right side of FIG. 4 includes reference voltage generating units 29a-0 to 29a-J, and a plurality of MOS transistor pairs (BFj) connected between the signal line A ′ (PBREF) and the ground. , BFEj) (where j = 0, 1,..., J). Here, the MOS transistors BFE1 to BFEJ are replica circuits in which the transistor size and voltage application are set exactly the same so that the current Id having the same value as the drain current Id of the circuit 29 flows. The sizes or gate voltages of the MOS transistors BF0 and BFE0 are controlled so that the drain current 0.5Id flows. In addition, each reference current generation unit including a pair of MOS transistors (BF0, BFE0; BF1, BFE1; BF2, BFE2;...) Flows from the power supply voltage VDD through the MOS transistor 25 to the signal line PBREF. A threshold reference current Iref that is the sum of the unit reference currents flows.

  The voltage corresponding to the drain current n × Id flowing in the MOS transistor 24 is applied to the inverting input terminal of the comparator 26 according to the number n of the MOS transistors TJn turned on in the program end determination circuit 27, while the MOS transistor A voltage corresponding to the threshold reference current Iref flowing through 25 is applied to the non-inverting input terminal of the comparator 26, and the comparator 26 outputs a low level state signal STB when n × Id <Iref. That is, the number N of memory cells that have not passed program verification for J + 1 sets of MOS transistors BFj, BFEj (j = 0, 1,..., J) through which the threshold reference current Iref flows is J ≧ N. At this time, the status signal STB is at a low level, and is determined to be a pseudo pass. For example, since threshold reference current Iref = 2.5Id when J = 2, the drain current N × Id flowing through the program end determination circuit 27 becomes a pseudo path when N ≦ 2.

  FIG. 5 is a flowchart showing the program path determination process of the NAND flash EEPROM of FIG. 1A. In FIG. 5, first, data is loaded in step S101, the data is programmed in step S102, and then verified in step S103. If all the memory cells (for one page) are all “1” in step S104, it is determined as “true pass” in step S105, and the process is terminated. On the other hand, if “NO” in the step S104, it is determined whether or not a timeout has occurred in a step S106. If “NO”, the process returns to the step S102, and if “YES”, the process proceeds to the step S107. In step S107, it is determined whether the error can be tolerated. If YES, the process proceeds to step S108, and if NO, the process proceeds to step S109. In step S108, it is determined as a “pseudo path” and the process ends. In step S109, it is determined as “fail” and the process is terminated.

JP-A-9-147582 JP 2006-134482 A JP2013-127825A JP 2008-004178 A JP 2008-198337 A

  A conventional NAND flash memory uses an inverter type circuit such as the inverter 62 of FIG. 3 as a sense amplifier when reading data from a memory cell. If the bit line voltage is higher than the trip point of the inverter, 0 data, If it is lower than the trip point, it is determined as one data. However, in such a simple sense amplifier circuit, as the NAND flash memory is miniaturized, there is a problem that the variation in trip points due to manufacturing variations increases, and data cannot be accurately determined.

  Also, since the recent NAND flash memory has an ECC (Error Checking and Correction) capacity of 4 bits or more, some of the ECC capacity is allocated to the program or data erasure fail bit relief shown in FIG. Can do. The current Id × n of the signal line A (PBPUP) is compared with the reference current Iref of the reference signal line PBREF. At this time, when the MOS transistor BF0 is turned on and the reference current Iref = 0.5 × Id, if the number of unprogrammed memory cells is 1 or more, the program end notification signal STB becomes a high level, and the fail state Indicates. On the other hand, if all the memory cells are programmed, the program state becomes the pass state, and the program end notification signal STB becomes the low level. For example, when the reference current Iref is set to 2.5 × Id, the pass state is set even if the number of unprogrammed memory cells is 2 or less, which is the “pseudo pass state”. As the miniaturization of the NAND flash memory progresses, the number of bits relieved by ECC increases and the number of pseudo pass bits can increase. However, such a simple program end detection circuit 16A has a problem that it cannot cope with a pseudo-pass state of many bits.

  FIG. 6 is a plan view showing an arrangement example of MOS transistors constituting the page buffer PBn and the program end determination unit 29-n in FIG. 3, and FIG. 6A is a plan view in which gates are arranged along the bit lines. FIG. 6B is a plan view showing an example in which the gates are arranged at right angles to the bit lines. In FIG. 6, G1 and G2 are gates, AR1 and AR2 are active regions, and CH1 and CH2 are contact holes.

  For example, in the configuration example of the NAND flash memory, the pitch of a pair of memory cells is, for example, 30 nm × 2, and the page buffer PBn is laid out in a space for 16 bit lines. 96 μm. Here, eight PBn are stacked per layout.

  In FIG. 6, it is necessary to form the above-described MOS transistors TJn and TJEn in a very narrow page buffer PBn pitch layout of, for example, 0.96 μm. Of course, it is possible to use an area of 2 × 0.96 μm, but if this size is used in all parts, the height of the page buffer PBn is doubled, and the size of the page buffer PBn is greatly increased. Therefore, it is necessary to make these MOS transistors smaller in accordance with miniaturization of the flash memory, and there is a problem that variation in electrical characteristics of these MOS transistors increases more and more.

  In addition, there is a high possibility that the page size will further increase in the future, and accordingly, the variation in the electrical characteristics of the MOS transistors in one chip also increases. If the variation is standard deviation σ = 10 mV (2%) and the average voltage of the sense amplifier trip point is 0.5 V, the worst variation is 10% in the page buffer. If the P-channel MOS transistor and the N-channel MOS transistor are arranged slightly apart, the trip point variation may be different by 10% or more in the worst case. As described above, the variation in the electrical characteristics of the MOS transistor greatly affects the sense accuracy of the flash memory that is further miniaturized.

  The object of the present invention is to compare with the prior art even if the pitch of the memory cells is reduced with the miniaturization of a nonvolatile memory device such as a NAND flash memory and the transistor size of the peripheral circuit is accordingly reduced. It is an object of the present invention to provide a sense circuit and a nonvolatile memory device for a nonvolatile memory device that can accurately sense a data value.

A sense circuit according to a first aspect of the present invention is provided in a page buffer including a latch for temporarily storing data when data is written to or read from a memory cell of a nonvolatile memory device, and senses the data.
A first switch element and a stacked gate type control element inserted between the first signal line and the first terminal of the latch and connected in series;
A second switch element connected between the first switch element and the stacked gate type control element;
A first terminal of the latch is connected to a first terminal of the first switch element;
A second terminal of the first switch element is connected to a first terminal of the stacked gate control element and a first terminal of the second switch element;
A second terminal of the second switch element is connected to a floating gate of the stacked gate type control element;
A second terminal of the stacked gate type control element is connected to the first signal line;
The first switch element is turned on or off by a sense enable signal,
The second switch element is turned on or off by a sense determination switching signal,
The stacked gate type control element is controlled by a signal voltage of a sense node of the sense circuit connected to the second terminal of the latch,
Prior to the start of sensing when the first switch element is turned on by the sense enable signal, the voltage of the floating gate of the stacked gate type control element is a threshold voltage viewed from the floating node of the stacked gate type control element. After the predetermined voltage is set to the voltage value, the data of the memory cell is sensed and stored in the latch.

In the sense circuit, the stacked gate type control element is:
(1) A stacked gate type MOS transistor or (2) a MOS transistor having a gate to which a capacitor is connected.

  In the sense circuit, the stacked gate MOS transistor has a structure similar to that of the stacked gate MOS transistor among the MOS transistors of the memory cell of the nonvolatile memory device.

  Further, in the sense circuit, the predetermined voltage is one voltage value in a range of 0V to 1.5V.

  Still further, in the sense circuit, the voltage setting of the voltage of the floating gate of the stacked gate type control element is executed by charging from the first terminal of the latch or the first signal line. To do.

The sense circuit further includes third and fourth switch elements inserted between the second signal line and the second terminal of the first switch element and connected in series to each other.
The first terminal of the third switch element is connected to the second signal line, the second terminal of the third switch element is connected to the first terminal of the fourth switch element, and The second terminal of the fourth switch element is connected to the second terminal of the first switch element,
The third switch element is turned on or off by the voltage of the first terminal of the latch or the second terminal of the latch,
The fourth switch element is turned on or off by a predetermined verify determination switching signal.

  Further, in the sense circuit, when the data is sensed for the verify read after the data is written, the voltage setting of the floating gate of the stacked gate type control element is set to the first terminal of the latch or the first It is executed by charging from the signal line.

  Furthermore, in the sense circuit, when the data is sensed for verify read after the data is written, the voltage setting of the floating gate of the stacked gate type control element is set by the first signal line or the second signal line. It is executed by charging from the signal line.

  Here, in the sense circuit, when the data is sensed for the verify read after the data is written, the voltage setting of the floating gate of the stacked gate type control element is set by charging from the first signal line. It is executed.

The sense circuit further includes a fifth switch element connected between the second signal line and the second terminal of the first switch element,
The first terminal of the first switch element is connected to the second terminal of the latch instead of the first terminal of the latch,
A first terminal of the fifth switch element is connected to the second signal line; a second terminal of the fifth switch element is connected to a second terminal of the first switch element;
The fifth switch element is turned on or off by the voltage of the first terminal of the latch or the second terminal of the latch.

  In the sense circuit, when data is sensed for verify read after the data is written, the voltage setting of the floating gate of the stacked gate type control element is performed after inverting the data stored in the latch. This is executed by charging from the second terminal of the latch or the first signal line.

  Further, in the sense circuit, when the data is sensed for verify reading after the data is written, the voltage setting of the floating gate of the stacked gate type control element is set by the second signal line or the first signal. After charging from the signal line, the data stored in the latch is inverted, the second signal line is floated, and the first signal line is set to the predetermined voltage. It is characterized by that.

In the sense circuit, the third switch element is an N-channel MOS transistor,
The third switch element is turned on or off by the voltage of the first terminal of the latch.

In the sense circuit, the third switch element is a P-channel MOS transistor.
The third switch element is turned on or off by the voltage of the second terminal of the latch.

Furthermore, in the sense circuit, the fifth switch element is an N-channel MOS transistor,
The fifth switch element is turned on or off by the voltage of the first terminal of the latch.

Still further, in the sense circuit, the fifth switch element is a P-channel MOS transistor,
The fifth switch element is turned on or off by the voltage of the second terminal of the latch.

  A non-volatile memory device according to a second aspect of the invention includes the sense circuit.

  According to the sense circuit for a nonvolatile memory device according to the present invention, the pitch of the memory cells is reduced with the miniaturization of the nonvolatile memory device such as a NAND flash memory, and the transistor size of the peripheral circuit is accordingly accompanied. Even if becomes smaller, the data value can be sensed more accurately than in the prior art.

It is a block diagram which shows the whole structure of the NAND type flash EEPROM which concerns on a prior art example. 1B is a circuit diagram showing a configuration of the memory cell array 10 of FIG. 1A and its peripheral circuits. FIG. 1B is a block diagram showing a configuration example of a page buffer circuit 14 and a program end detection circuit 16 in the NAND flash EEPROM of FIG. 1A. FIG. It is a circuit diagram which shows the detailed structural example of the program completion | finish detection circuit 16 of FIG. 1C. FIG. 3 is a circuit diagram illustrating a configuration example of a page buffer PBn and a program end determination unit 29-n in FIG. 1B is a circuit diagram showing a configuration example of a program end detection circuit 16A for pseudo path determination in the NAND flash EEPROM of FIG. 1A. FIG. 1B is a flowchart showing a program path determination process of the NAND flash EEPROM of FIG. 1A. 4A is a plan view showing an arrangement example of MOS transistors constituting the page buffer PBn and the program end determination unit 29-n in FIG. 3, and FIG. 4A is a plan view in which gates are arranged along a bit line; FIG. 3 is a plan view showing an example in which gates are arranged at right angles to bit lines. 3 is a circuit diagram showing a configuration example of a sense circuit 30A and a page buffer PBn for the NAND flash EEPROM according to the first embodiment. FIG. FIG. 8 is a flowchart showing a data read process executed by a sense circuit 30A and a page buffer PBn in FIG. FIG. 10 is a circuit diagram showing a configuration example of a sense circuit 30B and a page buffer PBn for a NAND flash EEPROM according to the second embodiment. 10 is a flowchart showing a data program and a verify process (when programming with SLR1 = Low) according to the embodiment 2-1, which are executed by the sense circuit 30B and the page buffer PBn of FIG. It is a flowchart which shows the data judgment process which is a subroutine of FIG. 10 is a flowchart showing a data program and a verify process (when not programmed with SLR1 = High) according to the embodiment 2-1, which are executed by the sense circuit 30B and the page buffer PBn of FIG. 10 is a flowchart illustrating a data program and a verify process (when programming with SLR1 = Low) according to the embodiment 2-2, which is executed by the sense circuit 30B and the page buffer PBn of FIG. 10 is a flowchart illustrating a data program and a verify process (when not programmed with SLR1 = High) according to the embodiment 2-2, which is executed by the sense circuit 30B and the page buffer PBn of FIG. 10 is a flowchart illustrating a data program and a verify process (when programming with SLR1 = Low) according to Embodiment 2-3, which is executed by the sense circuit 30B and the page buffer PBn of FIG. 10 is a flowchart illustrating a data program and a verify process (when not programmed with SLR1 = High) according to the embodiment 2-3, which is executed by the sense circuit 30B and the page buffer PBn in FIG. FIG. 10 is a circuit diagram showing a configuration example of a sense circuit 30C and a page buffer PBn for a NAND flash EEPROM according to a third embodiment. 18 is a flowchart showing a data program and a verify process (when programming with SLR1 = Low) according to Embodiment 3-1, which are executed by the sense circuit 30C and the page buffer PBn of FIG. It is a flowchart which shows the data judgment process which is a subroutine of FIG. 18 is a flowchart showing a data program and a verify process (when not programmed with SLR1 = High) according to Embodiment 3-1, which are executed by the sense circuit 30C and the page buffer PBn of FIG. 18 is a flowchart showing a data program and verify process (when programming with SLR1 = Low) according to Embodiment 3-2, which is executed by the sense circuit 30C and the page buffer PBn of FIG. 18 is a flowchart illustrating a data program and a verify process (when not programmed with SLR1 = High) according to the embodiment 3-2, which are executed by the sense circuit 30C and the page buffer PBn in FIG. FIG. 10 is a circuit diagram showing a configuration example of a sense circuit 30D and a page buffer PBn for a NAND flash EEPROM according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a part of a sense circuit 30E according to a modification.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
FIG. 7 is a circuit diagram showing a configuration example of the sense circuit 30A and the page buffer PBn for the NAND flash EEPROM according to the first embodiment. In FIG. 7, the sense circuit 30A according to the first embodiment is provided for each page buffer PBn, and is provided between the node SNS, SLS1 of the page buffer PBn and the signal line B, and one stacked gate type N channel. A MOS transistor N1 and two N-channel MOS transistors N2 and N3 each serving as a switching element are provided.

  The control gate of MOS transistor N1 is connected to node SNS (sense node of page buffer PBn), the floating gate of MOS transistor N1 is connected to the source of MOS transistor N2, and the source of MOS transistor N1 is connected to signal line B. . The drain of the MOS transistor N1 is connected to the source of the MOS transistor N3 and the drain of the MOS transistor N2. Further, a sense determination switching signal JDG_SW that is turned on when setting the potential of the source and floating gate of the MOS transistor N1 is applied to the gate of the MOS transistor N2. . Further, a sense enable signal SW for putting the sense circuit 30A into an operating state (sense state) is applied to the gate of the MOS transistor N3. The sense determination switching signal JDG_SW and the sense enable signal SW are generated by the control circuit 11 of FIG.

  The latch L1 of the page buffer PBn is a temporary storage element for storing the program data or program verify state of the memory cell corresponding to the page buffer PBn. The node SLS1 of the latch L1 of the page buffer PBn is connected to the drain of the MOS transistor N3. Then, the signal voltage of the node SNS of the page buffer PBn is applied to the control gate of the MOS transistor N1. Here, the signal voltage or node of the drain of the MOS transistor N1 is described by JDG_D, and the signal voltage or node of the floating gate of the MOS transistor N1 is described by JDG_G.

  The present embodiment is characterized in that a sense circuit 30A including a stacked gate type MOS transistor N1 is provided in order to compensate for variations in threshold voltage of the MOS transistor. The sense circuit 30A is connected to the node SLS1 of the latch L1, and the operation of the sense circuit 30A is determined by the stacked gate type MOS transistor N1 that receives the signal voltage of the node SNS of the page buffer PBn as a gate voltage. The stacked gate type MOS transistor N1 sets the voltage of the floating gate to a value based on the threshold value of N1 seen from the floating gate, thereby reducing the variation of the threshold value of the MOS transistor seen from the control gate. Can be compensated. (Hereinafter, this stacked gate type MOS transistor N1 may be simply referred to as a MOS transistor N1.)

  FIG. 8 is a flowchart showing a data read process from the memory cell executed by the sense circuit 30A and the page buffer PBn of FIG. In the specification and drawings of the present application, for simplification of description, the symbols of each node are shared as the symbol of the node name and the symbol of the node voltage or signal voltage. Further, in the flowcharts of the following processes, “=” represents the setting of each signal or the signal voltage as a processing result. For example, N3 = ON represents that the MOS transistor N3 is turned on, and N3 = OFF represents that the MOS transistor N3 is turned off. Further, High represents a predetermined high level such as 5V, and Low represents a predetermined low level such as 0V (ground voltage).

  In step S1 of FIG. 8, the data in the latch L1 is reset to set the node SLS1 to the power supply voltage VDD, the sense enable signal SW is set to 0V, the MOS transistor N3 is turned off, and the node SNS is set to the power supply voltage VDD. Next, in step S2, the signal line B is set to the power supply voltage VDD, the sense determination switching signal JDG_SW is set to the power supply voltage VDD to turn on the MOS transistor N2, and the sense enable signal SW is set to the power supply voltage VDD. As a result, the MOS transistor N3 is turned on. At this time, the node voltages JDG_D and JDG_G are as follows.

JDG_D = VDD−Vth (N3) (1)
JDG_G = VDD−Max (Vth (N2), Vth (N3)) (2)

  Here, Vth (N3) represents the threshold voltage of the MOS transistor N3, and Max (•) is a maximum value function indicating the maximum value of the plurality of arguments. For example, Max (Vth (N2), Vth (N3)) represents the higher threshold voltage of the threshold voltage of the MOS transistor N2 and the threshold voltage of the MOS transistor N3, and so on.

  In step S3, the sense enable signal SW is set to 0V (ground voltage) to turn off the MOS transistor N3. Next, in step S4, the signal line B is set to a predetermined voltage Va (for example, 0V to 1.5V). At this time, the current flows from the node JDG_G to the signal line B via the MOS transistor N2, the node JDG_D, and the MOS transistor N1. Flows. The node voltage JDG_G is expressed by the following equation by this current charge.

JDG_G = JDG_D = Vth (N1) + Va (3)

  Here, Vth (N1) represents the threshold voltage of the MOS transistor N1 viewed from the floating gate of the MOS transistor N1. As apparent from the equation (3), the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to a voltage obtained by adding the predetermined voltage Va to the threshold voltage viewed from the floating gate of the MOS transistor N1. .

  Next, in step S5, the sense determination switching signal JDG_SW is set to 0 V (ground voltage) to turn off the MOS transistor N2. At this time, the floating gate JDG_G of the MOS transistor N1 is in a floating state while maintaining the voltage Vth (N1) + Va. In step S6, in order to connect the bit line BLe or BLo in the page buffer PBn, the transistors 85 and 86 are turned on by BLSE = High and BLCLAMP = High, or the transistors 85 and 87 are turned on by BLSO = High and BLCLAMP = High. Thus, the data read from the memory cell is transferred to the SNS. In step S7, the latch L1 enters a high impedance state, and the inverters 61 and 62 enter a non-operating state.

  In step S8, the signal line B is set to 0V (ground voltage). Under this condition, the threshold value of the MOS transistor N1 viewed from the control gate is VDD−Va / α (α is called a coupling ratio, the capacitance between the control gate and the floating gate of the MOS transistor N1, and the floating gate. And a value of 0 or more and 1 or less determined by the capacitance ratio of the capacitance between the substrates). Then, by setting the sense enable signal SW to the power supply voltage VDD, the MOS transistor N3 is turned on to start data sensing. In step S9, it is determined whether or not the node voltage SNS is equal to or higher than the threshold value of the MOS transistor N1 as viewed from the control gate and the program state is set. If YES, the process proceeds to step S10. Proceed to In step S10, since the MOS transistor N1 is on and the MOS transistor N3 is on at this time, a current flows from the node SLS1 to the signal line B via the MOS transistors N3 and N1, and the node voltage SLS1 is at a low level (0V). ) And the process proceeds to step S12. On the other hand, in step S11, the node voltage JDG_G decreases due to the capacitive coupling of the MOS transistor N1, the MOS transistor N1 is turned off, and no current flows from the node SLS1 to the signal line B via the MOS transistors N3 and N1. The voltage SLS1 is held at a high level (power supply voltage VDD), and the process proceeds to step S12. Further, in step S12, the sense enable signal SW is set to 0V (ground voltage) to turn off the MOS transistor N3. In step S13, the inverter 61 is set in the operating state, and then the inverter 62 is set in the operating state. At this time, the latch L1 holds the data read from the memory cell and ends the processing. Note that after the processing in step S13, data is transferred to the latch L2 (see FIGS. 1B and 3), and data output and the like are performed, as in the prior art.

  As described above, according to the present embodiment, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1 before sensing the data of the memory cell. Since the voltage is set by adding the predetermined voltage Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

  In the above embodiments, the stacked gate type MOS transistor N1 is preferably not a peripheral circuit MOS transistor having a structure in which a control gate and a floating gate are directly connected in a nonvolatile memory device such as a flash memory. It is formed to have the same structure as a stacked gate MOS transistor for a cell. This is the same in the embodiments and modifications described later. Although the name of the floating gate comes from the floating gate of the memory cell, a gate electrode is formed in the stacked gate type MOS transistor N1 so that it can be connected to another circuit.

Embodiment 2. FIG.
FIG. 9 is a circuit diagram showing a configuration example of the sense circuit 30B and the page buffer PBn for the NAND flash EEPROM according to the second embodiment. The sense circuit 30B according to the second embodiment includes a data program and a verify process (including a case where the node voltage SLR1 is programmed at a low level and a case where the node voltage SLR1 is not programmed at a high level) in addition to data reading. The sense circuit is different from the sense circuit 30A according to the first embodiment in FIG. 7 in the following points.
(1) In addition to the MOS transistors N1 and N2, the sense circuit 30B is turned on / off based on the N channel MOS transistor N5 which is a switch element connected to the signal line A and the node SLS1 and the verify determination switching signal VSW. And an N channel MOS transistor N4 which is a switching element.
(2) The MOS transistor N3 is turned on / off based on the sense enable signal SSW instead of the sense enable signal SW.

  In FIG. 9, MOS transistors N5 and N4 are inserted and connected between the signal line A (PBPUP) and the source of the MOS transistor N3. Here, the signal line A (PBPUP) is connected to the drain of the MOS transistor N5, the source of the MOS transistor N5 is connected to the drain of the MOS transistor N4, the source of the MOS transistor N4 is the source of the MOS transistor N3, and the MOS transistor N1. And N2 to each drain.

  Here, the signal lines A (PBPUP) and B are a pair of signal lines for outputting a program end determination signal (see, for example, FIG. 4). The sense determination switching signal JDG_SW, the sense enable signal SSW, and the verification determination switching signal VSW are generated by the control circuit 11 of FIG.

Embodiment 2-1.
FIG. 10 shows a data program and a verify process according to the embodiment 2-1 executed by the sense circuit 30B and the page buffer PBn of FIG. 9 (when SLR1 = Low and SLR1 = 0V and SLS1 = VDD). It is a flowchart to show. The data program and verify process of FIG. 10 differ from the data read process of FIG. 8 in the following points. In each process of FIG. 10, a difference from the corresponding process in FIG. 8 is indicated by an underline, and similarly, a difference from the previous corresponding process is indicated by an underline.
(1) Instead of steps S1 to S4 in FIG. 8, the processes of steps S21 and S22 are included.
(2) Steps S8A and S12A are included instead of steps S8 and S12 in FIG.
(3) After the process of step S13, the program end determination process (S14) of FIG. 11 is executed.
Hereinafter, the difference will be described in detail.

  In step S21 of FIG. 10, both the sense enable signal SSW and the verify determination switching signal VSW are set to 0V (ground voltage) to turn off both the MOS transistors N3 and N4, and for example, an ISPP (Increment Step Pulse Program) method or the like. A program sequence using a program pulse is executed. Next, in step S22, the setting process of the node voltage “JDG_G = Vth (N1) + Va” including steps S22-1 to S22-4 is performed as follows.

  In step S22-1, the node voltage SLS1 is set to the power supply voltage VDD as described above, the sense enable signal SSW is set to 0V (ground voltage), the MOS transistor N3 is turned off, and the node voltage SNS is set to VDD. Set to. Next, in step S22-2, the signal line voltage B is set to the power supply voltage VDD, the sense determination switching signal JDG_SW is set to the power supply voltage VDD to turn on the MOS transistor N2, and the sense enable signal SSW is set to the power supply voltage VDD. As a result, the MOS transistor N3 is turned on. At this time, the node voltages JDG_D and JDG_G are expressed by the following equations.

JDG_D = VDD−Vth (N3) (4)
JDG_G = VDD−Max (Vth (N2), Vth (N3)) (5)

  In step S22-3, the MOS transistor N3 is turned off by setting the sense enable signal SSW to 0 V (ground voltage). Next, in step S22-4, the signal line voltage B is set to a predetermined voltage Va (= 0V to 1.5V). At this time, a current flows from the node JDG_G to the signal line B through the MOS transistor N2, the node JDG_D, and the MOS transistor N1. Thereby, the node voltage JDG_G is expressed by the following equation.

JDG_G = JDG_D = Vth (N1) + Va (6)

  Next, as in FIG. 8, after the processing of steps S5, S6, and S7 is executed, the signal line voltage B is set to 0 V (ground voltage) in step S8A. Under this condition, the threshold value of the MOS transistor N1 viewed from the control gate is VDD−Va / α (α is called a coupling ratio, the capacitance between the control gate and the floating gate of the MOS transistor N1, and the floating gate. And a value not less than 0 and not more than 1 determined by the ratio of the capacitance between the substrates). Then, by setting the sense enable signal SSW to the power supply voltage VDD, the MOS transistor N3 is turned on to start data sensing. Further, after executing the processes of steps S9 to S13, a program end determination process S14 which is a subroutine is executed to end the data program and the verify process.

  FIG. 11 is a flowchart showing a program end determination process (S14) for program verification, which is a subroutine of FIG.

  In step S31 of FIG. 11, the node voltage SNS is set to a predetermined fixed voltage Vf. Next, in step S32, the verify determination switching signal VSW is set to a high level, and then in step S33, a determination process for ending the program sequence is executed, and the process returns to the original main routine. The MOS transistor N5 in FIG. 9 corresponds to the MOS transistor TJn in FIG. 2, FIG. 3 or FIG. 4, and the MOS transistors N4 and N1 correspond to the MOS transistor TJEn and operate together with the program end detection circuit 16 or 16A as described above. To determine whether the program sequence passes verification and ends, or whether the program sequence has not passed yet and the program should be continued.

FIG. 12 shows the data program and verify processing (when SLR1 = VDD and SLS1 = 0V when SLR1 = High is not programmed) executed by the sense circuit 30B and page buffer PBn of FIG. It is a flowchart to show. The data program and verify process of FIG. 12 have the same processing sequence as that of the data program and verify process of FIG. 10, but the following points differ from FIG. 10 depending on the state of the latch L1. In FIG. 12, processing different from the corresponding processing in FIG. 10 is underlined.
(1) Instead of the conditions of SLR1 = 0V and SLS1 = VDD, the conditions of SLR1 = VDD and SLS1 = 0V are satisfied.
(2) The process of step 22A is included instead of step S22. Here, only the following formulas are different from the formulas (4) and (5).
JDG_D = VDD−Vth (N1)
JDG_G = VDD−Max (Vth (N2), Vth (N1))
(3) Instead of step S10, the result of step S10A is obtained.
(4) Instead of step S11, the result of step S11A is obtained.
(5) Instead of step S13, the process of step S13A is executed. The process itself is exactly the same, but the results are different.
Hereinafter, the differences will be described in detail.

  FIG. 12 shows the case where the node voltage SLS1 is set to 0 V (ground voltage) instead of the power supply voltage VDD (FIG. 10), that is, when the program data is “not written” or the memory cell is already written. This corresponds to the case where the verification is passed. At this time, in steps S10A and S11A, unlike step S10 and S11, node voltage SLS1 is already at a low level, so that node voltage SLS1 is at a low level regardless of the voltage at node SNS or the on / off state of MOS transistor N1. Hold. That is, the node voltage SLS1 holds SLS1 = Low and SLR1 = High regardless of the data read from the memory cell. Next, in step S13A, the inverters 61 and 62 are brought into an operating state, and the latch L1 is determined to hold SLS1 = Low and SLR1 = High regardless of the data read from the memory cell. Further, in step S14, the program end determination process of FIG. 11 is executed to end the data program and the verify process.

  According to the above embodiment 2-1, the signal line B = VDD is set at the node SLS1 = 0V in step S22-2 in FIG. 12, but here, the MOS transistors N1 and N3 are turned on. , A so-called bus fight occurs in which different voltages collide with each other on the path on the node JDG_D. However, since the voltage is determined on the voltage side of each element, no malfunction occurs in the embodiment 2-1, and Even if the floating gate voltage JDG_G of the MOS transistor N1 is not set correctly due to the bus fight, in step S13A, the latch L1 holds SLS1 = Low and SLR1 = High regardless of the data read from the memory cell. No operational problems occur.

  Therefore, according to the embodiment 2-1, before sensing the data of the memory cell, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1. Since the voltage is set by adding Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

  10 to 12, the data program and the verify process according to the embodiment 2-1 using the sense circuit 30B and the page buffer PBn of the embodiment 2 in FIG. 9 have been described. However, the present invention is not limited to this. Instead, the following data program and verify processing according to Embodiment 2-2 in FIGS. 13 and 14 and data program and verify processing according to Embodiment 2-3 in FIGS. 15 and 16 may be used.

Embodiment 2-2.
FIG. 13 shows a data program and a verify process according to the embodiment 2-2 executed by the sense circuit 30B and the page buffer PBn of FIG. 9 (when programming with SLR1 = Low, when SLR1 = 0V and SLS1 = VDD). It is a flowchart to show. The data program and verify process according to the embodiment 2-2 in FIG. 13 are different from the data program and verify process in FIG. 10 in the following points.
(1) Instead of step S22, the process of step S22B is executed. Here, the processing of step S22B is the processing of steps S22-1, S22-2B, S22-3B, and S22-4 instead of steps S22-1, S22-2, S22-3, and S22-4 of FIG. 10. It is characterized by including. Hereinafter, the differences will be described in detail.

  In step S22B, a setting process of JDG_G = Vth (N1) + Va is performed. Here, in step S22-2B, the signal line B is set to the power supply voltage VDD, the signal line A is set to the power supply voltage VDD, and the sense determination switching signal JDG_SW is set to the power supply voltage VDD to turn on the MOS transistor N2. Then, the MOS transistor N4 is turned on by setting the verify determination switching signal VSW to the power supply voltage VDD. At this time, the node voltages JDG_D and JDG_G are expressed by the following equations.

JDG_D = VDD−Max (Vth (N4), Vth (N5)) (7)
JDG_G = VDD−Max (Vth (N2), Vth (N4), Vth (N5))
(8)

  Next, in step S22-3B, the verify determination switching signal VSW is set to 0 V (ground voltage) to turn off the MOS transistor N4. The subsequent processing is the same as in FIG.

FIG. 14 shows the data program and verify processing (when SLR1 = VDD and SLS1 = 0V when SLR1 = High is not programmed) executed by the sense circuit 30B and page buffer PBn of FIG. It is a flowchart to show. The data program and verify process of FIG. 14 differ from the data program and verify process of FIG. 12 in the following points.
(1) The process of step S22B is executed instead of step S22A of FIG. The process of step S22B executes the processes of steps S22-1, S22-2B, S22-3B, and S22-4, respectively, instead of steps S22-1, S22-2, S22-3, and S22-4 of FIG. To do.
The processing in FIG. 14 is the same as that in FIG. 13, and the processing results (S10A, S11A, S13A) are the same as in FIG.

  According to the above embodiment 2-2, the sense enable signal SSW = 0V (N3 = OFF) in step S22-1 of FIG. 14, and the signal line voltage B = VDD is set in step S22-2B. In this case, since the MOS transistor N3 is turned off, bus fight does not occur. Therefore, no malfunction occurs in the embodiment 2-2, and no operational problem occurs.

  Therefore, according to the embodiment 2-2, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1 before sensing the data of the memory cell. Since the voltage is set by adding Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

Embodiment 2-3.
FIG. 15 shows the data program and verify processing (when SLR1 = Low is programmed and SLR1 = 0V and SLS1 = VDD) according to the embodiment 2-3, which is executed by the sense circuit 30B and the page buffer PBn of FIG. It is a flowchart to show. The data program and the verify process according to the embodiment 2-3 of FIG. 15 are different from the data program and the verify process of FIG. 10 in the following points.
(1) The process of step S22D is executed instead of step S22. Here, the process of step S22D includes the processes of steps S22-1, S22-2D, and S22-4 instead of steps S22-1, S22-2, S22-3, and S22-4 of FIG. No processing corresponding to -3). Hereinafter, the differences will be described in detail.

  In step S22D of FIG. 15, the setting process of JDG_G = Vth (N1) + Va is performed as follows. First, in step S22-1, the sense enable signal SSW is set to 0V (ground voltage) to turn off the MOS transistor N3 and set the node voltage SNS to the power supply voltage VDD. Next, in step S22-2D, the signal line voltage B is set to the power supply voltage VDD, and the sense determination switching signal JDG_SW is set to the power supply voltage VDD to turn on the MOS transistor N2. At this time, a current flows from the signal line B to the node JDG_G through the MOS transistor N1, the node JDG_D, and the MOS transistor N2. Thereby, the node voltages JDG_D and JDG_G are expressed by the following equations.

JDG_D = Vdd−Vth (N1) (11)
JDG_G = Vdd-Max (Vth (N1), Vth (N2)) (12)

  Further, the process of step S22-4 is executed in the same manner as in FIG. 10, thereby setting JDG_G = Vth (N1) + Va.

FIG. 16 shows the data program and verify processing (when SLR1 = VDD and SLS1 = 0V when SLR1 = High is not programmed) executed by the sense circuit 30B and page buffer PBn of FIG. It is a flowchart to show. The data program and verify process according to the embodiment 2-3 of FIG. 16 differ from the data program and verify process of FIG. 12 in the following points.
(1) Instead of step S22A, the same step S22D as in FIG. 15 is executed. Here, the process of step S22D includes the processes of steps S22-1, S22-2D, and S22-4 instead of steps S22-1, S22-2, S22-3, and S22-4 of FIG. 12. Features. Other processes are the same as those in FIG.

  According to the above embodiment 2-3, the sense enable signal SSW = 0V (N3 = OFF) in step S22-1 in FIG. 14, and the signal line voltage B = VDD is set in step S22-2D. In step S21, the MOS transistor N4 is turned off. In this case, since the MOS transistors N3 and N4 are turned off, bus fight does not occur. Therefore, there is no malfunction in the embodiment 2-3, and no operational problem occurs.

  Therefore, according to the embodiment 2-3, before the data of the memory cell is sensed, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1. Since the voltage is set by adding Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

Embodiment 3. FIG.
FIG. 17 is a circuit diagram showing a configuration example of the sense circuit 30C and the page buffer PBn for the NAND flash EEPROM according to the third embodiment. The sense circuit 30C of FIG. 17 is a sense circuit for data program and verify processing (including a case where the node voltage SLR1 is programmed at a low level and a case where the node voltage SLR1 is not programmed at a high level). The following points are different from the sense circuit 30B according to the second embodiment.
(1) The feature is that the MOS transistor N4 is omitted and the connection of the drain of the MOS transistor N3 to the node SLR1 of the latch is changed. Here, signal line A (PBPUP) is connected to the drain of MOS transistor N5, the gate of MOS transistor N5 is connected to node SLS1, and the drain of MOS transistor N3 is connected to node SLR1. Note that a sense enable signal SSW and a sense determination switching signal JDG_SW from the control circuit 11 are used as control signals. Of course, it is needless to say that the same operation as in the present embodiment can be performed only by changing the drain connection of the MOS transistor N3 without omitting the MOS transistor N4.

Embodiment 3-1.
FIG. 18 shows the data program and verify process (when SLR1 = Low is programmed and SLR1 = 0V and SLS1 = VDD) according to the embodiment 3-1, executed by the sense circuit 30C and the page buffer PBn of FIG. It is a flowchart to show. The data program and verify process of FIG. 18 differ from the data program and verify process of FIG. 10 in the following points.
(1) Step S21A is executed after step S21 and before step S22E.
(2) The process of step S22E is executed instead of step S22 of FIG.
(3) Steps S9, S10E, S11E, S12A, S13E, and S14E are executed in place of steps S9 to S14 in FIG.
Hereinafter, the differences will be described in detail.

  In step S21A, the data stored in the latch L1 is inverted. As a result, the node SLR1 = VDD. Step S22E performs a setting process of JDG_G = Vth (N1) + Va. Even if the circuit is changed, the process is the same as step S22 of FIG. In step S21A, the node voltage SLR1 is set to the power supply voltage VDD as described above, and the operation conditions are the same as those in step S22 in FIG. 10. Therefore, the process in step S22E is the same as the process in step S22 in FIG. .

  In the embodiment 3-1 of FIG. 18, the processes of steps S5, S6, S7, and S8A are then executed in the same manner as in FIG. Further, in step S9, it is determined whether or not the node voltage SNS is equal to or higher than the threshold value of the MOS transistor N1 as viewed from the control gate and the program state is set. If YES, the process proceeds to step S10E. Proceed to In step S10E, at this time, the MOS transistors N1 and N3 are both on, current flows from the node voltage SLR1 to the signal line B via the MOS transistors N3 and N1, and the node voltage SLR1 becomes low level (0 V). Proceed to S12A. On the other hand, in step S11E, the node voltage JDG_G decreases due to the capacitive coupling of the transistor N1, the transistor N1 is turned off, no current flows from the node SLR1 to the signal line B via the MOS transistors N3 and N1, and the node voltage SLR1 is The power supply voltage VDD that is at the high level is held, and the process proceeds to step S12A. In step S12A, the MOS transistor N3 is turned off by setting the sense enable signal SSW to 0 V (ground voltage). In step S13E, the inverter 62 is set in the operating state, and then the inverter 61 is set in the operating state. At this time, the latch L1 holds the data read from the memory cell, and after executing the program end determination process which is the subroutine of FIG. 19 in step S14E, the data program and the verify process are ended.

  Here, since the sense circuit 30C in FIG. 17 does not have a switch transistor corresponding to the transistor N4 in FIG. 9, if the transistor N3 is turned on, a path connected from the signal line A to the node SLR1 via the transistors N5 and N3 can be made. However, in this operation, since the node SLR1 becomes VDD, the node SLS1 is turned off at 0V, that is, the gate of the transistor N5 is turned off at 0V, so that the operation is not affected.

  FIG. 19 is a flowchart showing a program end determination process (S14E) for program verification, which is a subroutine of FIG.

  In step S34 of FIG. 19, first, the data stored in the latch L1 is inverted. Next, in step S31, the node voltage SNS is set to a predetermined fixed voltage Vf. In step S33, the program end determination process is executed, and the process returns to the original routine.

FIG. 20 shows the data program and verify processing (when SLR1 = VDD and SLS1 = 0V when not programmed with SLR1 = High) executed by the sense circuit 30C and page buffer PBn of FIG. It is a flowchart to show. The data program and verify process of FIG. 20 differ from the data program and verify process of FIG. 12 in the following points.
(1) Step S21A is executed after step S21 and before step S22F.
(2) The process of step S22F is executed instead of step S22A of FIG.
(3) Steps S10F, S11F, S12A, S13F, and S14E are executed instead of steps S10A, S11A, S12A, S13A, and S14 in FIG.
Hereinafter, the differences will be described in detail.

  In step S21A, the data stored in the latch L1 is inverted. As a result, the node SLR1 becomes 0V. In step S22F, a setting process of JDG_G = Vth (N1) + Va is performed. Even if the circuit is changed, the process is the same as that in step S22 of FIG. In step S21A, the node voltage SLR1 is set to VDD (power supply voltage) as described above, and the operation conditions are the same as those in step S22A in FIG. 12. Therefore, the process in step S22F is the same as the process in step S22A in FIG. It is.

  In the embodiment 3-1 of FIG. 20, the processing of steps S5, S6, and S7 is then executed in the same manner as in FIG. Further, the sensing operation is started in step S8A and the data state of the memory cell is taken into the node SNS. However, in step S10F or S11F branched in step S9, the node SLR1 is already at 0V regardless of whether the transistor N1 is on or off. Therefore, the node voltage SLR1 is kept at a low level. Thereby, the node voltage SLR1 becomes independent from the state of the node SNS. Next, in step S12A, the sense enable signal SSW is set to 0 V (ground voltage) to turn off the MOS transistor N3. In step S13F, the inverter 62 is set to the operating state, and then the inverter 61 is set to the operating state. As a result, the node voltage SLS1 is restored to the high level state, and the latch L1 holds SLS1 = High and SLR1 = Low regardless of the data read from the memory cell. Further, in step S14E, the program end determination process of FIG. 19 is executed to end the data program and the verify process.

  According to the embodiment 3-1, the node SLR1 = 0V in step S21A of FIG. 20, the signal line B = VDD is set in step S22-2, and the MOS transistor N3 is turned on. Although the fight occurs, the voltage is fixed on the voltage side of each element, so that the malfunction does not occur in the embodiment 3-1, and the floating gate voltage JDG_G of the MOS transistor N1 is correctly set by the bus fight. Even if not, in step S13F, the latch L1 holds SLS1 = High and SLR1 = Low regardless of the data read from the memory cell, so that no operational problem occurs.

  In step S22F, S10F or S11F, since the node SLS1 is at a high level while the transistor N3 is on, the path of the signal line A-transistor N5-transistor N3-node SLR1 is connected, and at the same time, the signal line A-transistor N5- The path of the transistor N1-signal line B is also connected if the transistor N1 is ON. The setting of the signal line A does not invert as described above even if it slightly affects the low level of the node SLR1, but it is not preferable because it causes a current to flow. Therefore, the setting of the signal line A is the same as the setting of the floating or signal line B. It is desirable to make it.

  Therefore, according to the embodiment 3-1, before the data of the memory cell is sensed, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1. Since the voltage is set by adding Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

Embodiment 3-2.
FIG. 21 shows a data program and a verify process according to the embodiment 3-2 executed by the sense circuit 30C and the page buffer PBn of FIG. 17 (when SLR1 = Low and SLR1 = 0V and SLS1 = VDD). It is a flowchart to show. The data program and verify process of FIG. 21 differ from the data program and verify process of FIG. 10 in the following points.
(1) The process of step S22G is executed instead of step S22 of FIG.
(2) Steps S9, S10E, S11E, S12A, S13E, and S14E are executed instead of steps S9 to S14 in FIG.
Hereinafter, step S22G of the difference will be described in detail. Since steps S10E to S14E are the same as those described above (FIG. 18), description thereof is omitted.

  Step S22G performs the setting process of JDG_G = Vth (N1) + Va. Compared to step S22 in FIG. 10, step S22-1 in FIG. 10 is the same, but steps S22-2, S22-3 in FIG. Instead of S22-4, steps S22-2G, S22-3G, and S22-4G are executed. In step S22-2G, the signal line voltage B is set to the power supply voltage VDD, the sense determination switching signal JDG_SW is applied to the power supply voltage VDD, the MOS transistor N2 is turned on, and the signal line voltage A is further set to the power supply voltage VDD. Set to. At this time, the node voltages JDG_D and JDG_G are expressed by the following equations.

JDG_D = VDD−Vth (N5) (13)
JDG_G = VDD−Max (Vth (N2), Vth (N5)) (14)

  Next, when the data stored in the latch L1 is inverted in step S22-3G and the node SLS1 is set to a low level, the transistor N5 is turned off. Further, in step S22-4G, the signal line A is set in a floating state, and the signal line voltage B is set to a predetermined voltage Va (= 0V to 1.5V). At this time, a current flows from the node JDG_G to the signal line B through the MOS transistor N2, the node JDG_D, and the MOS transistor N1. Thereby, the node voltage JDG_G is expressed by the following equation.

JDG_G = JDG_D = Vth (N1) + Va (15)

  Next, the processing after step S5 is executed in the same manner as in FIG.

FIG. 22 shows the data program and verify processing (when SLR1 = VDD and SLS1 = 0V when SLR1 = High is not programmed), which is executed by the sense circuit 30C and the page buffer PBn of FIG. It is a flowchart to show. The data program and verify process of FIG. 22 differ from the data program and verify process of FIG. 12 in the following points.
(1) The process of step S22H is executed instead of step S22A of FIG.
(2) Steps S10F to S13F and S14E are executed instead of steps S10A to S13A and S14 in FIG.
Hereinafter, step S22H which is a difference will be described in detail. In addition, since the process of step S10F-S14E is the same as the above-mentioned, description is abbreviate | omitted.

  In step S22H, JDG_G = Vth (N1) + Va is set, but steps S22-1, S22-2G, S22-3G, and S22-4G are executed as compared with step S22A in FIG. The processing in the first step S22-1 is the same as that in FIG. Next, in step S22-2G, the signal line B is set to the power supply voltage VDD, the sense determination switching signal JDG_SW is set to the power supply voltage VDD to turn on the MOS transistor N2, and the signal line A is set to the power supply voltage VDD. . Since the transistor N3 is off and the node SLS1 is at a low level, the transistor N5 is also off. At this time, the node voltages JDG_D and JDG_G are expressed by the following equations.

JDG_D = VDD−Vth (N1) (16)
JDG_G = VDD−Max (Vth (N2), Vth (N1)) (17)

  In step S22-3G, the data stored in the latch L1 is inverted. The node SLR1 = 0V and SLS1 = VDD. Next, in step S22-4G, the signal line A is set in a floating state, and the signal line B is set to a predetermined voltage Va (for example, 0 V to 1.5 V). At this time, a current flows from the node JDG_G to the signal line B through the MOS transistor N2, the node JDG_D, and the MOS transistor N1. Thereby, the node voltages JDG_D and JDG_G are set as follows.

JDG_G = JDG_D = Vth (N1) + Va (18)

  According to the above embodiment 3-2, the node SLS1 = 0V in step S22-1 in FIG. 22 and the signal line B = VDD is set in step S22-2G. Here, the MOS transistor N3 is Since it is off, bus fight does not occur, and the voltage is fixed on the voltage side of each element. Therefore, no malfunction occurs in the embodiment 3-2, and no operational problem occurs.

  Therefore, according to the embodiment 3-2, the node voltage JDG_G of the floating gate of the MOS transistor N1 is set to the threshold voltage viewed from the floating gate of the MOS transistor N1 before the data sensing of the memory cell. Since the voltage is set by adding Va, the data voltage of the memory cell can be sensed by compensating for variations in the threshold value of the MOS transistor of the sense amplifier. As a result, the data voltage read from the memory cell can be sensed more accurately than in the prior art.

Embodiment 4 FIG.
FIG. 23 is a circuit diagram showing a configuration example of the sense circuit 30D and the page buffer PBn for the NAND flash EEPROM according to the fourth embodiment. The sense circuit 30D according to the fourth embodiment is a modification of the sense circuit 30B according to the second embodiment in FIG. 9, and the N-channel MOS transistor N5 is configured by a P-channel MOS transistor P5, and the gate of the MOS transistor P5 is a node. It is characterized by being connected to SLR1. The data program and the verify process according to the fourth embodiment can be executed in the same manner as in the embodiments 2-1 to 2-3, and have the same effects. Needless to say, the same modification can be made in the sense circuit 30C according to the third embodiment shown in FIG.

Modified example.
FIG. 24 is a circuit diagram showing a configuration example of a part of a sense circuit 30E according to a modification. In the first to fourth embodiments described above, the MOS transistor N1 is configured as a stacked gate type MOS transistor. However, the present invention is not limited to this, and the capacitor C1 is used as the gate as shown in the modification of FIG. A connected N-channel MOS transistor N1A may be used. That is, the floating gate type MOS transistor N1 or the MOS transistor N1A having the capacitor C1 constitutes a stacked gate type control element. Here, the capacitor C1 is preferably an ONO type capacitor in which SiO ₂ , SiN, and SiO ₂ are stacked in this order.

  In FIG. 24, the node SNS is connected to the gate of the MOS transistor N1A via the capacitor C1, and the gate is connected to the node JDG_G. The drain of the MOS transistor N1A is connected to the node JDG_D, and the source of the MOS transistor N1A is connected to the signal line B.

  In the above embodiments, a flash memory such as a NAND flash EEPROM has been described. However, the present invention is not limited to this and can be applied to a nonvolatile memory device such as a NOR flash memory.

  Furthermore, in the above embodiment, the sense circuits 30A to 30D are configured by the MOS transistors N1 to N3 and the like, but the present invention is not limited to this, and may be configured by a switch element that is on / off controlled from an external control signal. Good.

  As described above in detail, according to the sense circuit for a nonvolatile memory device according to the present invention, the pitch of the memory cells is reduced as the nonvolatile memory device such as a NAND flash memory is miniaturized. Accordingly, even if the transistor size of the peripheral circuit is reduced, the data value can be sensed more accurately than in the prior art.

10: Memory cell array,
11 ... control circuit,
12 ... row decoder,
13. High voltage generation circuit,
14: Data rewriting and reading circuit (page buffer),
14a, 14b ... latch circuit,
15 ... column decoder,
16 ... Program end detection circuit,
17 ... Command register,
18 ... Address register,
19 ... Operation logic controller,
21, 22 ... MOS transistors,
23 ... Inverter,
24, 25 ... MOS transistors,
26: Comparator,
27. Program end determination circuit,
28: Reference current generating circuit,
29-n... Program end determination unit,
30A-30D ... sense circuit,
50: Data input / output buffer,
51: Data input / output terminal,
52. Data signal line,
61, 62 ... inverter,
71-90 ... MOS transistors,
A, B ... Output line,
L1, L2 ... Latch,
N1-N5, N1A, P5 ... MOS transistors,
PBn: Page buffer.

Claims (10)

In a sense circuit that senses the data provided in a page buffer including a latch that temporarily stores data when data is written to or read from a memory cell of a nonvolatile memory device,
A first switch element and a stacked gate type control element inserted between the first signal line and the first terminal of the latch and connected in series;
A second switch element connected between the first switch element and the stacked gate type control element;
A first terminal of the latch is connected to a first terminal of the first switch element;
A second terminal of the first switch element is connected to a first terminal of the stacked gate control element and a first terminal of the second switch element;
A second terminal of the second switch element is connected to a floating gate of the stacked gate type control element;
A second terminal of the stacked gate type control element is connected to the first signal line;
The first switch element is turned on or off by a sense enable signal,
The second switch element is turned on or off by a sense determination switching signal,
The stacked gate type control element is controlled by a signal voltage of a sense node of the sense circuit connected to the second terminal of the latch,
Prior to the start of sensing when the first switch element is turned on by the sense enable signal, the voltage of the floating gate of the stacked gate type control element is a threshold voltage viewed from the floating node of the stacked gate type control element. Is set to a voltage value obtained by adding a predetermined voltage to the data, and the data of the memory cell is sensed and stored in the latch .
The sense circuit further includes third and fourth switch elements inserted between the second signal line and the second terminal of the first switch element and connected in series with each other,
The first terminal of the third switch element is connected to the second signal line, the second terminal of the third switch element is connected to the first terminal of the fourth switch element, and The second terminal of the fourth switch element is connected to the second terminal of the first switch element,
The third switch element is turned on or off by the voltage of the first terminal of the latch or the second terminal of the latch,
The fourth switch element is turned on or off by a predetermined verify judgment switching signal,
When the sense circuit senses data for verify read after writing the data, the voltage setting of the floating gate of the stacked gate type control element is set to the first terminal of the latch, or the first or Executed by charging from the second signal line;
The sense circuit
(1) The second switch element is turned off by the sense determination switching signal,
(2) The voltage read from the memory cell is transferred to the gate of the stacked gate type control element,
(3) Set the output of the latch to a high impedance state,
(4) The first switch element is turned on by the sense enable signal to start sensing,
(5) turning off the first switch element by the sense enable signal;
(6) The latch is activated and data read from the memory cell or predetermined data is held in the latch,
(7) A sense circuit characterized in that an end determination process at the time of data writing is performed by performing a verify operation with the gate of the stacked gate type control element set to a predetermined fixed voltage . In a sense circuit that senses the data provided in a page buffer including a latch that temporarily stores data when data is written to or read from a memory cell of a nonvolatile memory device,
A first switch element and a stacked gate type control element inserted between the first signal line and the first terminal of the latch and connected in series;
A second switch element connected between the first switch element and the stacked gate type control element;
A second terminal of the latch is connected to a first terminal of the first switch element;
A second terminal of the first switch element is connected to a first terminal of the stacked gate control element and a first terminal of the second switch element;
A second terminal of the second switch element is connected to a floating gate of the stacked gate type control element;
A second terminal of the stacked gate type control element is connected to the first signal line;
The first switch element is turned on or off by a sense enable signal,
The second switch element is turned on or off by a sense determination switching signal,
The stacked gate type control element is controlled by a signal voltage of a sense node of the sense circuit connected to the second terminal of the latch,
Prior to the start of sensing when the first switch element is turned on by the sense enable signal, the voltage of the floating gate of the stacked gate type control element is a threshold voltage viewed from the floating node of the stacked gate type control element. Is set to a voltage value obtained by adding a predetermined voltage to the data, and the data of the memory cell is sensed and stored in the latch .
The sense circuit further includes a fifth switch element connected between the second signal line and the second terminal of the first switch element,
The fifth switch element is turned on or off by the voltage of the first terminal of the latch or the second terminal of the latch;
When the sense circuit senses data for verify read after the data is written, the voltage setting of the floating gate of the stacked gate type control element is performed after inverting the data stored in the latch. Executed by charging from a second terminal of the latch or the first signal line;
The sense circuit
(1) The second switch element is turned off by the sense determination switching signal,
(2) The voltage read from the memory cell is transferred to the gate of the stacked gate type control element,
(3) Set the output of the latch to a high impedance state,
(4) The first switch element is turned on by the sense enable signal to start sensing,
(5) turning off the first switch element by the sense enable signal;
(6) The latch is activated and data read from the memory cell or predetermined data is held in the latch,
(7) The data held by the latch is inverted, the gate of the stacked gate type control element is set to a predetermined fixed voltage, and a verify operation is performed to perform an end determination process at the time of data writing. A sense circuit characterized by that. The stacked gate type control element is
(1) stacked-gate MOS transistors, or (2) a sense circuit according to claim 1 or 2, wherein the capacitor is a MOS transistor having a gate connected. 4. The sense circuit according to claim 3, wherein the stacked gate type MOS transistor has a structure similar to that of the stacked gate type MOS transistor among the MOS transistors of the memory cells of the nonvolatile memory device. The predetermined voltage is a sense circuit according to any one of claims 1-4, characterized in that the one voltage value among the range of 0V to 1.5V. The third switch element is an N-channel MOS transistor,
It said third sensing circuit of claim 1, wherein the switch element, characterized in that it is turned on or off by the voltage of the first terminal of the latch. The third switch element is a P-channel MOS transistor,
It said third sensing circuit of claim 1, wherein the switch element, characterized in that it is turned on or off by the voltage of the second terminal of the latch. The fifth switch element is an N-channel MOS transistor,
3. The sense circuit according to claim 2, wherein the fifth switch element is turned on or off by the voltage of the first terminal of the latch. The fifth switch element is a P-channel MOS transistor,
3. The sense circuit according to claim 2, wherein the fifth switch element is turned on or off by the voltage of the second terminal of the latch. Nonvolatile memory device characterized by comprising a sense circuit according to any one of claims 1-9.

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