JP5305620B2 - Non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory the high integration of which can be achieved. <P>SOLUTION: The nonvolatile memory has a memory cell array in which a plurality of memory cells are arranged in a matrix corresponding to rows and columns, a plurality of first word lines, a plurality of second word lines, and a plurality of bit lines, where each of the plurality of memory cells has a first memory transistor and a second memory transistor which are connected in series, a gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the first word line, one of source and drain regions of the first memory transistor is connected to the first bit line, the other of source and drain regions of the second memory transistor is connected to the second bit line, and the first bit line and the second bit line are common to the memory cells in rows adjacent to rows having respective memory cells. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically erasable and erasable semiconductor nonvolatile memory (EEPROM (Electrically Erasable and Programmable Read Only Memory)).

  In recent years, multi-function and high-performance small semiconductor devices typified by portable devices such as portable computers and mobile phones are rapidly spreading. Along with this, a semiconductor nonvolatile memory has attracted attention as a memory constituting a semiconductor device. Although the semiconductor nonvolatile memory is inferior in storage capacity as compared with a magnetic disk, it has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like. Recently, those having sufficient performance in the number of rewrites and data retention time, which have been problems of the semiconductor nonvolatile memory, have been developed, and the movement to use the semiconductor nonvolatile memory as a substitute for the magnetic disk has increased. It was.

  Semiconductor nonvolatile memories are roughly classified into two types: full-function EEPROMs and flash memories. The full function EEPROM is a semiconductor non-volatile memory capable of erasing bit by bit, and can perform writing, reading and erasing operations every bit. Although the degree of integration and cost are inferior to those of flash memories, they have high functionality. On the other hand, a flash memory is a semiconductor nonvolatile memory that performs batch erase of the entire memory or erase in units of blocks of the memory, and realizes high integration density and low cost at the expense of erase operation for each bit.

  In a flash memory, all data must be erased in order to rewrite one bit of data. Therefore, the power consumption is larger than that of a full-function EEPROM, and the reliability is lowered because rewriting is performed even in a memory cell that does not require rewriting. Of course, the flash memory cannot be used for applications that require a 1-bit erase operation.

  Here, a full-function EEPROM is taken up as a conventional semiconductor nonvolatile memory, and a circuit diagram, a cross-sectional view of a memory cell, and a driving method will be described.

  FIG. 12 shows a circuit diagram of a conventional full-function EEPROM. The full function EEPROM shown in FIG. 12 includes a memory cell array 405 in which a plurality of memory cells (1, 1) to (m, n) are arranged in a matrix of m vertical × n horizontal, an X address decoder 401, and a Y address. The decoder 402 and other peripheral circuits 403 and 404 are configured.

  Each memory cell (considering memory cell (i, j) as a representative) (i is an integer of 1 to m and j is an integer of 1 to n) is composed of an n-channel memory transistor Tr1 and an n-channel memory transistor. A selection transistor Tr2 is included, and these two transistors are connected in series. The source electrode and control gate electrode of the memory transistor Tr1 are connected to the source line Si and the word line Wj, respectively, and the drain electrode and gate electrode of the selection transistor Tr2 are connected to the bit line Bi and the selection line Vj, respectively. . The bit lines B1 to Bn are connected to the Y address decoder 402, the word lines W1 to Wm and the selection lines V1 to Vm are connected to the X address decoder 401, respectively, and the source lines S1 to Sn all share a predetermined potential Vs. Is given.

  When the memory transistor included in each memory cell records 1-bit data, the full-function EEPROM shown in FIG. 12 has a storage capacity of m × n bits.

  However, the full-function EEPROM has a problem that the memory cell storing 1-bit data is composed of two transistors, that is, a memory transistor and a selection transistor, so that the memory cell area is large and the integration density is low. This hinders miniaturization and cost reduction of the full-function EEPROM.

In order to solve the above problem, a structure that improves integration density by providing two memory transistors instead of a selection transistor in a memory cell that stores 1-bit data has been proposed (for example, Patent Documents). 1). In recent years, memory elements have been used in various fields, and there has been a demand for a small-capacity, large-capacity non-volatile memory.
JP 2002-43447 A

  It is an object of the present invention to provide a nonvolatile memory that can realize higher integration.

  The nonvolatile memory of the present invention includes a memory cell array in which a plurality of memory cells are arranged in a matrix corresponding to the row direction and the column direction, a plurality of first word lines, a plurality of second word lines, Each of the plurality of memory cells has a first memory transistor and a second memory transistor connected in series, and the gate electrode of the first memory transistor is the first memory transistor. Connected to the word line, the gate electrode of the second memory transistor is connected to the second word line, one of the source region or the drain region of the first memory transistor is connected to the first bit line, The other of the source region or the drain region of the memory transistor is connected to the second bit line, and each of the first bit line and the second bit line is adjacent to the column in which the memory cell is provided. It is characterized in that provided in common to the memory cell. Note that the bit line is provided in common with the memory cell in the column adjacent to the column in which the memory cell is provided, that the memory cell in a certain column (j column) and the column adjacent to it ((j + 1) column). One bit line is arranged between the memory cell and the bit line is electrically connected to both the memory transistor provided in the memory cell in the j column and the memory transistor provided in the (j + 1) column. The state that is.

  The nonvolatile memory of the present invention includes a memory cell array in which a plurality of memory cells are arranged in a matrix corresponding to the row direction and the column direction, a plurality of first word lines, and a plurality of second word lines. And a plurality of bit lines including a first bit line and a second bit line provided adjacent to each other, and each of the plurality of memory cells includes a first memory transistor and a first memory transistor connected in series. And the gate electrode of the first memory transistor is connected to the first word line, the gate electrode of the second memory transistor is connected to the second word line, and the first memory transistor One of the source region and the drain region of the second memory transistor is connected to the first bit line, the other of the source region and the drain region of the second memory transistor is connected to the second bit line, and the first bit line is ( -1) One of the source region or drain region of the second memory transistor provided in the memory cell in the column and one of the source region or drain region of the first memory transistor provided in the memory cell in the j column And the second bit line is connected to one of the source region and the drain region of the second memory transistor provided in the memory cell in the j column and the first bit line provided in the memory cell in the (j + 1) column. The memory transistor is connected to one of a source region and a drain region.

  In addition, the nonvolatile memory of the present invention is capable of writing for each bit and erasing for each bit. Further, writing and erasing to the memory cell can be performed by a tunnel current.

  In the nonvolatile memory of the present invention, the wiring in the column direction connected to the memory cell is called a bit line. The nonvolatile memory of the present invention does not have a source line, and the source region of the transistor connected to the source line in the conventional full function EEPROM is connected to the adjacent bit line.

  The nonvolatile memory of the present invention has a high integration density by configuring a memory cell with two memory transistors and removing a conventional source line and connecting it to an adjacent bit line instead of the conventional source line. It is possible to provide a full-function EEPROM that is small and low-cost.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
In this embodiment mode, a circuit diagram of a nonvolatile memory of the present invention, a driving method, and a cross-sectional structure of a memory cell will be described.

  FIG. 1 shows a circuit of a nonvolatile memory shown in this embodiment mode. Here, as an example, a circuit diagram of an m × n (m and n are integers of 1 or more) bit nonvolatile memory is shown.

  The nonvolatile memory described in this embodiment includes a memory cell array 105 in which m × n memory cells (1, 1) to (m, n) are arranged in a matrix of m vertical × n horizontal, the memory An X address decoder 101 and a Y address decoder 102 which are driving circuits of the cell array 105 and other peripheral circuits 103 and 104 are configured.

  Each memory cell (considering memory cell (i, j) as a representative) (i is an integer of 1 to m and j is an integer of 1 to n) has two memory transistors Tr1 and Tr2, respectively. These two memory transistors Tr1 and Tr2 are connected in series. The gate electrode of the memory transistor Tr1 is connected to the first word line Waj, and the gate electrode of the memory transistor Tr2 is connected to the second word line Wbj.

  Further, in the nonvolatile memory described in this embodiment, wirings in which memory cells adjacent in a row function as bit lines are shared. That is, in a certain row (for example, i row), the source electrode of the memory transistor Tr1 in the j column and the drain electrode of the memory transistor Tr2 in the (j−1) column are connected to the same wiring (jth bit line), The source electrode of the memory transistor Tr1 in the (j + 1) th column and the drain electrode of the memory transistor Tr2 in the jth column are connected to the same wiring ((j + 1) th bit line).

  By providing wirings in common in adjacent memory cells, the memory transistors can be integrated with higher density, so that the non-volatile memory can be reduced in size and capacity.

  When each memory transistor stores 1-bit data, the nonvolatile memory of this embodiment has a storage capacity of m × n × 2 bits. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary.

  The memory transistors Tr1 and Tr2 may be either n-channel or p-channel conductivity type transistors, but in this embodiment, an n-channel transistor is shown. In this embodiment, a case where one memory transistor stores 1-bit data is considered. However, one memory transistor can store data of 2 bits or more by a multi-value technique. When one memory transistor stores k bits (k is an integer equal to or greater than 1), the storage capacity of the nonvolatile memory according to the present embodiment is m × n × 2 × k bits.

  In addition, the memory transistor included in the nonvolatile memory may be provided over any of a silicon substrate, an SOI substrate, and a substrate having an insulating surface. Further, by forming the memory cell drive circuit (in this embodiment, the X address decoder 101 and the Y address decoder 102) and the other peripheral circuits 103 and 104 over the same substrate as the memory transistor, a small nonvolatile A memory can be realized.

  In particular, when the nonvolatile memory described in this embodiment is formed using a memory TFT (TFT-type memory element) formed over a substrate having an insulating surface, it is integrally formed with any semiconductor device component including the TFT. Therefore, it is possible to provide a small-sized semiconductor device that is multifunctional or highly functional.

  Next, an example of a memory cell constituting the nonvolatile memory of this embodiment will be described with reference to the drawings. 2 is a top view of the memory cell, FIG. 3A is a cross-sectional view taken along line AB in FIG. 2, and FIG. 3B is a cross-sectional view taken along line CD in FIG. ing.

  In the nonvolatile memory described in this embodiment, two memory transistors 212 and 213 included in the memory cell 211 are formed over a substrate 201 (see FIG. 3A). The memory transistor 212 includes a semiconductor film 203, a first insulating film 204a, a first conductive film 205a, a second insulating film 206a, and a second conductive film 207a which are formed over the substrate 201 with the insulating film 202 interposed therebetween. It is configured. In the memory transistor 212, the semiconductor film 203 includes source or drain regions 203c and 203d and a channel formation region 203a.

  Similarly, the memory transistor 213 includes a semiconductor film 203, a first insulating film 204b, a first conductive film 205b, a second insulating film 206b, and a second conductive film which are formed over the substrate 201 with the insulating film 202 interposed therebetween. 207b. In the memory transistor 213, the semiconductor film 203 includes source or drain regions 203c and 203e and a channel formation region 203b.

  In the row direction (direction parallel to CD), conductive films 210a to 210d that can function as bit lines are provided between the semiconductor films 203 and 223 provided in adjacent memory cells, respectively. The conductive films 210a to 210d are electrically connected to adjacent semiconductor films in the row direction. Specifically, a conductive film 210b is provided between the semiconductor film 203 of the memory cell 211 and the semiconductor film 223 of the memory cell 221, and the conductive film 210b includes a source region or a drain region 203e of the semiconductor film 203 and The source region or the drain region of the semiconductor film 223 is electrically connected. That is, the conductive film 210 b is provided in common between the memory cell 211 and the memory cell 221.

  As described above, by providing the wiring connected to the semiconductor film of the memory cell adjacent in the row direction in common, the semiconductor film can be integrated at a higher density than when the wiring is provided for each semiconductor film. (See FIGS. 2 and 3B). For example, the area can be reduced by the distance between the source line width and the source line-bit line for each column as compared with the case where independent bit lines and source lines are provided for each column. The wiring width is, for example, about 0.1 μm to 2 μm, the distance between the wirings is, for example, about 0.1 μm to 2 μm, and the width can be reduced by about 0.2 μm to 4 μm for each column.

  Note that the second conductive film 207a in the memory transistor 212 corresponds to the first word line Wa, and the second conductive film 207b in the memory transistor 213 corresponds to the second word line Wb. In the memory transistors 212 and 213, the first insulating films 204a and 204b can function as tunnel insulating films. The first conductive films 205a and 205b can function as floating gate electrodes. Further, the second insulating films 206a and 206b can function as control insulating films. In addition, the second conductive films 207a and 207b can function as control gate electrodes.

  In addition, insulating films 208 and 209 are formed so as to cover the memory transistors 212 and 213, and a conductive film 210a electrically connected to the source or drain regions 203c and 203e of the semiconductor film 203 over the insulating film 209. 210b is provided.

  Note that although an example of a thin film transistor type memory transistor is shown here by providing a semiconductor active layer formed of an island-shaped semiconductor film over the substrate 201, the present invention is not limited thereto. For example, a memory transistor can be provided using a semiconductor active region formed on a silicon substrate or a semiconductor active layer on an SOI (Silicon on Insulator) substrate.

  Although the example in which the conductive films 210a to 210d are provided so as not to overlap with the semiconductor film is shown here, the conductive films 210a to 210d may be provided so as to overlap with the semiconductor film. In this case, the memory cell area can be reduced by reducing the interval between adjacent semiconductor films in the row direction, and the memory cells can be integrated at a higher density.

  In addition, the memory transistor 212 includes a region (overlap region) where the source or drain regions 203c and 203d partially overlap with the first conductive film 205a with the first insulating film 204a and the like interposed therebetween. The overlap region is a region for allowing a tunnel current to flow between the first conductive film that can function as a floating gate electrode and the source region or the drain region. Therefore, in the case where a tunnel current flows between the source region and the first conductive film 205a, it is preferable to form an overlap region between the source region and the first conductive film 205a. In the case where a tunnel current flows between the drain region and the first conductive film 205a, an overlap region is preferably formed between the drain region and the first conductive film 205a. In accordance with the driving method of the nonvolatile memory, an overlap region may be provided in one of the source region and the drain region of the memory transistors 212 and 213, or the memory transistors 212 and 213 may be provided as shown in FIG. You may provide in both a source region or a drain region. In particular, when a tunnel current is passed between the substrate (body) and the first conductive film 205a, the overlap region may not be provided.

  The nonvolatile memory described in this embodiment is characterized in that a memory transistor having a memory function is used as a selection transistor and a wiring provided between adjacent memory cells in the row direction is shared as compared with a conventional full-function EEPROM. It is to become. As a result, 2-bit data can be stored in one memory cell, and data can be written, read and erased completely in 1-bit units.

  The writing and erasing operations of the nonvolatile memory described in this embodiment mode are characterized by using a tunnel current.

  Hereinafter, taking the memory cell (i, j) as an example, the writing, reading and erasing operation methods in the memory transistors Tr1 and Tr2 will be described. In the following description, writing data refers to injecting electrons into the floating gate electrode of the memory transistor, and erasing data refers to discharging electrons accumulated in the floating gate electrode of the memory transistor. .

  First, a case where data is written to the memory transistor Tr1 in the memory cell (i, j) will be described.

  When writing data (injecting electrons) to the memory transistor Tr1, for example, the bit line Bj is −10V, the other bit lines Bk (k = 1 to j−1, j + 1 to n + 1) are 0V, One word line Wai is 10V, the other first word lines Wak (k = 1 to i-1, i + 1 to m) are 0V, and all the second word lines Wbk (k = 1 to m) are -10V. (See FIG. 4A).

  As a result, 10 V is applied to the gate electrode of Tr1 in the memory cell (i, j), and −10 V is applied to the source region or drain region connected to the bit line Bj, resulting in a high potential difference. Then, electrons are injected from the channel region into the floating gate electrode by the tunnel current, and writing is performed.

  Although there is a potential difference of 10 V between the bit line Bj and the other bit lines Bk (k = 1 to j−1, j + 1 to n + 1), all the second word lines Wbk (k = 1 to m) are connected. By setting the voltage to −10 V, the memory transistor Tr2 is turned off in all the memory cells, and almost no current flows between the bit lines. In addition, even if a potential difference occurs in the memory transistors other than the memory transistor Tr1 of the memory cell (i, j), only a potential difference of about 10 V is generated, so that writing to other memory transistors is not erroneously performed.

  Next, a case where data is written to the memory transistor Tr2 in the memory cell (i, j) will be described.

  When writing data (injecting electrons) into the memory transistor Tr2, for example, the bit line B (j + 1) is −10V, the other bit lines Bk (k = 1 to j, j + 2 to n + 1) are 0V, One word line Wak (k = 1 to m) is −10 V, the second word line Wbi in the i-th row is 10 V, and the other second word lines Wbk (k = 1 to i−1, i + 1 to m) It is set to 0 V (see FIG. 4B).

  As a result, 10 V is applied to the gate electrode of Tr2 in the memory cell (i, j), and −10 V is applied to the source region or drain region connected to the bit line B (j + 1), resulting in a high potential difference. Then, electrons are injected from the channel region into the floating gate electrode by the tunnel current, and writing is performed.

  Although there is a potential difference of 10 V between the bit line B (j + 1) and the other bit lines Bk (k = 1 to j, j + 2 to n + 1), all the first word lines Wak (k = 1 to m) By setting -10V to -10V, the memory transistor Tr1 is turned off in all the memory cells, and almost no current flows between the bit lines. In addition, even if a potential difference occurs in the memory transistors other than the memory transistor Tr2 of the memory cell (i, j), a potential difference of about 10 V is not generated at all, and therefore writing to other memory transistors is not erroneously performed.

  Next, data erasure will be described. First, a case where data is erased from the memory transistor Tr1 in the memory cell (i, j) will be described.

  When erasing data (discharging electrons) from the memory transistor Tr1, for example, the bit line Bj is + 10V, the other bit lines Bk (k = 1 to j−1, j + 1 to n + 1) are 0V, and the first in the i-th row Word line Wai of −10V, the other first word lines Wak (k = 1 to i−1, i + 1 to m + 1) are set to 0V, and all the second word lines Wbk (k = 1 to m) are set to 0V. (See FIG. 5A).

  As a result, −10 V is applied to the gate electrode of Tr1 in the memory cell (i, j), and 10 V is applied to the source region or drain region connected to the bit line Bj, resulting in a high potential difference. Then, a tunnel current flows in the overlap region, and electrons are emitted from the floating gate to the source region or the drain region. That is, erasure is performed.

  Although there is a potential difference of 10 V between the bit line Bj and the other bit lines Bk (k = 1 to j−1, j + 1 to n + 1), all the second word lines Wbk (k = 1 to m) are connected. By setting the voltage to 0 V, the memory transistor Tr2 is turned off in all the memory cells, and almost no current flows between the bit lines. Further, even if a potential difference occurs in the memory transistors other than Tr1 in the memory cell (i, j), only a potential difference of about 10 V is generated, so that the other memory transistors are not erroneously erased.

  When erasing data (discharging electrons) from the memory transistor Tr2, for example, the bit line B (j + 1) is + 10V, the other bit lines Bk (k = 1 to j, j + 2 to n + 1) are 0V, and all the first Word line Wak (k = 1 to m) is 0V, second word line Wbi in row i is −10V, and other second word lines Wbk (k = 1 to i−1, i + 1 to m + 1) are 0V. (See FIG. 5B).

  As a result, −10 V is applied to the gate electrode of Tr2 in the memory cell (i, j), and 10 V is applied to the source region or drain region connected to the bit line B (j + 1), resulting in a high potential difference. Then, a tunnel current flows in the overlap region, and electrons are emitted from the floating gate to the source region or the drain region. That is, erasure is performed.

  Although there is a potential difference of 10 V between the bit line B (j + 1) and the other bit lines Bk (k = 1 to j, j + 2 to n + 1), all the first word lines Wak (k = 1 to m) By setting 0 to 0 V, the memory transistor Tr1 is turned off in all the memory cells, and almost no current flows between the bit lines. Further, even if a potential difference occurs in the memory transistors other than Tr2 of the memory cell (i, j), only a potential difference of about 10 V is generated, so that the other memory transistors are not erroneously erased.

  In addition, in the nonvolatile memory described in this embodiment, writing or erasing of a plurality of memory transistors can be performed at the same time. For example, a horizontal row of memory transistors Tr 1, a horizontal row of memory transistors Tr 2, a vertical row of memory transistors Tr 1, a vertical row of memory transistors Tr 2, any one of them, and the like are possible. Also, the entire memory transistor Tr1 and Tr2 in the horizontal row, the entire memory transistor Tr1 and Tr2 in the horizontal row, the memory transistor Tr1 in the horizontal row, the memory transistor Tr2 in the horizontal row, the memory transistor Tr1 in the vertical row, It is possible to simultaneously write or erase a plurality of columns of memory transistors Tr2 and Tr1 of all memory cells.

  For example, in the case where writing to the transistor Tr1 is performed simultaneously in the i-th memory cell (i, k) (k = 1 to n + 1), all the bit lines Bk (k = 1 to n + 1) are set to −10V, the first The word line Wai is set to 10V, the other first word lines Wak (k = 1 to i-1, i + 1 to m) are set to 0V, and all the second word lines Wbk (k = 1 to m) are set to -10V. That's fine. When erasing the transistor Tr2 is simultaneously performed in the memory cells (k, j) (k = 1 to m) in the j column, the bit line B (j + 1) is set to 10V and the other bit lines Bk (k = 1 to j). , J + 2 to n + 1) may be set to 0V, all the first word lines Wak (k = 1 to m) may be set to 0V, and all the second word lines Wbk (k = 1 to m) may be set to −10V.

  Next, a data read operation will be described with reference to FIG. First, a case where data is read from the memory transistor Tr1 in the memory cell (i, j) will be described.

  When data is read from the memory transistor Tr1, for example, the bit line Bj is connected to a read circuit, the bit line B (j + 1) is set to 0 V, and the other bit lines Bk (k = 1 to j−1, j + 2 to n + 1). Is in a floating state. Further, the first word line Wai in the i row is Vrl (V), the second word line Wbi in the i row is Vrh (V), and the other first word lines Wak (k = 1 to i−1, i + 1). ˜m) is set to 0V, and the other second word lines Wbk (k = 1 to i−1, i + 1 to m) are set to 0V (see FIG. 6A). Vrh (V) is selected so as to be in an on state regardless of whether the memory transistor is written or erased (for example, 4 to 8 V). Vrl (V) is selected so as to be in an off state when the memory transistor is written, but is turned on when the memory transistor is erased (for example, 2 to 4 V).

  As a result, Tr1 is turned off when Tr1 is written, but both Tr1 and Tr2 are turned on when Tr1 is erased. That is, the effective resistance of the memory cell (i, j) changes greatly. Therefore, the state of Tr1 in the memory cell (i, j) can be read by connecting the bit line B (j + 1) to 0 V and the bit line Bj to the reading circuit.

  When reading data from the memory transistor Tr2, for example, the bit line Bj is connected to a read circuit, the bit line B (j + 1) is set to 0V, and the other bit lines Bk (k = 1 to j-1, j + 2 to n + 1). Is in a floating state. The first word line Wai in the i row is Vrh (V), the second word line Wbi in the i row is Vrl (V), and the other first word lines Wak (k = 1 to i−1, i + 1). ˜m) is set to 0V, and other second word lines Wbk (k = 1 to i−1, i + 1 to m) are set to 0V (see FIG. 6B). Vrh (V) is selected so as to be in an on state regardless of whether the memory transistor is written or erased (for example, 4 to 8 V). Vrl (V) is selected so as to be in an off state when the memory transistor is written, but is turned on when the memory transistor is erased (for example, 2 to 4 V).

  As a result, Tr2 is turned off when Tr2 is written, but both Tr1 and Tr2 are turned on when Tr2 is erased. That is, the effective resistance of the memory cell (i, j) changes greatly. Therefore, the state of Tr2 in the memory cell (i, j) can be read by connecting the bit line B (j + 1) to 0 V and the bit line Bj to the reading circuit.

  Note that the reading circuit may be configured to be able to read the difference in the connected load resistance. It is possible to perform resistance division, compare the amount of discharge after precharge, and the like. Further, since all other bit lines are in a floating state, the read operation is not affected.

  As described above, the memory cell is configured by two memory transistors and does not have a source line (instead, is connected to a bit line in an adjacent column). While maintaining the same function as that of a conventional full-function EEPROM constituted by two selection transistors, it is possible to realize a memory capacity of twice or more in the same memory cell area. As a result, it is possible to provide a full-function EEPROM that has a high integration density, and thus can be reduced in size and cost.

  Of course, the value of the operating voltage described above is an example, and is not limited to that value. Actually, the voltage applied to the memory transistor depends on the first insulating film, the second insulating film, the capacitance between the floating gate electrode and the gate electrode, the size of the overlap region, and the like. The operating voltage of the memory transistor changes accordingly.

  The value of the operating voltage needs to maintain a potential difference necessary for performing write, read and erase operations in the selected memory cell. Under such conditions, it is preferable to reduce as much as possible stress (unnecessary potential difference generated between the terminals) that causes malfunction or deterioration of reliability in the unselected memory cells. Any value may be used as long as the degree of malfunction and a decrease in reliability are within the range where there is no problem in use.

(Embodiment 2)
In this embodiment mode, a 2048-bit nonvolatile memory including p-channel memory transistors will be described with reference to the drawings as an example of the nonvolatile memory of the present invention.

  FIG. 11 shows a circuit diagram of the nonvolatile memory according to the present embodiment. The nonvolatile memory shown in FIG. 11 includes a memory cell array 605 in which 1024 memory cells (1, 1) to (32, 32) are arranged in a matrix of 32 vertical × 32 horizontal, an X address decoder 601, A Y address decoder 602 and other peripheral circuits 603 and 604 are included. Each memory cell is composed of two p-channel type memory transistors Tr1 and Tr2. When each memory transistor stores 1-bit data, the nonvolatile memory of this embodiment has a storage capacity of 2048 bits. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary.

  Each memory cell (considering memory cell (i, j) as a representative) (i and j are integers of 1 to 32) each have two memory transistors Tr1 and Tr2, and these two memory transistors Tr1 And Tr2 are connected in series. One of the source region or the drain region of the memory transistor Tr1 and the control gate electrode are connected to the bit line Bj and the first word line Wai, respectively, and the other of the source region or the drain region of the memory transistor Tr2 and the control gate electrode are connected to the bit line Bj. The line B (j + 1) and the second word line Wbi are connected to each other. The bit lines B1 to B32 are connected to the Y address decoder 602, and the first word lines Wa1 to Wa32 and the second word lines Wb1 to Wb32 are connected to the X address decoder 601.

  The nonvolatile memory of the present embodiment can store 2-bit data for one memory cell, and data can be written, read and erased completely in 1-bit units. The operation method is similar to the operation method of the n-channel nonvolatile memory described in the first embodiment, and writing and erasing by tunnel current are performed. The operation method of the p-channel type nonvolatile memory will be briefly described below.

  When data is written to the memory transistor Tr1 in the memory cell (i, j), for example, the bit line Bj is −10V, the other bit lines Bk (k = 1 to j−1, j + 1 to 33) are 0V, the first The word line Wai is 10V, the other first word lines Wak (k = 1 to i-1, i + 1 to 32) are 0V, and all the second word lines Wbk (k = 1 to 32) are 0V. . In Tr1 in the memory cell (i, j), 10 V is applied to the control gate electrode and −10 V is applied to the source region or drain region connected to the bit line Bj, and a tunnel current flows in the overlap region. Then, electrons are injected from the source region or the drain region to the floating gate electrode.

  When erasing data from the memory transistor Tr1 in the memory cell (i, j), for example, the bit line Bj is +10 V, the other bit lines Bk (k = 1 to j−1, j + 1 to 33) are 0 V, the first Word line Wai of −10V, the other first word lines Wak (k = 1 to i−1, i + 1 to 32) are 0 V, and all the second word lines Wbk (k = 1 to 32) are 10 V. To do. As a result, −10 V is applied to the control gate electrode of Tr1 in the memory cell (i, j), 10 V is applied to the source region or drain region connected to the bit line Bj, and a tunnel current flows from the floating gate to the channel formation region. Electrons are emitted.

  Although there is a potential difference of 10 V between the bit line Bj and the other bit lines Bk (k = 1 to j−1, j + 1 to 33), all the second word lines Wbk (k = 1 to 32) are connected. By setting the voltage to 0 V (during writing) or -10 V (during erasing), the memory transistor Tr2 is turned off in all the memory cells, and almost no current flows between the bit lines. Further, since only a potential difference of about 10 V is generated at most in the memory transistors other than Tr1 in the memory cell (i, j), writing or erasing is not erroneously performed on other memory transistors.

  When data is read from the memory transistor Tr1 in the memory cell (i, j), for example, the bit line Bj is connected to a read circuit, the bit line B (j + 1) is set to 0 V, and the other bit lines Bk (k = 1 to j). −1, j + 2 to 33) are in a floating state. Further, the first word line Wai in the i row is Vrl (V), the second word line Wbi in the i row is Vrh (V), and the other first word lines Wak (k = 1 to i−1, i + 1). To 32) is set to 0V, and the other second word lines Wbk (k = 1 to i-1, i + 1 to 32) are set to 0V. Vrh (V) is selected so that the memory transistor is turned on regardless of whether the memory transistor is written or erased (for example, −6 V). Further, Vrl (V) is selected so as to be in an on state when the memory transistor is written but is turned off when the memory transistor is erased (for example, −3V). As a result, Tr1 and Tr2 are both turned on when Tr1 is written, but Tr1 is turned off when Tr1 is erased. That is, the effective resistance of the memory cell (i, j) changes greatly. Therefore, the state of Tr1 in the memory cell (i, j) can be read by connecting the bit line B (j + 1) to 0 V and the bit line Bj to the reading circuit.

  As described above, the memory cell is configured by two memory transistors and does not have a source line (instead, is connected to a bit line in an adjacent column). While maintaining the same function as that of a conventional full-function EEPROM constituted by two selection transistors, it is possible to realize a memory capacity of twice or more in the same memory cell area. As a result, it is possible to provide a full-function EEPROM that has a high integration density, and thus can be reduced in size and cost.

  Note that the reading circuit may be configured to be able to read the difference in the connected load resistance. It is possible to perform resistance division, compare the amount of discharge after precharge, and the like. Further, since all other bit lines are in a floating state, the read operation is not affected.

  Of course, the value of the operating voltage described above is an example, and is not limited to that value. The value of the operating voltage may be any value within a range that does not cause malfunction in the non-selected memory cell while maintaining the potential difference necessary for performing the write, read and erase operations in the selected memory cell. It does not matter.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing a nonvolatile memory of the present invention will be described with reference to drawings. In the following description, two memory transistors (n-type memory TFTs) provided in a memory cell and a CMOS circuit serving as a drive circuit for the memory cell and other peripheral circuits are used as elements constituting the nonvolatile memory. Two thin film transistors (a p-type TFT and an n-type TFT) are described.

First, island-shaped semiconductor films 808, 810, and 812 are formed over the substrate 802 with the insulating film 804 interposed therebetween (FIG. 7A). The island-shaped semiconductor films 808, 810, and 812 are formed using a material (for example, silicon (Si)) as a main component by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 804 formed in advance on a substrate 802. An amorphous semiconductor film can be formed using Si _x Ge _1-x or the like, and the amorphous semiconductor film can be crystallized and then selectively etched. The crystallization of the amorphous semiconductor film is performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed.

When crystallization or recrystallization is performed by laser light irradiation, an LD-excited continuous wave (CW) laser (YVO ₄ , second harmonic (wavelength 532 nm)) can be used as a laser light source. The second harmonic is not particularly limited to the second harmonic, but the second harmonic is superior to higher harmonics in terms of energy efficiency. When the semiconductor film is irradiated with the CW laser, energy is continuously given to the semiconductor film. Therefore, once the semiconductor film is in a molten state, the molten state can be continued. Furthermore, the solid-liquid interface of the semiconductor film can be moved by scanning with a CW laser, and crystal grains that are long in one direction can be formed along the direction of this movement. The solid laser is used because the output stability is higher than that of a gas laser or the like, and stable processing is expected. Note that not only the CW laser but also a pulse laser having a repetition frequency of 10 MHz or more can be used. If a pulse laser with a high repetition frequency is used, the semiconductor film can always remain in a molten state if the laser pulse interval is shorter than the time from when the semiconductor film melts until it solidifies. A semiconductor film including crystal grains that are long in one direction can be formed. Other CW lasers and pulse lasers with a repetition frequency of 10 MHz or more can also be used. For example, examples of the gas laser include an Ar laser, a Kr laser, and a CO ₂ laser. Examples of the solid-state laser include a YAG laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a Y ₂ O ₃ laser, and a YVO ₄ laser. Examples of the metal vapor laser include a helium cadmium laser. In addition, it is preferable to emit laser light in TEM ₀₀ (single transverse mode) in a laser oscillator because energy uniformity of a linear beam spot obtained on the irradiated surface can be improved. In addition, a pulsed excimer laser may be used.

  The substrate 802 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate), a semiconductor substrate such as a ceramic substrate, and a Si substrate. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate.

  As the insulating film 804, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0), or the like is formed using a CVD method, a sputtering method, or the like. The insulating material is used. For example, in the case where the insulating film 804 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. In this manner, by forming the insulating film 804 functioning as a blocking layer, alkali metal such as Na or alkaline earth metal from the substrate 802 can be prevented from adversely affecting an element formed thereon. Note that the insulating film 804 may be omitted when quartz is used for the substrate 802.

Note that a low-concentration impurity element may be introduced into the semiconductor films 808, 810, and 812 in advance in order to control a threshold value or the like. In this case, the impurity element is also introduced into a region to be a channel formation region later in the semiconductor films 808, 810, and 812. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. For example, boron (B) as an impurity element is introduced in advance over the entire surface of the semiconductor films 808, 810, and 812 so as to be contained at a concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ atoms / cm ³ .

Next, a resist 814 is formed so as to cover part of the semiconductor film 808, the semiconductor film 810, and the semiconductor film 812, and an impurity element is introduced into the semiconductor film 808 using the resist 814 as a mask, so that an impurity region 816 is formed. (FIG. 7B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into part of the semiconductor film 808 as an impurity element so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

  Next, high-density plasma treatment is performed and the semiconductor films 808, 810, and 812 are subjected to oxidation treatment, nitridation treatment, or oxynitridation treatment, so that the surfaces of the semiconductor films 808, 810, and 812 are oxidized, nitride, or acid, respectively. Insulating films 818, 820, and 822 to be nitride films are formed, and then a charge storage layer 824 is formed so as to cover the insulating films 818, 820, and 822 (FIG. 7C).

  For example, in the case where an oxidation treatment or a nitridation treatment is performed using a semiconductor film containing Si as a main component as the semiconductor films 808, 810, and 812, a silicon oxide (SiOx) film and a silicon nitride (SiNx) are used as the insulating films 818, 820, and 822, respectively. ) A film is formed. Alternatively, after the semiconductor films 808, 810, and 812 are oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the semiconductor films 808, 810, and 812, a film containing oxygen and nitrogen (hereinafter referred to as “oxynitride film”) is formed over the silicon oxide film, and the insulating film 818 is formed. , 820 and 822 are films in which a silicon oxide film and an oxynitride film are stacked.

  Here, the insulating films 818, 820, and 822 are formed with a thickness of 1 to 10 nm, preferably 1 to 5 nm. For example, a silicon oxide film having a thickness of about 5 nm is formed on the surfaces of the semiconductor films 808, 810, and 812 by performing oxidation treatment on the semiconductor films 808, 810, and 812 by high-density plasma treatment, and then silicon oxide films by high-density plasma treatment. An oxynitride film having a thickness of about 2 nm is formed on the surface. At this time, it is preferable that the oxidation treatment and the nitriding treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

Note that in the case where a semiconductor film is oxidized by high-density plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) are used. Or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). On the other hand, in the case of nitriding a semiconductor film by high-density plasma treatment, under a nitrogen atmosphere (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), Plasma treatment is performed in an atmosphere of nitrogen, hydrogen, and a rare gas, or NH ₃ and a rare gas.

  As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. In the case where the high-density plasma treatment is performed in a rare gas atmosphere, the insulating films 818, 820, and 822 contain the rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. When Ar is used, the insulating films 818, 820, and 822 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature near the object to be processed (here, the semiconductor films 808, 810, and 812) formed over the substrate 802 is low, damage to the object to be processed is prevented. can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower than 100 degrees below the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. As a frequency for forming plasma, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

  In this embodiment mode, the insulating film 818 formed over the semiconductor film 808 in the memory portion functions as a tunnel oxide film in a nonvolatile memory to be completed later. Therefore, the thinner the insulating film 818, the easier the tunnel current to flow and the higher speed operation of the memory becomes possible. In addition, as the insulating film 818 is thinner, charge can be stored in a charge storage layer formed later at a lower voltage, so that power consumption of the semiconductor device can be reduced. Therefore, the insulating film 818 is preferably formed thin.

  In general, there is a thermal oxidation method as a method for forming a thin insulating film on a semiconductor film. However, when a memory element is provided on a substrate such as a glass substrate whose melting point is not sufficiently high, the insulating film is formed by a thermal oxidation method. Forming 818 is very difficult. In addition, an insulating film formed by a CVD method or a sputtering method includes defects inside the film, so that the film quality is not sufficient, and there is a problem that defects such as pinholes occur when the film thickness is thin. In addition, in the case where an insulating film is formed by a CVD method or a sputtering method, the end of the semiconductor film is not sufficiently covered, and the conductive film or the like formed later on the insulating film 818 may leak. is there. Therefore, as shown in this embodiment mode, by forming the insulating film 818 by high-density plasma treatment, an insulating film denser than an insulating film formed by a CVD method, a sputtering method, or the like can be formed. The end portion of the semiconductor film can be sufficiently covered with the insulating film. As a result, the memory can be operated at high speed, and the power consumption of the semiconductor device can be reduced.

  In addition, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x) are formed on the semiconductor films 808, 810, and 812 by CVD or sputtering. > Y> 0) or the like, the insulating films 818, 820, and 822 may be formed. In addition, after forming an insulating film using these materials, high-density plasma treatment is preferably performed, and the insulating film is subjected to oxidation treatment, nitridation treatment, or oxynitridation treatment. This is because the surface of the insulating film can be densified by performing oxidation treatment, nitriding treatment, or oxynitriding treatment on the insulating film.

  The charge storage layer 824 functions as a charge storage layer in a memory element to be completed later, and is generally called a floating gate (floating gate).

  The charge storage layer 824 is preferably formed using a material having an energy gap (band gap) smaller than that of the substance used for the semiconductor films 808, 810, and 812 (eg, silicon (Si)), for example, germanium (Ge), silicon It can be formed of a germanium alloy or the like. In addition, any other conductive film or semiconductor film can be used for the charge storage layer 824 as long as the material has a smaller energy gap (band gap) than the material used for the semiconductor films 808, 810, and 812.

For example, as the charge storage layer 824, a film containing germanium as a main component is formed with a thickness of 1 to 20 nm, preferably 5 to 10 nm, by performing a plasma CVD method in an atmosphere containing a germanium element (for example, GeH ₄ ). As described above, a film containing germanium having a smaller energy gap than Si is formed on the semiconductor film with an insulating film functioning as a tunnel oxide film formed using a material mainly containing Si as a semiconductor film. The second barrier formed by the insulating film for the charge of the charge storage layer is energetically higher than the first barrier formed by the insulating film for the charge of the semiconductor film. As a result, charges can be easily injected from the semiconductor film into the charge storage layer, and the charge can be prevented from disappearing from the charge storage layer. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved.

  Alternatively, the charge accumulation layer 824 can be formed using an insulating layer having defects that trap charges in the film, or an insulating layer containing conductive particles or semiconductor particles such as silicon. For example, as the charge storage layer 122, an insulating layer containing a nitrogen element, for example, a silicon nitride (SiNx) film, a silicon nitride oxide (SiNxOy) film (x> y), a silicon oxynitride (SiOxNy) (x> y) film, or These insulating layers are formed of a film containing conductive particles and semiconductor particles.

  Next, the charge storage layer 824 and the insulating films 820 and 822 formed over the semiconductor films 810 and 812 are selectively removed, so that the surfaces of the semiconductor films 810 and 812 are exposed. At this time, the charge storage layer 826 remaining over the semiconductor film 808 is formed (FIG. 7D).

  Next, an insulating film 828 is formed so as to cover the charge storage layer 826 and the semiconductor films 810 and 812 (FIG. 8A).

  The insulating film 828 is formed of an insulating film such as a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy) (x> y) film, a silicon nitride (SiNx) film, or a silicon nitride oxide (SiNxOy) (x> y) film. can do. These insulating films can be formed using a CVD method, a sputtering method, or the like. Alternatively, after these insulating films are formed by a CVD method, high-density plasma treatment may be performed, and the insulating film may be subjected to oxidation treatment, nitridation treatment, or oxynitridation treatment. In addition, a material such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx) may be used for the insulating film 828.

  Next, the insulating film 828 formed over the semiconductor films 810 and 812 is selectively removed to expose the surfaces of the semiconductor films 810 and 812 (FIG. 8B).

  Next, high-density plasma treatment is performed to form insulating films 832 and 834 over the semiconductor films 810 and 812, respectively (FIG. 8C). At this time, an insulating film 830 remaining over the semiconductor film 808 is formed. For example, by performing high-density plasma treatment in an oxygen atmosphere, insulating films 832 and 834 having silicon oxide films are formed on the surfaces of the semiconductor films 810 and 812. Note that the insulating films 832 and 834 function as gate insulating films in a thin film transistor to be formed later.

  Alternatively, the insulating film 828 formed over the semiconductor films 810 and 812 may be used as a gate insulating film without being removed. In this case, it is preferable that after the insulating film 828 is formed, high-density plasma treatment is performed to densify the surface of the insulating film. By manufacturing in this way, the manufacturing process can be simplified.

  Next, a conductive film 836 is formed so as to cover the insulating film 830 and the insulating films 832 and 834 (FIG. 8D).

  The conductive film 836 was selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. It can be formed of an element or an alloy material or a compound material containing these elements as main components. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used. Here, the conductive film 836 is provided with a structure in which tantalum nitride and tungsten are sequentially stacked. In the case of providing a stacked structure, tungsten nitride, molybdenum nitride, or titanium nitride can be formed below, and tantalum, molybdenum, titanium, or the like can be formed upward.

  Next, a resist is selectively provided over the conductive film 836, and the insulating film 818, the charge storage layer 826, the insulating film 830, and the conductive film 836 provided over the semiconductor film 808 are selectively formed using the resist as a mask. Remove. At the same time, the insulating film 832 and the conductive film 836 provided above the semiconductor film 810 and the insulating film 834 and the conductive film 836 provided above the semiconductor film 812 are selectively removed. As a result, an insulating film 838, a charge storage layer 840, an insulating film 842, a conductive film 844 (hereinafter also referred to as “stacked structure 1”) stacked in order, and an insulating film stacked in order are disposed above the semiconductor film 808. 848, a charge storage layer 850, an insulating film 852, and a conductive film 854 (hereinafter also referred to as “stacked structure 2”) are formed. Further, an insulating film 858 and a conductive film 860 which are sequentially stacked are formed above the semiconductor film 810, and an insulating film 862 and a conductive film 864 which are sequentially stacked are formed above the semiconductor film 812 (FIG. 9 (A)).

  Here, in the semiconductor film 808, a region 846 (overlap region) where the end portion of the stacked structure 1 and a part of the impurity region 816 overlap with each other, and a region where an end portion of the stacked structure 2 and a part of the impurity region 816 overlap with each other. The stacked structure 1 and the stacked structure 2 are formed by selective etching so that 856 is formed.

  In addition, the insulating films 838 and 848 formed over the semiconductor film 808 function as a tunnel insulating film in the memory, and the insulating films 842 and 852 function as a control insulating film in the memory.

Next, by using the conductive films 844, 854, 860, and 864 as masks, impurity elements are introduced into the semiconductor films 808, 810, and 812, so that low-concentration impurity regions 868, 870, and 872 are formed (FIG. 9B). ). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced at 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ to form n-type low-concentration impurity regions 868, 870, and 872.

Next, a resist 874 is selectively formed so as to cover the semiconductor films 808 and 812, and an impurity element is introduced into the semiconductor film 810 using the conductive film 860 as a mask to form a high-concentration impurity region 876 (FIG. 9C )). The high-concentration impurity region 876 functions as a source region or a drain region in the thin film transistor, and here, a channel formation region 878 is formed between the high-concentration impurity regions 876 that are provided apart from each other. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced at 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ , so that a high-concentration impurity region 876 showing p-type is formed.

  Next, an insulating film 880 (also referred to as a sidewall) in contact with the side surfaces of the conductive films 844, 854, 860, and 864 is formed (FIG. 9D), specifically, a silicon film is formed by a plasma CVD method, a sputtering method, or the like. A film containing an inorganic material such as silicon oxide or silicon nitride, or a film containing an organic material such as an organic resin is formed as a single layer or a stacked layer, and the insulating film is anisotropic mainly in the vertical direction. The insulating film 880 can be formed so as to be in contact with the side surfaces of the conductive films 844, 854, 860, and 864. Note that the insulating film 880 is formed when an LDD (Lightly Doped Drain) region is formed. Used as a mask for doping.

  Next, a resist 882 is selectively formed so as to cover the semiconductor film 810, and an impurity element is introduced into the semiconductor films 808 and 812 using the conductive films 844, 854, 864, and the insulating film 880 as masks, thereby forming a high concentration impurity region. 886, 890, 894, and 900 are formed (FIG. 10A). Note that the impurity element is again introduced into the impurity region 816 that is formed in advance in part of the high-concentration impurity regions 886 and 894.

The high concentration impurity regions 886, 890, 894, and 900 function as a source region or a drain region, and low concentration impurity regions 888 and 896 (LDD regions) are formed adjacent to the high concentration impurity region 890 and below the insulating film 880. Is done. Further, a low concentration impurity region 902 (LDD region) is formed adjacent to the high concentration impurity region 900 and below the insulating film 880, and a channel formation region 898 is formed between the low concentration impurity regions 902 (LDD regions). . In addition, a channel formation region 884 is formed between the high concentration impurity region 886 and the low concentration impurity region 888, and a channel formation region 892 is formed between the high concentration impurity region 894 and the low concentration impurity region 896. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced at 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ to form high-concentration impurity regions 886, 890, and 894 showing n-type.

  Next, an insulating film is formed over the semiconductor films 808, 810, and 812 and the conductive films 844, 854, 860, and 864 (FIG. 10B). Here, the insulating films 906 and 908 are formed as the insulating films. Note that the insulating film may be formed of a single layer or a stacked structure of three or more layers, and then the insulating films 906 and 908 contact holes are selectively formed to form a semiconductor. Conductive films 910, 912, 914, 916, and 918 that are electrically connected to the source region or the drain region of the films 808, 810, and 812 are selectively formed.

  The insulating films 906 and 908 are formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) by CVD or sputtering. An insulating layer having oxygen or nitrogen such as a film, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin A single layer or a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The conductive films 910, 912, 914, 916, and 918 are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni) by CVD or sputtering. , Elements selected from platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements An alloy material or a compound material containing as a main component is formed in a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. For example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film may be employed. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive films 910, 912, 914, 916, and 918 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

  Through the above-described steps, a memory transistor (n-type memory TFT) and two thin film transistors (p-type TFT and n-type TFT) constituting a CMOS circuit which is a drive circuit for memory cells and other peripheral circuits are manufactured. be able to.

  In addition, as shown in the above embodiment, the structure of the memory transistor is configured such that the memory cell includes two memory transistors and does not have a source line (instead, is connected to a bit line in an adjacent column) By doing so, it is possible to realize a memory capacity more than doubled in the same memory cell area while maintaining the same function as a conventional full-function EEPROM in which a memory cell is constituted by one memory transistor and one selection transistor. . As a result, it is possible to create a full-function EEPROM that has a high integration density and is therefore small and low-cost.

  Note that although an example in which a thin film transistor (TFT) is formed using a semiconductor film formed over a substrate is described in this embodiment mode, the semiconductor device of the present invention is not limited thereto. For example, a field effect transistor (FET) in which a channel region is directly formed on a substrate using a semiconductor substrate such as Si may be used.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 4)
In this embodiment, application examples of a semiconductor device including the nonvolatile semiconductor memory described in the above embodiment and capable of inputting and outputting data without contact will be described below with reference to drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

  First, an example of a top structure of the semiconductor device described in this embodiment will be described with reference to FIG. A semiconductor device 80 illustrated in FIG. 13 includes a thin film integrated circuit 131 provided with a plurality of elements included in the nonvolatile memory and the logic portion described in the above embodiment, and a conductive film 132 functioning as an antenna. The conductive film 132 functioning as an antenna is electrically connected to the thin film integrated circuit 131.

  FIG. 13B is a schematic view of the cross section of FIG. The conductive film 132 functioning as an antenna may be provided above the elements included in the memory portion and the logic portion. For example, in the structure described in the above embodiment mode, the antenna is provided over the insulating film 908 with the insulating film 920 interposed therebetween. The conductive film 132 functioning as can be provided.

  The conductive film 132 functioning as an antenna may be provided so as to overlap with the thin film integrated circuit 131 or may be provided around the thin film integrated circuit 131 without overlapping. In this embodiment mode, an example in which the conductive film 132 functioning as an antenna is provided in a coil shape and an electromagnetic induction method or an electromagnetic coupling method is applied is shown; however, the semiconductor device of the present invention is not limited to this and uses a microwave method. It is also possible to apply. In the case of a microwave method, the shape of the conductive film 132 functioning as an antenna may be determined as appropriate depending on the wavelength of the electromagnetic wave used.

  For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, the conductive film functioning as an antenna is used because electromagnetic induction due to a change in magnetic field density is used. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna).

  In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. For example, the conductive film functioning as an antenna may be set as appropriate, for example, the conductive film functioning as an antenna may be linear (for example, a dipole antenna), flat (for example, a patch antenna), or ribbon type. It can be formed into a shape or the like. Further, the shape of the conductive film functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  The conductive film 132 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  In the case of providing an antenna, the thin film integrated circuit 131 and the conductive film 132 functioning as an antenna may be directly formed over one substrate, or the thin film integrated circuit 131 and the conductive film 132 functioning as an antenna may be provided. May be provided on different substrates and then bonded together so as to be electrically connected.

  Next, an example of operation of the semiconductor device described in this embodiment will be described.

  The semiconductor device 80 has a function of communicating data without contact, and controls the high frequency circuit 81, the power supply circuit 82, the reset circuit 83, the clock generation circuit 84, the data demodulation circuit 85, the data modulation circuit 86, and other circuits. A control circuit 87, a memory circuit 88, and an antenna 89 are provided (FIG. 14A). The high frequency circuit 81 is a circuit that receives a signal from the antenna 89 and outputs the signal received from the data modulation circuit 86 from the antenna 89, and the power supply circuit 82 is a circuit that generates a power supply potential from the received signal, and a reset circuit 83. Is a circuit that generates a reset signal, a clock generation circuit 84 is a circuit that generates various clock signals based on the reception signal input from the antenna 89, and a data demodulation circuit 85 demodulates the reception signal to control the control circuit 87. The data modulation circuit 86 is a circuit that modulates the signal received from the control circuit 87. Further, as the control circuit 87, for example, a code extraction circuit 91, a code determination circuit 92, a CRC determination circuit 93, and an output unit circuit 94 are provided. The code extraction circuit 91 is a circuit that extracts a plurality of codes included in an instruction sent to the control circuit 87, and the code determination circuit 92 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 93 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

  Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 89. The radio signal is sent to the power supply circuit 82 via the high frequency circuit 81, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 80. The signal sent to the data demodulation circuit 85 via the high frequency circuit 81 is demodulated (hereinafter, demodulated signal). Further, the signal and the demodulated signal that have passed through the reset circuit 83 and the clock generation circuit 84 via the high frequency circuit 81 are sent to the control circuit 87. The signal sent to the control circuit 87 is analyzed by the code extraction circuit 91, the code determination circuit 92, the CRC determination circuit 93, and the like. Then, information on the semiconductor device stored in the memory circuit 88 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 94. Further, the encoded information of the semiconductor device 80 passes through the data modulation circuit 86 and is transmitted on the radio signal by the antenna 89. Note that in a plurality of circuits included in the semiconductor device 80, a low power supply potential (hereinafter referred to as VSS) is common and VSS can be GND. Further, the nonvolatile memory of the present invention can be applied to the memory circuit 88.

  As described above, by transmitting a signal from the reader / writer to the semiconductor device 80 and receiving the signal transmitted from the semiconductor device 80 by the reader / writer, the data of the semiconductor device can be read.

  Further, the semiconductor device 80 may be of a type in which power supply voltage is supplied to each circuit by electromagnetic waves without mounting a power source (battery), or each circuit is mounted by using electromagnetic waves and a power source (battery). The power supply voltage may be supplied to the type.

  Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on a side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on a side surface of the article 3220 (FIG. 14B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210 Is done. Further, when the product 3260 is conveyed by a belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 14C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

  In addition, the nonvolatile memory of the present invention can be used for electronic devices in various fields including the memory. For example, as an electronic device to which the nonvolatile memory of the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a computer, Playing back a recording medium such as a game machine, a portable information terminal (mobile computer, mobile phone, portable game machine or electronic book), an image playback device (specifically a DVD (digital versatile disc)) provided with a recording medium, And a device provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

  FIGS. 15A and 15B show a digital camera. FIG. 15B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter button 2115, and the like. In addition, a nonvolatile memory 2116 that can be taken out is provided, and data captured by the digital camera is stored in the memory 2116. A nonvolatile memory formed using the present invention can be applied to the memory 2116.

  FIG. 15C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the memory 2125 and played back. A nonvolatile memory formed using the present invention can be applied to the memory 2125.

  FIG. 15D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 15D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the memory portion 2132, a nonvolatile memory formed using the present invention can be used. For example, by using a NAND nonvolatile memory with a recording capacity of 20 to 200 gigabytes (GB) and operating the operation unit 2133, video and audio (music) can be recorded and reproduced. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable audio device. Note that the nonvolatile memory provided in the memory portion 2132 may be removable.

  FIG. 15E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a memory portion 2144. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the memory portion 2144, a nonvolatile memory formed using the present invention can be used. For example, by using a NAND nonvolatile memory with a recording capacity of 20 to 200 gigabytes (GB) and operating the operation key 2143, video and audio (music) can be recorded and reproduced. Note that the nonvolatile memory provided in the memory portion 2144 may be removable.

  As described above, the applicable range of the nonvolatile memory of the present invention is so wide that the nonvolatile memory of the present invention can be used for electronic devices in various fields as long as it has a memory.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

The figure which shows an example of the non-volatile memory of this invention. The figure which shows an example of the non-volatile memory of this invention. The figure which shows an example of the non-volatile memory of this invention. The figure which shows an example of operation | movement of the non-volatile memory of this invention. The figure which shows an example of operation | movement of the non-volatile memory of this invention. The figure which shows an example of operation | movement of the non-volatile memory of this invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile memory of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile memory of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile memory of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile memory of the present invention. The figure which shows an example of the non-volatile memory of this invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. The figure which shows an example of operation | movement of the non-volatile memory of this invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention.

Explanation of symbols

101 X address decoder 102 Y address decoder 103 Peripheral circuit 104 Insulating film 105 Memory cell array 122 Charge storage layer 131 Thin film integrated circuit 132 Conductive film 174 Conductive film 201 Substrate 202 Insulating film 203 Semiconductor film 208 Insulating film 209 Insulating film 211 Memory cell 212 Memory Transistor 213 Memory transistor 221 Memory cell 223 Semiconductor film 312 Memory transistor 401 X address decoder 402 Y address decoder 403 Peripheral circuit 405 Memory cell array 601 X address decoder 602 Y address decoder 603 Peripheral circuit 605 Memory cell array 802 Substrate 804 Insulating film 808 Semiconductor film 810 Semiconductor film 812 Semiconductor film 814 Resist 816 Impurity region 818 Insulating film 820 Insulating film 824 Charge storage layer 826 Load accumulation layer 828 Insulating film 830 Insulating film 832 Insulating film 834 Insulating film 836 Conductive film 838 Insulating film 840 Charge accumulating layer 842 Insulating film 844 Conductive film 848 Insulating film 850 Charge accumulating layer 852 Insulating film 854 Insulating film 858 Insulating film 860 Conductive film 862 Insulating film 864 Conductive film 868 Low concentration impurity region 874 Resist 876 High concentration impurity region 878 Channel formation region 880 Insulating film 882 Resist 884 Channel formation region 886 High concentration impurity region 888 Low concentration impurity region 890 High concentration impurity region 892 Channel formation region 894 High-concentration impurity region 896 Low-concentration impurity region 898 Channel formation region 900 High-concentration impurity region 902 Low-concentration impurity region 906 Insulating film 908 Insulating film 910 Conductive film 920 Insulating film 922 Conductive film 103a Semiconductor film 1225 Memory 2 3a channel formation region 203b channel formation region 203c drain region 203e drain region 204a first insulating film 204b first insulating film 205a conductive film 205b conductive film 206a second insulating film 206b second insulating film 207a conductive film 207b conductive film 210a conductive film 210b conductive film

Claims (2)

A memory cell array in which a plurality of memory cells are arranged in a matrix corresponding to the row direction and the column direction;
A plurality of first word lines;
A plurality of second word lines;
A plurality of bit lines including a first bit line and a second bit line;
Each of the plurality of memory cells includes a first memory transistor and a second memory transistor,
A gate electrode of the first memory transistor is electrically connected to the first word line;
A gate electrode of the second memory transistor is electrically connected to the second word line;
One of a source region and a drain region of the first memory transistor is electrically connected to one of a source region and a drain region of the second memory transistor;
The first bit line is provided in the other of the source region and the drain region of the second memory transistor provided in the memory cell in the (j−1) th column and in the memory cell in the jth column. Electrically connected to the other of the source region and the drain region of the first memory transistor;
The second bit line includes the other of the source region and the drain region of the second memory transistor provided in the memory cell in the jth column, and the second bit line provided in the memory cell in the (j + 1) th column. Electrically connected to the other of the source region and the drain region of one memory transistor ;
A first potential is applied to the first word line, a second potential is applied to the second word line, the second potential is applied to the first bit line, and the second potential is applied to the second word line. By applying a third potential to the bit line, data is written to the first memory transistor provided in the memory cell in the j-th column,
The second potential is applied to the first word line, the first potential is applied to the second word line, the third potential is applied to the first bit line, and the first potential is applied to the first word line. When the second potential is applied to the second bit line, data is written to the second memory transistor provided in the memory cell in the j-th column,
The second potential is applied to the first word line, the third potential is applied to the second word line, the first potential is applied to the first bit line, and the first potential is applied to the first word line. By applying the third potential to the second bit line, data is erased from the first memory transistor provided in the memory cell in the j-th column,
The third potential is applied to the first word line, the second potential is applied to the second word line, the third potential is applied to the first bit line, and By applying the first potential to the second bit line, data is erased from the second memory transistor provided in the memory cell in the j-th column,
The nonvolatile memory according to claim 1, wherein the third potential is a value between the first potential and the second potential . An electronic device incorporating the nonvolatile memory according to claim 1 .

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