JP5164405B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory device which can be electrically written, read and erased, and a manufacturing method thereof. In particular, the present invention relates to a structure of a floating gate in the nonvolatile semiconductor memory device.

The market for nonvolatile memories that can electrically rewrite data and store data even when the power is turned off is expanding. The nonvolatile memory has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is characterized in that a region capable of accumulating charges for a long period is provided on the channel formation region. This charge storage region is formed on an insulating layer and is also called a floating gate because it is isolated from the surroundings. Since the floating gate is surrounded by an insulator and is electrically insulated from the surroundings, the floating gate has a characteristic of continuing to hold the charge when the charge is injected into the floating gate. On the floating gate, a gate electrode called a control gate is further provided via an insulating layer. The control gate is distinguished from the floating gate because a predetermined voltage is applied when data is written or read.

The floating gate type nonvolatile memory having such a structure has a mechanism for storing data by electrically controlling charge injection into the floating gate and discharge of the charge from the floating gate. Specifically, charge injection into the floating gate and charge discharge from the floating gate are performed by applying a high voltage between the semiconductor layer in which the channel formation region is formed and the control gate. At this time, it is said that Fowler-Nordheim type (FN type) tunnel current (NAND type) or thermal electrons (NOR type) flow in the insulating layer on the channel formation region. Thus, the insulating layer is also called a tunnel insulating layer.

Floating gate type non-volatile memories are required to have characteristics capable of retaining the charge stored in the floating gate for more than 10 years in order to guarantee reliability. For this reason, the tunnel insulating layer is required to have high insulating properties so as to prevent charges from leaking while being formed with a thickness through which a tunnel current flows.

The floating gate formed on the tunnel insulating layer is formed of silicon, which is the same semiconductor material as the semiconductor layer in which the channel formation region is formed. Specifically, a method of forming a floating gate with polycrystalline silicon is widespread, and for example, a method in which a polysilicon film is deposited to a thickness of 400 nm is known (see Patent Document 1).
JP 2000-58685 A (page 7, FIG. 7)

Since the floating gate and the channel formation region of the non-volatile memory are formed of the same silicon material, the energy level at the bottom of the conduction band as seen from the band model is the same. Rather, the floating gate is formed of polycrystalline silicon, and when the thickness is reduced, the energy level at the bottom of the conduction band becomes higher than that of the semiconductor layer forming the channel formation region. When such a state is formed, it becomes difficult to inject electrons from the semiconductor layer forming the channel formation region into the floating gate, and it is necessary to increase the writing voltage. For this reason, in a nonvolatile memory in which the floating gate is formed of polycrystalline silicon, in order to lower the write voltage as much as possible, an n-type impurity such as phosphorus or arsenic is added to the floating gate to bring the Fermi level to the conduction band side. It is necessary to shift to.

With respect to the gate insulating layer provided between the floating gate and the semiconductor layer, it is necessary to reduce the thickness of the gate insulating layer in order to inject charges into the floating gate with a low voltage. On the other hand, in order to stably hold the charge of the floating gate for a long period of time, it is necessary to increase the film thickness in order to prevent charge leakage.

After all, the conventional nonvolatile memory requires a high write voltage. Further, with respect to deterioration due to repeated rewriting of the charge retention characteristic, reliability is ensured by taking measures such as providing redundant memory cells or devising a controller and performing error detection / error correction.

Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that is excellent in writing characteristics and charge retention characteristics.

The present invention includes a semiconductor layer in which a channel formation region is provided between a pair of impurity regions formed apart from each other, and a first insulating layer at a position that is an upper layer portion of the semiconductor layer and substantially overlaps the channel formation region , A non-volatile semiconductor memory device having a floating gate, a second insulating layer, and a control gate. In the present invention, the floating gate is formed of a plurality of layers using a semiconductor material. Alternatively, a barrier layer that improves the water resistance of the floating gate and prevents corrosion is provided in contact with the second insulating layer side of the floating gate formed of a specific semiconductor material. The semiconductor material for forming the floating gate can be selected from a plurality of types in relation to the semiconductor layer for forming the channel formation region.

As a semiconductor material for forming the floating gate, a material that satisfies one or more of the following conditions can be selected. The band gap (also referred to as “band gap”) of the semiconductor material forming the floating gate is preferably smaller than the band gap of the semiconductor layer. For example, the band gap of the semiconductor material forming the floating gate and the band gap of the semiconductor layer have a difference of 0.1 eV or more, and the former is preferably smaller. The band gap of the second insulating layer provided in contact with the floating gate is preferably larger than the band gap of the semiconductor material forming the floating gate.

The semiconductor material is preferably formed of a material having an electron affinity higher than that of the material forming the semiconductor layer. The semiconductor material preferably has a higher barrier energy against electrons of the floating gate formed by the first insulating layer than that of electrons of the semiconductor layer formed by the first insulating layer.

As a semiconductor material for forming the floating gate, typically, germanium or a germanium compound is preferable.

The floating gate is applied to the nonvolatile semiconductor memory device according to the present invention for the purpose of accumulating electric charge, but if it has a similar function, that is, if it functions as a charge accumulation layer, germanium or It is not limited to a germanium compound, and can be replaced with an oxide or nitride of the germanium or germanium compound, or an oxide or nitride layer containing the germanium or germanium compound.

Further, it is preferable to apply a layer formed of silicon or a silicon compound as a layer in contact with the floating gate formed of germanium or a germanium compound. As the silicon compound, silicon nitride, silicon nitride oxide, silicon carbide, silicon germanium containing germanium at a concentration of less than 10 atomic%, metal nitride, metal oxide, or the like can be used. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

In the nonvolatile semiconductor memory device according to the present invention, it is preferable that the semiconductor layer is formed on an insulating surface and separated into islands. At least a semiconductor layer forming a memory element and a semiconductor layer forming a logic circuit are preferably divided. That is, the present invention provides a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other, and a first insulating layer at a position that is an upper layer portion of the semiconductor layer and substantially overlaps the channel formation region. , A non-volatile semiconductor memory device having a floating gate, a second insulating layer, and a control gate, in which a semiconductor layer is formed on an insulating surface.

In the case where the floating gate is formed over the semiconductor layer through the first insulating layer functioning as the tunnel insulating layer, the floating gate is formed of a semiconductor material containing at least germanium, so that the charge from the semiconductor layer to the floating gate can be reduced. Implantation can be facilitated, and charge retention characteristics in the floating gate can be improved. Further, by providing a semiconductor material or a barrier layer that prevents corrosion by improving the water resistance of the floating gate in contact with the floating gate, deterioration of the floating gate can be suppressed.

In addition, by forming a floating gate using a material having a property close to that of silicon, a nonvolatile semiconductor memory device having excellent characteristics can be manufactured without impairing productivity. Since germanium is a material belonging to Group 14 of the same periodic table as silicon and is a semiconductor, it can perform fine processing of a thin film without imposing a burden on a manufacturing facility.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

FIG. 1 is a cross-sectional view for explaining a main configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. 1 particularly shows the main part of the nonvolatile memory element. This nonvolatile memory element is manufactured using a substrate 10 having an insulating surface. As the substrate 10 having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used.

A semiconductor layer 14 is formed over the substrate 10 having the insulating surface. A base insulating layer 12 may be provided between the substrate 10 and the semiconductor layer 14. The base insulating layer 12 prevents impurities such as alkali metals from diffusing from the substrate 10 to the semiconductor layer 14 and contaminates them, and may be provided as a blocking layer as appropriate.

As the base insulating layer 12, using a CVD method, a sputtering method, or the like, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)), or the like is used. It is formed using an insulating material. For example, in the case where the base insulating layer 12 has two structures, a silicon nitride oxide film may be formed as a first insulating film and a silicon oxynitride film may be formed as a second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film.

The semiconductor layer 14 is preferably formed using a single crystal semiconductor or a polycrystalline semiconductor. For example, after the semiconductor layer formed on the entire surface of the substrate 10 is crystallized on the substrate 10 by a sputtering method, a plasma CVD method, or a low pressure CVD method, the semiconductor layer 14 can be formed by selective etching. That is, for the purpose of element isolation, it is preferable to form an island-shaped semiconductor layer on the insulating surface and to form one or more nonvolatile memory elements on the semiconductor layer. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor film, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used. Further, instead of such a thin film process, a so-called SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface may be used.

Thus, by separating and forming the semiconductor layer formed on the insulating surface in an island shape, even when the memory element array and the peripheral circuit are formed on the same substrate, the element can be effectively separated. That is, a memory element array that needs to be written and erased at a voltage of about 10V to 20V and a peripheral circuit that operates at a voltage of about 3V to 7V and mainly performs data input / output and command control on the same substrate. Even when formed, mutual interference due to a difference in voltage applied to each element can be prevented.

A p-type impurity may be implanted into the semiconductor layer 14. For example, boron is used as the p-type impurity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ^{3 to} 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the transistor, and acts effectively when added to the channel formation region. The channel formation region is formed in a region substantially coinciding with the gate 26 described later, and is located between the pair of impurity regions 18 of the semiconductor layer 14.

The pair of impurity regions 18 functions as a source and a drain in the nonvolatile memory element. The pair of impurity regions 18 is formed by adding phosphorus or arsenic, which is an n-type impurity, at a concentration of about 1 × 10 ¹⁹ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ .

A first insulating layer 16, a floating gate electrode 20, a second insulating layer 22, and a control gate electrode 24 are formed on the semiconductor layer 14. In this specification, from the floating gate electrode 20 to the control gate electrode 24. The stacked structure may be referred to as the gate 26.

The first insulating layer 16 is formed of silicon oxide or a stacked structure of silicon oxide and silicon nitride. The first insulating layer 16 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because an insulating layer formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. Since the first insulating layer 16 is used as a tunnel insulating layer for injecting charges into the floating gate electrode 20, a dense layer having high withstand voltage and excellent reliability is preferable. The first insulating layer 16 is preferably formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. For example, when the gate length is 600 nm, the first insulating layer 16 can be formed to a thickness of 3 nm to 6 nm.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating film is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

When the surface of the semiconductor layer 14 is oxidized by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) are used in an oxygen atmosphere. Or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe)). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used.

FIG. 15 shows a configuration example of an apparatus for performing plasma processing. This plasma processing apparatus includes a support base 88 for arranging the substrate 10, a gas supply unit 84 for introducing gas, an exhaust port 86 connected to a vacuum pump for exhausting gas, an antenna 80, and a dielectric plate. 82, a microwave supply unit 92 for supplying microwaves for plasma generation. In addition, the temperature of the substrate 10 can be controlled by providing the temperature control unit 90 on the support base 88.

Hereinafter, the plasma treatment will be described. Note that plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating layer, and a conductive layer. For these processes, a gas supplied from the gas supply unit 84 may be selected according to the purpose.

The oxidation treatment or nitridation treatment may be performed as follows. First, the processing chamber is evacuated and a plasma processing gas containing oxygen or nitrogen is introduced from the gas supply portion 84. The substrate 10 is heated to 100 ° C. to 550 ° C. by the room temperature or the temperature controller 90. The interval between the substrate 10 and the dielectric plate 82 is about 20 mm to 80 mm (preferably 20 mm to 60 mm). Next, the microwave is supplied from the microwave supply unit 92 to the antenna 80. Then, plasma 94 is generated by introducing the microwave from the antenna 80 through the dielectric plate 82 into the processing chamber. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized and / or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas. This method can perform oxidation, nitridation, or oxynitridation by solid-phase reaction at a low temperature of 500 ° C. or lower by effectively using active radicals excited by plasma.

In FIG. 1, an example of a suitable first insulating layer 16 formed by plasma treatment is to form a silicon oxide layer 16a with a thickness of 3 nm or more and 6 nm or less on the semiconductor layer 14 by plasma treatment in an oxygen atmosphere, and then The silicon nitride layer 16b is formed by nitriding the surface of the silicon oxide layer in a nitrogen atmosphere. In the case where a silicon material is used as a typical example of the semiconductor layer 14, a dense oxide film without distortion at the interface can be formed by oxidizing the surface of the silicon layer by plasma treatment. Further, the oxide film can be further densified by nitriding the oxide film by plasma treatment to form a nitride layer by replacing oxygen in the surface layer portion with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In any case, heat generated at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or lower is used by using the solid phase oxidation treatment or solid phase nitridation treatment by plasma treatment as described above. An insulating layer equivalent to the oxide film can be obtained. That is, a highly reliable tunnel insulating layer can be formed as the tunnel insulating layer of the nonvolatile memory element.

The floating gate electrode 20 is formed on the first insulating layer 16. The floating gate electrode 20 is formed of a first floating gate electrode 20a and a second floating gate electrode 20b. Of course, the present invention is not limited to this two-layer structure, and a plurality of layers may be stacked. However, the first floating gate electrode 20a formed in contact with the first insulating layer 16 is preferably formed of a semiconductor material, and a material that satisfies one or more of the following conditions can be selected.

The band gap of the semiconductor material forming the first floating gate electrode 20 a is preferably smaller than the band gap of the semiconductor layer 14. For example, the band gap of the semiconductor material forming the first floating gate electrode 20a and the band gap of the semiconductor layer 14 are preferably 0.1 eV or more, and the former is preferably smaller. In order to improve the charge (electron) injection property and the charge retention characteristics by lowering the energy level of the bottom of the conduction band of the floating gate electrode 20 from the energy level of the bottom of the conduction band of the semiconductor layer 14. is there.

The semiconductor material forming the first floating gate electrode 20a is preferably a material having a higher electron affinity than the material forming the semiconductor layer 14. By lowering the energy level of the bottom of the conduction band of the first floating gate electrode 20a from the energy level of the bottom of the conduction band of the semiconductor layer 14, the charge (electron) injection property is improved and the charge retention characteristics are improved. This is to make it happen. In the case of semiconductors, electron affinity is the energy difference from the bottom of the conduction band to vacuum.

The semiconductor material forming the first floating gate electrode 20a is the first floating gate formed by the first insulating layer 16 against the barrier energy against electrons of the semiconductor layer 14 formed by the first insulating layer 16. It is preferable that the barrier energy for electrons of the electrode 20a is high. This is because it is easy to inject charges (electrons) from the semiconductor layer 14 to the first floating gate electrode 20a, and the charge is prevented from disappearing from the first floating gate electrode 20a.

As a condition that satisfies such a condition, the first floating gate electrode 20a can be typically formed of germanium or a germanium compound. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the concentration of germanium is less than 10 atomic%, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

Of course, other materials can be applied as long as the same effect can be obtained as the first floating gate electrode 20a. For example, a ternary semiconductor material containing germanium can be used. The semiconductor material may be hydrogenated. Further, as a function of a charge storage layer of a nonvolatile memory element, an oxide or nitride of the germanium or germanium compound, or an oxide or nitride layer containing the germanium or germanium compound can be used. .

A layer formed of silicon or a silicon compound is preferably used for the second floating gate electrode 20b provided on the second insulating layer 22 side in contact with the first floating gate electrode 20a. As the silicon compound, silicon nitride, silicon nitride oxide, silicon carbide, silicon germanium containing germanium at a concentration of less than 10 atomic%, metal nitride, metal oxide, or the like can be used. Thus, by forming the second floating gate electrode 20b with a material having a larger band gap than the first floating gate electrode 20a, the charge accumulated in the floating gate leaks to the second insulating layer 22 side. Can be prevented. Further, a metal nitride or a metal oxide can be used for forming the second floating gate electrode 20b. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

In any case, in the manufacturing process, the second layer of silicon or silicon compound, metal nitride, or metal oxide described above is provided on the upper layer side of the first layer formed of germanium or germanium compound. It can be used as a barrier layer for the purpose of water resistance and chemical resistance. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the floating gate can be easily processed.

The second insulating layer 22 is made of silicon oxide, silicon oxynitride (SiOxNy, (x> y)), silicon nitride (SiNx), silicon nitride oxide (SiNxOy, (x> y)), aluminum oxide (AlxOy), or the like. One layer or a plurality of layers are formed by a low pressure CVD method, a plasma CVD method, or the like. The thickness of the second insulating layer 22 is 1 nm to 20 nm, preferably 5 nm to 10 nm. For example, a silicon nitride layer 22a having a thickness of 3 nm and a silicon oxide layer 22b having a thickness of 5 nm can be used. Further, a plasma treatment may be performed on the second floating gate electrode 20b to form a nitride film (for example, silicon nitride when silicon is used as the second floating gate electrode 20b). . In any case, the first insulating layer 16 and the second insulating layer 22 are either a nitride film or a nitrided layer on one or both sides in contact with the floating gate electrode 20, so that the floating gate electrode 20 Oxidation can be prevented.

The control gate electrode 24 is a metal selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or contains these metals as a main component. It is preferable to form with an alloy material or a compound material. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. Further, the control gate electrode 24 may be formed by a laminated structure of one or more metal nitride layers 24a and the metal layer 24b. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer 24a, the adhesion of the metal layer 24b can be improved and peeling can be prevented. Further, since the metal nitride such as tantalum nitride has a high work function, the thickness of the first insulating layer 16 can be increased by a synergistic effect with the second insulating layer 22.

An operation mechanism of the nonvolatile memory element shown in FIG. 1 will be described with reference to a band diagram. In the band diagram shown below, the same elements as those in FIG.

FIG. 2 shows a state in which the semiconductor layer 14, the first insulating layer 16, the floating gate electrode 20, the second insulating layer 22, and the control gate electrode 24 are stacked. FIG. 2 shows a case where no voltage is applied to the control gate electrode 24 and the Fermi level Ef of the semiconductor layer 14 and the Fermi level Efm of the control gate electrode 24 are equal.

Among the semiconductor layer 14 and the floating gate electrode 20, at least the first floating gate electrode 20a is formed of different materials with the first insulating layer 16 interposed therebetween. The band gap Eg1 (energy difference between the lower end Ec of the conduction band and the upper end Ev of the valence band) of the semiconductor layer 14 is different from the band gap Eg2 of the first floating gate electrode 20a, and the latter band gap is reduced. Combined. For example, silicon (1.12 eV) can be combined as the semiconductor layer 14 and germanium (0.72 eV) or silicon germanium (0.73 eV to 1.0 eV) can be combined as the first floating gate electrode 20a. When polycrystalline silicon is used as the second floating gate electrode 20b, the band gap is larger than that of the first floating gate electrode 20a. This difference in band gap serves as a barrier against carriers injected into the first floating gate electrode 20a through the first insulating layer 16. Thereby, the injected carriers can be prevented from leaking to the second insulating layer 22 side and trapped at the interface.

The first insulating layer 16 is represented by a silicon oxide layer 16a (about 8 eV) and a silicon nitride layer 16b (about 5 eV) obtained by nitriding the silicon oxide by plasma treatment. The second insulating layer 22 also shows a state in which the silicon nitride layer 22a and the silicon oxide layer 22b are stacked from the floating gate electrode 20 side.

When the vacuum level is 0 eV, the energy level of the conduction band of silicon is −4.05 eV, and the energy level of the conduction band of germanium is −4.1 eV. The energy level of the conduction band of silicon oxide is -0.9 eV. Therefore, by the combination of the semiconductor layer 14 and the first floating gate electrode 20a, the first insulating layer 16 against the barrier energy (Be1) to electrons of the semiconductor layer 14 formed by the first insulating layer 16 is used. The barrier energy (Be2) for electrons of the first floating gate electrode 20a formed by the above can be increased. That is, the energy barrier against electrons, that is, the first barrier Be1 and the second barrier Be2 have different values, and can have a relationship of Be2> Be1.

In such a situation, the silicon band gap Eg1 as the semiconductor layer 14 and the germanium band gap Eg2 as the first floating gate electrode 20a satisfy the relationship of Eg1> Eg2. Furthermore, when the electron affinity is considered as described above, an energy difference ΔE between the energy levels at the bottom of the conduction band of the semiconductor layer 14 and the floating gate electrode 20 is generated. As will be described later, this energy difference ΔE acts in the direction of accelerating electrons when injecting electrons from the semiconductor layer 14 to the floating gate electrode 20, thereby contributing to a decrease in the write voltage.

For comparison, FIG. 16 shows a band diagram in the case where the semiconductor layer and the floating gate electrode are formed of the same semiconductor material. This band diagram shows a state in which the semiconductor layer 01, the first insulating layer 02, the floating gate electrode 03, the second insulating layer 04, and the control gate electrode 05 are sequentially stacked. Even when the semiconductor layer 01 and the floating gate electrode 03 are formed of the same silicon material, the band gap differs if the floating gate electrode 03 is formed thin. In FIG. 16, the band gap of the semiconductor layer 01 is represented by Eg1, and the band gap of the floating gate electrode 03 is represented by Eg2. For example, when silicon is thinned, it is said that the band gap increases from 1.12 eV in bulk to about 1.4 eV. As a result, an energy difference of −ΔE is generated between the semiconductor layer 01 and the floating gate electrode 03 in a direction that blocks electron injection. In such a situation, a high voltage is required to inject electrons from the semiconductor layer 01 into the floating gate electrode 03. In other words, in order to lower the write voltage, it is necessary to form the floating gate electrode 03 as thick as bulk silicon or dope phosphorus or arsenic as an n-type impurity at a high concentration. This is a defect in the conventional nonvolatile memory.

By the way, in order to inject electrons into the floating gate electrode 20, there are a method using thermal electrons and a method using FN tunnel current. When thermoelectrons are used, a positive voltage is applied to the control gate electrode 24, and a high voltage is applied to the drain to generate thermoelectrons. Thereby, thermoelectrons can be injected into the floating gate electrode 20. When an FN type tunnel current is used, a positive voltage is applied to the control gate electrode 24 and injected from the semiconductor layer 14 into the floating gate electrode 20 by the FN type tunnel current.

FIG. 6A shows an applied voltage when injecting into the floating gate electrode 20 by the FN type tunnel current. A positive high voltage (10V to 20V) is applied to the control gate electrode 24, and the source region 18a and the drain region 18b are set to 0V. The band diagram at this time is as shown in FIG. Electrons in the semiconductor layer 14 are injected into the first insulating layer 16 by the high electric field, and an FN tunnel current flows. As described in FIG. 2, the relationship between the band gap Eg1 of the semiconductor layer 14 and the band gap Eg2 of the floating gate electrode 20 is Eg1> Eg2. This difference acts as a self-bias so that electrons injected from the channel formation region of the semiconductor layer 14 are accelerated toward the floating gate electrode. Thereby, the electron injection property can be improved.

The energy level of the bottom of the conduction band of the floating gate electrode 20 is at a level lower by ΔE in terms of electronic energy than the energy level of the bottom of the conduction band of the semiconductor layer 14. Therefore, when electrons are injected into the floating gate electrode 20, an internal electric field caused by this energy difference acts. This is realized by the combination of the semiconductor layer 14 and the floating gate electrode 20 as described above. That is, it becomes easy to inject electrons from the semiconductor layer 14 into the floating gate electrode 20, and the write characteristics in the nonvolatile memory element can be improved. This effect is the same when electrons are injected into the floating gate electrode 20 using thermoelectrons.

While electrons are held in the floating gate electrode 20, the threshold voltage of the nonvolatile memory element shifts in the positive direction. This state can be a state in which data “0” is written. FIG. 4 shows a band diagram in the charge holding state. Carriers of the floating gate electrode 20 are energeticly confined by being sandwiched between the first insulating layer 16 and the second insulating layer 22. Although the potential is increased by carriers (electrons) accumulated in the floating gate electrode 20, electrons are not emitted from the floating gate electrode 20 unless energy exceeding the barrier energy is applied to the electrons. In other words, the carriers accumulated in the floating gate electrode can be retained even in the reliability test by being kept at a constant temperature of 150 ° C.

More specifically, it can be said that the carrier of the first floating gate electrode 20a is energeticly confined between the first insulating layer 16 and the second floating gate electrode 20b. In this state, the injected carriers can be prevented from leaking to the second insulating layer 22 side and trapped at the interface. That is, in the erase operation, it is possible to prevent the carriers injected into the floating gate region from remaining and causing an erase failure. However, since the second floating gate electrode 20b also has the ability to accumulate carriers as a floating gate, the first floating gate electrode 20a can be supplemented to function as a floating gate.

In any case, in this case, electrons are not emitted from the floating gate electrode 20 unless energy exceeding the barrier energy is applied to the electrons. The energy level at the bottom of the conduction band of the floating gate electrode 20 is at a level lower by ΔE in terms of electronic energy than the energy level at the bottom of the conduction band of the semiconductor layer 14, and is an energy barrier against electrons. Is formed. This barrier can prevent electrons from flowing out into the semiconductor layer 14 due to the tunnel current.

In order to detect the state in which the data “0” is written, it may be determined by a circuit that the transistor is not turned on when the intermediate potential Vread is applied to the control gate electrode 24. The intermediate potential is an intermediate potential between the threshold voltage Vth1 for data “1” and the threshold voltage Vth2 for data “0” (in this case, Vth1 <Vread <Vth2). Alternatively, as shown in FIG. 6B, it is determined whether or not the nonvolatile memory element is conductive when a bias is applied between the source region 18a and the drain region 18b and the control gate electrode 24 is set to 0V. Can do.

FIG. 7A shows a state in which charges are released from the floating gate electrode 20 and data is erased from the nonvolatile memory element. In this case, a negative bias is applied to the control gate electrode 24 and an FN tunnel current is caused to flow between the semiconductor layer 14 and the floating gate electrode 20. Alternatively, as shown in FIG. 7B, a negative bias is applied to the control gate electrode 24, and a positive high voltage is applied to the source region 18a, thereby generating an FN type tunnel current. Electrons may be extracted to the 18a side.

FIG. 5 shows a band diagram in this erased state. In the erase operation, since the first insulating layer 16 can be formed thin, electrons of the floating gate electrode 20 can be emitted to the semiconductor layer 14 side by the FN tunnel current. Further, holes are more easily injected from the channel formation region of the semiconductor layer 14, and a substantial erasing operation can be performed by injecting into the floating gate electrode 20.

By forming the floating gate electrode 20 from germanium or a germanium compound, the thickness of the first insulating layer 16 can be reduced. Thereby, it becomes easy to inject electrons into the floating gate electrode 20 through the first insulating layer 16 by a tunnel current, and a low voltage operation becomes possible. Furthermore, it becomes possible to store electric charges at a low energy level, and a significant effect can be obtained that electric charges can be stored in a stable state.

In the nonvolatile memory element according to the present invention, as shown in FIGS. 2 and 3, a self-bias is generated between the semiconductor layer 14 and the floating gate electrode 20 as Eg1> Eg2. This relationship is extremely important, and acts to facilitate injection when carriers are injected from the channel formation region of the semiconductor layer into the floating gate electrode. That is, the writing voltage can be lowered. Conversely, it is difficult to release carriers from the floating gate electrode. This acts to improve the storage retention characteristics of the nonvolatile memory element. In addition, by doping the germanium layer as the floating gate electrode with an n-type impurity, the energy level at the bottom of the conduction band can be further lowered, and the self-bias acts to make it easier to inject carriers into the floating gate electrode. Can be made. That is, the write voltage can be lowered and the memory retention characteristics of the nonvolatile memory element can be improved.

As described above, the nonvolatile memory element according to the present invention can easily inject charges from the semiconductor layer to the floating gate electrode, and can prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved.

Various nonvolatile semiconductor memory devices can be obtained using such a nonvolatile memory element. FIG. 8 shows an example of an equivalent circuit of a nonvolatile memory cell array. The memory cell MS01 that stores 1-bit information includes a selection transistor S01 and a nonvolatile memory element M01. The selection transistor S01 is inserted in series between the bit line BL0 and the nonvolatile memory element M01, and the gate is connected to the word line WL1. The gate of the nonvolatile memory element M01 is connected to the word line WL11. When data is written to the nonvolatile memory element M01, when the word line WL1 and the bit line BL0 are set to the H level and the BL1 is set to the L level and a high voltage is applied to the word line WL11, charges are accumulated in the floating gate as described above. The When erasing data, the word line WL1 and the bit line BL0 are set to H level, and a negative high voltage is applied to the word line WL11.

In this memory cell MS01, the select transistor S01 and the non-volatile memory element M01 are formed by the semiconductor layers 30 and 32 formed in an island shape on the insulating surface, respectively, so that no element isolation region is provided. Interference with other selection transistors or nonvolatile memory elements can be prevented. Further, since both the select transistor S01 and the nonvolatile memory element M01 in the memory cell MS01 are n-channel type, by forming both of them in a semiconductor layer separated into one island shape, a wiring for connecting the two elements is formed. Can be omitted.

FIG. 9 shows a NOR-type equivalent circuit in which a nonvolatile memory element is directly connected to a bit line. In this memory cell array, word lines WL and bit lines BL are arranged so as to intersect with each other, and nonvolatile memory elements are arranged at each intersection. In the NOR type, the drain of each nonvolatile memory element is connected to the bit line BL. The sources of the nonvolatile memory elements are commonly connected to the source line SL.

Also in this case, in the memory cell MS01, the non-volatile memory element M01 is formed of the semiconductor layer 32 formed on the insulating surface so as to be separated into islands, so that other non-volatile elements can be provided without providing an element isolation region. Interference with the memory element can be prevented. Further, a plurality of nonvolatile memory elements (for example, M01 to M23 shown in FIG. 9) are handled as one block, and these nonvolatile memory elements are formed by a semiconductor layer separated into one island shape, so that a block unit. The erase operation can be performed with.

The NOR type operation is, for example, as follows. In data writing, the source line SL is set to 0 V, a high voltage is applied to the word line WL selected for data writing, and a potential corresponding to data “0” and “1” is applied to the bit line BL. For example, H level and L level potentials are applied to the bit line BL for “0” and “1”, respectively. In order to write “0” data, in the nonvolatile memory element to which H level is given, hot electrons are generated in the vicinity of the drain, and this is injected into the floating gate. In the case of “1” data, such electron injection does not occur.

In a memory cell to which “0” data is given, hot electrons are generated in the vicinity of the drain due to a strong lateral electric field between the drain and the source, and this is injected into the floating gate. As a result, the state where electrons are injected into the floating gate and the threshold voltage becomes high is “0”. In the case of “1” data, hot electrons are not generated, electrons are not injected into the floating gate, and a low threshold voltage state, that is, an erased state is maintained.

When erasing data, a positive voltage of about 10 V is applied to the source line SL, and the bit line BL is left floating. Then, a negative high voltage is applied to the word line WL (a negative high voltage is applied to the control gate), and electrons are extracted from the floating gate. As a result, the data “1” is erased.

For data reading, the source line SL is set to 0V and the bit line BL is set to about 0.8V, and the selected word line WL is set to an intermediate value between the threshold values of data “0” and “1”. A voltage is applied, and the presence / absence of current draw in the nonvolatile memory element is determined by a sense amplifier connected to the bit line BL.

FIG. 10 shows an equivalent circuit of the NAND memory cell array. A NAND cell NS1 in which a plurality of nonvolatile memory elements are connected in series is connected to the bit line BL. A plurality of NAND cells gather to constitute a block BLK. The block BLK1 shown in FIG. 10 has 32 word lines (word lines WL0 to LW31). The nonvolatile memory elements located in the same row of the block BLK1 are commonly connected to word lines corresponding to this row.

In this case, since the selection transistors S1 and S2 and the nonvolatile memory elements M0 to M31 are connected in series, they may be formed as a single semiconductor layer 34. Accordingly, wiring for connecting the nonvolatile memory elements can be omitted, so that integration can be achieved. Further, it is possible to easily separate the adjacent NAND cells. Further, the semiconductor layer 36 of the select transistors S1 and S2 and the semiconductor layer 38 of the NAND cell may be formed separately. When performing an erasing operation for extracting charges from the floating gates of the nonvolatile memory elements M0 to M31, the erasing operation can be performed in units of the NAND cells. Further, the nonvolatile memory elements (for example, the row of M30) commonly connected to one word line may be formed by one semiconductor layer 40.

The write operation is executed after the NAND cell NS1 is in the erased state, that is, the threshold value of each nonvolatile memory element of the NAND cell NS1 is in a negative voltage state. Writing is performed in order from the memory element M0 on the source line SL side. An example of writing to the memory element M0 is as follows.

In FIG. 11A, when “0” is written, for example, Vcc (power supply voltage) is applied to the selection gate line SG2 to turn on the selection transistor S2 and to set the bit line BL0 to 0 V (ground voltage). The selection gate line SG1 is set to 0V, and the selection transistor S1 is turned off. Next, the word line WL0 of the nonvolatile memory element M0 is set to the high voltage Vpgm (about 20V), and the other word lines are set to the intermediate voltage Vpass (about 10V). Since the voltage of the bit line BL0 is 0V, the potential of the channel formation region of the selected nonvolatile memory element M0 is 0V. Since the potential difference between the word line WL0 and the channel formation region is large, electrons are injected into the floating gate of the nonvolatile memory element M0 by the FN tunnel current as described above. As a result, the threshold voltage of the nonvolatile memory element M0 becomes positive (a state in which “0” is written).

On the other hand, when "1" is written, the bit line BL is set to Vcc (power supply voltage), for example, as shown in FIG. Since the voltage of the selection gate line SG2 is Vcc, the selection transistor S2 is cut off when Vcc minus Vth (Vcc−Vth) with respect to the threshold voltage Vth of the selection transistor S2. Accordingly, the channel formation region of the nonvolatile memory element M0 is in a floating state. Next, when the high voltage Vpgm (20 V) is applied to the word line WL0 and the intermediate voltage Vpass (10 V) is applied to the other word lines, the capacitive coupling between each word line and the channel formation region causes the channel formation region. The voltage rises from Vcc-Vth and becomes about 8V, for example. Since the voltage of the channel formation region is boosted to a high voltage, the potential difference between the word line WL0 and the channel formation region is small unlike the case of writing “0”. Therefore, electron injection due to the FN tunnel current does not occur in the floating gate of the nonvolatile memory element M0. Therefore, the threshold value of the nonvolatile memory element M0 is maintained in a negative state (a state in which “1” is written).

When performing the erase operation, as shown in FIG. 12A, a negative high voltage (Vers) is applied to all the word lines in the selected block. The bit line BL and the source line SL are brought into a floating state. Thereby, electrons in the floating gate are emitted to the semiconductor layer by the tunnel current in all the memory cells of the block. As a result, the threshold voltages of these memory cells shift in the negative direction.

In the reading operation shown in FIG. 12B, the voltage Vr (for example, 0 V) of the word line WL0 of the nonvolatile memory element M0 selected for reading is used, and the word lines WL1 to WL31 and the selection gate lines of the unselected memory cells. SG1 and SG2 are read intermediate voltages Vread that are slightly higher than the power supply voltage. That is, as shown in FIG. 13, the memory elements other than the selected memory element function as transfer transistors. Thus, it is detected whether or not a current flows through the nonvolatile memory element M0 selected for reading. That is, when the data stored in the nonvolatile memory element M0 is “0”, the nonvolatile memory element M0 is off, and the bit line BL is not discharged. On the other hand, in the case of “1”, since the nonvolatile memory element M0 is turned on, the bit line BL is discharged.

FIG. 14 shows an example of a circuit block diagram of a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, the memory cell array 52 and the peripheral circuit 54 are formed on the same substrate. The memory cell array 52 has a configuration as shown in FIG. 8, FIG. 9, and FIG. The configuration of the peripheral circuit 54 is as follows.

A row decoder 62 for selecting a word line and a column decoder 64 for selecting a bit line are provided around the memory cell array 52. The address is sent to the control circuit 58 via the address buffer 56, and the internal row address signal and the internal column address signal are transferred to the row decoder 62 and the column decoder 64, respectively.

For writing and erasing data, a potential obtained by boosting the power supply potential is used. Therefore, a booster circuit 60 controlled by the control circuit 58 according to the operation mode is provided. The output of the booster circuit 60 is supplied to the word line WL and the bit line BL via the row decoder 62 and the column decoder 64. The sense amplifier 66 receives the data output from the column decoder 64. Data read by the sense amplifier 66 is held in the data buffer 68, and the data is randomly accessed under the control of the control circuit 58 and output via the data input / output buffer 70. The write data is temporarily held in the data buffer 68 via the data input / output buffer 70 and transferred to the column decoder 64 under the control of the control circuit 58.

Thus, in the nonvolatile semiconductor memory device, it is necessary to use a potential different from the power supply potential in the memory cell array 52. Therefore, it is desirable that at least the memory cell array 52 and the peripheral circuit 54 are electrically isolated from each other. In this case, insulation isolation can be easily performed by forming a nonvolatile memory element and a transistor of a peripheral circuit with a semiconductor layer formed on an insulating surface as in an embodiment described below. Thus, a non-volatile semiconductor memory device with no malfunction and low power consumption can be obtained.

Hereinafter, the nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to examples. In the structure of the present invention described below, reference numerals indicating the same elements are used in common in different drawings, and repetitive description in that case may be omitted.

In this embodiment, an example of a nonvolatile semiconductor memory device will be described with reference to the drawings. In the following description, in a nonvolatile semiconductor memory device, a non-volatile memory element that forms a memory unit, and an element such as a transistor that forms a logic unit that is provided on the same substrate as the memory unit and controls the memory unit. Are shown simultaneously.

First, an equivalent circuit of a memory portion in the nonvolatile semiconductor memory device is shown in FIG.

In the memory portion shown in this embodiment, a plurality of memory cells each including a selection transistor and a nonvolatile memory element are provided. In FIG. 8, one memory cell is formed by the select transistor S01 and the nonvolatile memory element M01. Similarly, the selection transistor S02 and the nonvolatile memory element M02, the selection transistor S03 and the nonvolatile memory element M03, the selection transistor S11 and the nonvolatile memory element M11, the selection transistor S12 and the nonvolatile memory element M12, and the selection transistor S13 and the nonvolatile transistor A memory cell is formed by the volatile memory element M13.

The gate electrode of the selection transistor S01 is connected to the word line WL1, one of the source and the drain is connected to the bit line BL0, and the other is connected to the source or the drain of the nonvolatile memory element M01. The gate electrode of the nonvolatile memory element M01 is connected to the word line WL11, one of the source and the drain is connected to the source or the drain of the selection transistor S01, and the other is connected to the source line SL.

Note that since the selection transistor provided in the memory portion has a higher driving voltage than the transistor provided in the logic portion, the gate insulating film of the transistor provided in the memory portion and the transistor provided in the logic portion are formed with different thicknesses. It is preferable. For example, it is preferable to provide a thin film transistor with a thin gate insulating film when the driving voltage is small and it is desired to reduce the variation in threshold voltage. When the driving voltage is large and the withstand voltage performance of the gate insulating film is required, the gate insulating film is It is preferable to provide a thick thin film transistor.

Therefore, in this embodiment, an insulating layer having a small film thickness is formed for a transistor in the logic portion where the driving voltage is small and the variation in threshold voltage is small, and the withstand voltage performance of the gate insulating film is required because the driving voltage is large. A case where an insulating layer having a large film thickness is formed for a transistor in a memory portion will be described below with reference to the drawings. 32 to 34 are top views, and FIGS. 18 to 21 are cross-sectional views taken along lines AB, CD, EF, and GH in FIGS. 32 to 34. Yes. In addition, a thin film transistor provided in the logic portion is shown between AB and CD, a non-volatile memory element provided in the memory portion is shown between EF, and a thin film transistor provided in the memory portion is shown between GH. Show. In this embodiment, a thin film transistor provided between A and B is a p-channel type, a thin film transistor provided between C and D, a thin film transistor provided between GH and an n channel type, and a carrier of a nonvolatile memory element provided between EFs. Although the case where movement is performed by electrons will be described, the nonvolatile semiconductor device of the present invention is not limited to this.

First, island-shaped semiconductor layers 104, 106, 108, 110 are formed over the substrate 100 with the insulating layer 102 interposed therebetween, and the first insulating layer is formed so as to cover the island-shaped semiconductor layers 104, 106, 108, 110. 112, 114, 116, and 118 are formed, respectively. Then, charge storage layers 120 and 123 functioning as floating gates of a nonvolatile memory element to be completed later are stacked so as to cover the first insulating layers 112, 114, 116, and 118 (see FIG. 18A). ). The island-shaped semiconductor layers 104, 106, 108, and 110 are materials whose main component is silicon (Si) using a sputtering method, an LPCVD method, a plasma CVD method, or the like over the insulating layer 102 formed in advance on the substrate 100. An amorphous semiconductor layer can be formed using (for example, Si _x Ge _1-x ) or the like, and the amorphous semiconductor layer can be crystallized and then selectively etched. The crystallization of the amorphous semiconductor layer may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed.

In the case where the semiconductor layer is crystallized or recrystallized by laser light irradiation, an LD-excited continuous wave (CW) laser (YVO ₄ , second harmonic (wavelength 532 nm)) is used as a laser light source. Can be used. The second harmonic is not particularly limited to the second harmonic, but the second harmonic is superior to higher harmonics in terms of energy efficiency. When the semiconductor layer is irradiated with the CW laser, energy is continuously given to the semiconductor layer. Therefore, once the semiconductor layer is in a molten state, the molten state can be continued. Furthermore, the solid-liquid interface of the semiconductor layer can be moved by scanning with a CW laser, and crystal grains that are long in one direction can be formed along the direction of this movement. The solid laser is used because the output stability is higher than that of a gas laser or the like, and stable processing is expected. Note that not only the CW laser but also a pulse laser having a repetition frequency of 10 MHz or more can be used. If a pulse laser with a high repetition frequency is used, the semiconductor layer can always remain in a molten state if the laser pulse interval is shorter than the time from when the semiconductor layer melts until it solidifies. A semiconductor layer including crystal grains that are long in one direction can be formed. Other CW lasers and pulse lasers with a repetition frequency of 10 MHz or more can also be used. For example, examples of the gas laser include an Ar laser, a Kr laser, and a CO ₂ laser. Examples of the solid-state laser include a YAG laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a Y ₂ O ₃ laser, and a YVO ₄ laser. YAG laser, Y ₂ O ₃ laser, GdVO ₄ laser, YVO ₄ laser, and the like are also called ceramic lasers. Examples of the metal vapor laser include a helium cadmium laser. In addition, it is preferable to emit laser light in TEM ₀₀ (single transverse mode) in a laser oscillator because energy uniformity of a linear beam spot obtained on the irradiated surface can be improved. In addition, a pulsed excimer laser may be used.

The substrate 100 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a ceramic substrate or a stainless steel substrate), and a semiconductor substrate such as a silicon substrate. In addition, as the plastic substrate, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfine (PES), or acrylic can be selected.

The insulating layer 102 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y)), or silicon nitride oxide (SiNxOy, (x> y)) using a CVD method, a sputtering method, or the like. It forms using. For example, in the case where the insulating layer 102 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating layer and a silicon oxynitride film may be formed as the second insulating layer. Alternatively, a silicon nitride film may be formed as the first insulating layer, and a silicon oxide film may be formed as the second insulating layer. In this manner, by forming the insulating layer 102 functioning as a blocking layer, alkali metal such as Na or alkaline earth metal from the substrate 100 can be prevented from adversely affecting the element formed thereon. Note that the insulating layer 102 may be omitted when quartz is used for the substrate 100.

The first insulating layers 112, 114, 116, and 118 can be formed by performing heat treatment, plasma treatment, or the like on the semiconductor layers 104, 106, 108, and 110. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layers 104, 106, 108, and 110 by high-density plasma treatment, an oxide film and a nitride film are formed on the semiconductor layers 104, 106, 108, and 110, respectively. Alternatively, the first insulating layers 112, 114, 116, and 118 which are to be oxynitride films are formed. In addition, you may form by plasma CVD method or a sputtering method.

For example, in the case where a semiconductor layer containing silicon as a main component is used as the semiconductor layers 104, 106, 108, and 110, oxidation treatment or nitridation treatment is performed by high-density plasma treatment, the first insulating layers 112, 114, 116, and 118 As a result, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is formed. Further, after the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the semiconductor layers 104, 106, 108, and 110, and a film containing oxygen and nitrogen (hereinafter referred to as a “silicon oxynitride film”) is formed over the silicon oxide film. The first insulating layers 112, 114, 116, and 118 are films in which a silicon oxide film and a silicon oxynitride film are stacked.

In this example, the first insulating layers 112, 114, 116, and 118 are formed with a thickness of 1 nm to 10 nm, preferably 1 nm to 5 nm. For example, the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment to form a silicon oxide film with a thickness of about 5 nm on the surfaces of the semiconductor layers 104, 106, 108, and 110, and then the high-density plasma treatment. Nitriding is performed to form a silicon oxynitride film having a thickness of about 2 nm on the surface of the silicon oxide film. In this case, the film thickness of the silicon oxide film formed on the surface of the semiconductor layers 104, 106, 108, 110 is approximately 3 nm. This is because the silicon oxynitride film is reduced by the amount formed. At this time, it is preferable that the oxidation treatment and the nitriding treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

Note that in the case where the semiconductor layer is oxidized by high-density plasma treatment, an atmosphere containing oxygen (for example, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr And at least one of Xe), oxygen, or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas atmosphere. On the other hand, in the case of nitriding a semiconductor layer by high-density plasma treatment, an atmosphere containing nitrogen (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe)) Under nitrogen, hydrogen, and rare gas atmosphere, or NH ₃ and rare gas atmosphere).

As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. When the high-density plasma treatment is performed in a rare gas atmosphere, the first insulating layers 112, 114, 116, and 118 are formed of at least one of rare gases (He, Ne, Ar, Kr, and Xe) used for the plasma treatment. In the case of using Ar, the first insulating layers 112, 114, 116, and 118 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (in this example, the semiconductor layers 104, 106, 108, and 110) formed on the substrate 100 is low, Damage can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower than the strain point of the glass substrate by 100 ° C. or more, the oxidation or nitridation treatment can be sufficiently performed. As a frequency for forming plasma, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

In this embodiment, when an object to be processed is oxidized by high-density plasma treatment, a mixed gas of oxygen (O ₂ ), hydrogen (H ₂ ), and argon (Ar) is introduced. The mixed gas used here may be introduced with oxygen at 0.1 sccm to 100 sccm, hydrogen at 0.1 sccm to 100 sccm, and argon at 100 sccm to 5000 sccm. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

In addition, when performing nitriding treatment by high-density plasma treatment, a mixed gas of nitrogen (N ₂ ) and argon (Ar) is introduced. The mixed gas used here may be introduced at 20 sccm to 2000 sccm for nitrogen and 100 sccm to 10000 sccm for argon. For example, nitrogen may be introduced at 200 sccm and argon at 1000 sccm.

In this embodiment, the first insulating layer 116 formed over the semiconductor layer 108 provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating layer 116 is, the easier it is for the tunnel current to flow and the higher speed operation of the memory becomes possible. In addition, as the thickness of the first insulating layer 116 is thinner, charge can be accumulated in a floating gate formed later at a lower voltage, so that power consumption of the semiconductor device can be reduced. Therefore, the first insulating layers 112, 114, 116, and 118 are preferably formed thin.

In general, there is a thermal oxidation method as a method for forming a thin insulating layer over a semiconductor layer. However, when a substrate having a sufficiently low melting point such as a glass substrate is used as the substrate 100, the first method is performed by the thermal oxidation method. It is very difficult to form the insulating layers 112, 114, 116, and 118. In addition, an insulating layer formed by CVD or sputtering has a problem that a sufficient breakdown voltage cannot be obtained because the film contains defects, and defects such as pinholes are caused when the film is formed thin. There are problems that arise. In addition, in the case where the insulating layer is formed by a CVD method or a sputtering method, the end portion of the semiconductor layer is not sufficiently covered, and the conductive layer and the like that are formed later on the first insulating layer 116 and the semiconductor layer leak. There is a case. Therefore, as shown in this embodiment, by forming the first insulating layers 112, 114, 116, and 118 by high-density plasma treatment, an insulating layer that is denser than the insulating layer formed by CVD or sputtering is used. The end portions of the semiconductor layers 104, 106, 108, 110 can be sufficiently covered with the first insulating layers 112, 114, 116, 118. As a result, high-speed operation and charge retention characteristics as a memory can be improved. Note that in the case where the first insulating layers 112, 114, 116, and 118 are formed by a CVD method or a sputtering method, high-density plasma treatment is performed after forming the insulating layer, and the surface of the insulating layer is oxidized or nitrided. Alternatively, oxynitriding treatment is preferably performed.

The charge storage layers 120 and 123 are formed with a stacked structure of a film containing germanium such as germanium (Ge) or a silicon germanium alloy and a film containing silicon (silicon). In this example, a plasma CVD method is performed as the charge storage layer 120 in an atmosphere containing a germanium element (for example, GeH ₄ ), so that a film containing germanium as a main component is 1 nm to 20 nm, preferably 1 nm to 10 nm. After forming the film, a film containing silicon as a main component has a thickness of 1 nm to 50 nm, preferably 1 nm to 20 nm by performing plasma CVD in an atmosphere containing silicon element (for example, SiH ₄ ) as the charge storage layer 123. By forming in the following, a stacked structure of germanium and silicon is provided. Thus, a film containing germanium having a smaller energy gap than silicon is formed over the semiconductor layer with the first insulating layer functioning as a tunnel oxide film formed using a material containing silicon as a main component as the semiconductor layer. When the charge storage layer is provided, the second barrier formed by the insulating layer for the charge of the charge storage layer is higher in energy than the first barrier formed by the insulating layer for the charge of the semiconductor layer. As a result, charge can be easily injected from the semiconductor layer into the charge storage layer, and the charge can be prevented from disappearing from the charge storage layer. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. A stacked structure including the charge storage layer 120 and the charge storage layer 123 formed over the semiconductor layer 108 provided in the memory portion functions as a floating gate in a nonvolatile memory element to be completed later.

Next, the stacked structure including the first insulating layers 112, 114, and 118, the charge storage layer 120, and the charge storage layer 123 formed over the semiconductor layers 104, 106, and 110 is selectively removed, and the semiconductor layer 108 is removed. The stacked structure including the first insulating layer 116, the charge storage layer 120, and the charge storage layer 123 formed thereon is left. In this example, a stacked structure including the semiconductor layer 108, the first insulating layer 116, the charge storage layer 120, and the charge storage layer 123 provided in the memory portion is selectively covered with a resist, and the semiconductor layers 104, 106, and 110 are formed. The stacked structure including the first insulating layers 112, 114, 118, the charge storage layer 120, and the charge storage layer 123 is selectively removed by etching (see FIG. 18B).

Next, a resist 122 is formed so as to selectively cover a part of the stacked structure including the semiconductor layers 104, 106, and 110 and the charge storage layer 120 and the charge storage layer 123 formed above the semiconductor layer 108. The charge storage layers 120 and 123 not covered with the resist 122 are selectively removed by etching, so that a part of the stacked structure including the charge storage layer 120 and the charge storage layer 123 remains and functions as a floating gate. A stacked structure including the charge storage layer 121 and the charge storage layer 125 is formed (see FIGS. 18C and 32).

Next, an impurity region is formed in a specific region of the semiconductor layer 110. In this example, after removing the resist 122, a resist 124 is formed so as to selectively cover the semiconductor layers 104, 106, and 108 and part of the semiconductor layer 110, and the semiconductor layer 110 not covered with the resist 124 is formed. By introducing an impurity element, an impurity region 126 is formed (see FIG. 19A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is introduced into the semiconductor layer 110 as the impurity element.

Next, the semiconductor layer 104, 106, 110, the first insulating layer 116 formed above the semiconductor layer 108, and the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate are covered. The second insulating layer 128 is formed (see FIG. 19B).

The second insulating layer 128 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)), or the like using a CVD method, a sputtering method, or the like. These insulating materials are used to form a single layer or a stacked layer. For example, when the second insulating layer 128 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 nm to 50 nm by a CVD method. In the case where the second insulating layer 128 is provided with a three-layer structure, a silicon oxynitride film is formed as the first insulating layer, a silicon nitride film is formed as the second insulating layer, A silicon oxynitride film is formed as the insulating layer. In addition, germanium oxide or nitride may be used for the second insulating layer 128.

Note that the second insulating layer 128 formed above the semiconductor layer 108 functions as a control insulating layer in a nonvolatile memory element to be completed later, and the second insulating layer 128 formed above the semiconductor layer 110 is It functions as a gate insulating film in a transistor to be completed later.

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the semiconductor layers 108 and 110, and the second insulating layer 128 formed over the semiconductor layers 104 and 106 is formed. This is selectively removed (see FIG. 19C).

Next, third insulating layers 132 and 134 are formed so as to cover the semiconductor layers 104 and 106, respectively (see FIG. 20A).

The third insulating layers 132 and 134 are formed by any one of the methods described for forming the first insulating layers 112, 114, 116, and 118. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layers 104, 106, 108, and 110 by high-density plasma treatment, a silicon oxide film, a nitride film, or oxynitridation is performed on the semiconductor layers 104 and 106, respectively. Third insulating layers 132 and 134 to be films are formed.

In this example, the third insulating layers 132 and 134 are formed with a thickness of 1 nm to 20 nm, preferably 1 nm to 10 nm. For example, the semiconductor layers 104 and 106 are oxidized by high-density plasma treatment to form a silicon oxide film on the surfaces of the semiconductor layers 104 and 106, and then nitridation is performed by high-density plasma treatment to oxidize the surface of the silicon oxide film. A silicon nitride film is formed. In this case, the surface of the second insulating layer 128 formed above the semiconductor layers 108 and 110 is also subjected to oxidation treatment or nitridation treatment, so that an oxide film or an oxynitride film is formed. The third insulating layers 132 and 134 formed over the semiconductor layers 104 and 106 function as gate insulating films in transistors to be completed later.

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the semiconductor layers 104 and 106 and the second insulating layer 128 formed above the semiconductor layers 108 and 110 (see FIG. (See FIG. 20B). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

The conductive films 136 and 138 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

In this example, the conductive film 136 is formed using tantalum nitride, and the conductive film 138 is formed using tungsten over the stacked structure. In addition, a single layer or stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used as the conductive film 136, and a single layer or stacked film selected from tantalum, molybdenum, or titanium is used as the conductive film 138. Can be used.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left over part of the semiconductor layers 104, 106, 108, and 110. Conductive films 140, 142, 144, and 146 each functioning as a gate electrode are formed (see FIGS. 20C and 33). Note that the conductive film 144 formed over the semiconductor layer 108 provided in the memory portion functions as a control gate in a nonvolatile memory element to be completed later. In addition, the conductive films 140, 142, and 146 function as gate electrodes in transistors that are completed later.

Next, a resist 148 is selectively formed so as to cover the semiconductor layer 104, and an impurity element is introduced into the semiconductor layers 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 21A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 21A, an impurity element 152 and a channel formation region 150 which form a source region or a drain region are formed in the semiconductor layer 106 by introducing an impurity element. In the semiconductor layer 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the semiconductor layer 110, an impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

Further, the low-concentration impurity region 158 formed in the semiconductor layer 108 penetrates the stacked structure including the charge storage layer 121 and the charge storage layer 125 in which the impurity element introduced in FIG. 21A functions as a floating gate. It is formed. Therefore, in the semiconductor layer 108, a channel formation region 154 is formed in a region overlapping with both the stacked structure including the conductive film 144, the charge storage layer 121, and the charge storage layer 125, and the stack including the charge storage layer 121 and the charge storage layer 125 is formed. A low concentration impurity region 158 is formed in a region that overlaps with the structure and does not overlap with the conductive film 144, and a high concentration impurity region 156 exists in a region that does not overlap with both the stacked structure including the charge storage layer 121 and the charge storage layer 125 and the conductive film 144. It is formed.

Next, a resist 166 is selectively formed so as to cover the semiconductor layers 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the semiconductor layer 104 using the resist 166 and the conductive film 140 as a mask ( (See FIG. 21B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (for example, boron (B)) having a conductivity type different from that of the impurity element introduced into the semiconductor layers 106, 108, and 110 in FIG. As a result, an impurity region 170 and a channel formation region 168 that form a source region or a drain region are formed in the semiconductor layer 104.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the semiconductor layers 104 and 106 are formed over the insulating layer 172. , 108, and 110, conductive films 174 that are electrically connected to the impurity regions 170, 152, 156, and 162, respectively, are formed (see FIGS. 21C and 34).

The insulating layer 172 is formed by CVD, sputtering, or the like using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)). An insulating layer having oxygen or nitrogen such as a film, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin A single layer or a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

The conductive film 174 is formed by a CVD method, a sputtering method, or the like by aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper ( Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 174 has, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. Adopt it. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive film 174 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

In this embodiment, the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate is formed so as to cross over the end portion of the semiconductor layer 108 (see FIG. 32). Accordingly, a stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate through the first insulating layer 116 functioning as a tunnel insulating layer is formed at an end portion of the semiconductor layer 108 provided in an island shape. Is formed. Therefore, there is a possibility that the characteristics of the nonvolatile memory element may be affected by poor coverage of the first insulating layer 116 or accumulation of some charges accompanying the manufacturing process. Therefore, in the above structure, the impurity region 194 is selectively provided in an end portion of the semiconductor layer 108 and in a region overlapping with the stacked structure including the charge storage layer 121 and the charge storage layer 125 and a region in the vicinity thereof. It is also possible (see FIG. 35).

The impurity region 194 is provided so as to have a different conductivity type from the impurity region 156 functioning as a source region or a drain region of the semiconductor layer 108. For example, when the impurity region 156 is provided with a conductivity type indicating n-type, the impurity region 194 is provided with a conductivity type indicating p-type.

In FIG. 35, the impurity region 194 is provided at the vicinity of the stacked region including the charge storage layer 121 and the charge storage layer 125 which are the end portions of the semiconductor layer 108 and function as floating gates, and in the vicinity thereof. However, the present invention is not limited to this. For example, the impurity region 194 may be provided only in a region that is an end portion of the semiconductor layer 108 and overlaps with a stacked structure including the charge storage layer 121 and the charge storage layer 125, or may be provided in the entire outer peripheral portion of the end portion of the semiconductor layer 108. Can be provided. Further, for example, the impurity region 194 is provided in the vicinity of a region overlapping with the stacked structure including the charge storage layer 121 and the charge storage layer 125 at the end portion of the semiconductor layer 108 and includes the charge storage layer 121 and the charge storage layer 125. A structure that is not provided below the structure may be employed (see FIG. 36).

In this manner, by providing the impurity region 194, the adjacent portion of the impurity region 156 and the impurity region 194 has a high resistance due to the pn junction. It is possible to suppress the influence on the characteristics of the nonvolatile memory element due to accumulation or the like.

  In this example, the nonvolatile memory element between E and F has been described. Similarly, the transistors provided between A and B, between CD and GH are also illustrated in FIGS. As described above, an impurity region 194 may be provided.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor layer to the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a case where a plurality of nonvolatile memory elements are provided in one island-like semiconductor layer in the structure shown in Embodiment 1 will be described with reference to the drawings. In addition, when referring to the same thing as the said Example, it shows using the same code | symbol and abbreviate | omits description. 37 shows a top view, and FIG. 38 shows a cross-sectional view between EF and GH in FIG.

The nonvolatile semiconductor memory device shown in this embodiment includes island-shaped semiconductor layers 200a and 200b that are electrically connected to the bit lines BL0 and BL1, respectively. The island-shaped semiconductor layers 200a and 200b are provided in the island-shaped semiconductor layers 200a and 200b, respectively. A plurality of nonvolatile memory elements are provided (see FIGS. 37 and 38). Specifically, in the semiconductor layer 200a, a NAND cell 202a having a plurality of nonvolatile memory elements M0 to M31 is provided between the select transistors S01 and S02. In the semiconductor layer 200b, a NAND cell 202b having a plurality of nonvolatile memory elements is provided between the select transistors. Further, by providing the semiconductor layers 200a and 200b separately, the adjacent NAND cells 202a and NAND cells 202b can be insulated and separated.

Further, by providing a plurality of nonvolatile memory elements in one island-like semiconductor layer, the nonvolatile memory elements can be more integrated and a large-capacity nonvolatile semiconductor memory device can be formed.

In this embodiment, as in the first embodiment, the gate insulating layer of the selection transistor of the NAND cell is thickened so that a higher voltage is applied than in the logic portion in the write and erase operations for the nonvolatile memory element. Even in this case, the stability of the operation can be improved. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor layer to the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. With such a configuration, the nonvolatile semiconductor memory device of this embodiment can stabilize the operation of the nonvolatile semiconductor memory device.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a semiconductor device different from that in Embodiment 1 is described with reference to drawings. In addition, when referring to the same thing as the said Example, it shows using the same code | symbol and abbreviate | omits description. 22 to 24, the thin film transistors provided in the logic portion are shown between AB and CD, the non-volatile memory elements provided in the memory portion are shown between EF, and between GH are shown. A thin film transistor provided in a memory portion is shown.

First, until the formation of FIG. 18C, similarly, the resist 122 is removed, and the semiconductor layers 104, 106, and 110, the first insulating layer 116 formed above the semiconductor layer 108, the charge storage layer 121, and A second insulating layer 128 is formed so as to cover the stacked structure including the charge accumulation layer 125 (see FIG. 22A).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the semiconductor layers 108 and 110, and the second insulating layer 128 formed over the semiconductor layers 104 and 106 is formed. This is selectively removed (see FIG. 22B).

Next, third insulating layers 132 and 134 are formed so as to cover the semiconductor layers 104 and 106, respectively (see FIG. 22C).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the semiconductor layers 104 and 106 and the second insulating layer 128 formed above the semiconductor layers 108 and 110 (see FIG. (See FIG. 23A). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left over part of the semiconductor layers 104, 106, 108, and 110. Conductive films 140, 142, 144, and 146 each functioning as a gate electrode are formed (see FIG. 23B). Note that the conductive film 140 includes conductive films 182 a and 184 a provided by being stacked using the remaining conductive films 136 and 138. In this embodiment, the width of the conductive film 182a formed below in the conductive film 140 (width with respect to a direction substantially parallel to the direction in which carriers flow in the channel formation region (the direction connecting the source region and the drain region)). The width is larger than the width of the conductive film 184a. Similarly, the conductive film 142 is formed by sequentially stacking a conductive film 182b and a width 184b smaller than the conductive film 182b, and the conductive film 144 is formed by sequentially stacking a conductive film 182c and a width 184c smaller than the conductive film 182c. In the conductive film 146, the conductive film 182d and the conductive film 182d having a smaller width than the conductive film 182d are sequentially stacked.

Next, a resist 148 is selectively formed so as to cover the semiconductor layer 104, and an impurity element is introduced into the semiconductor layers 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 23C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 23C, by introducing an impurity element, a high concentration impurity region 152 that forms a source region or a drain region, a low concentration impurity region 186 that forms an LDD region, and a channel formation region 150 are formed in the semiconductor layer 106. It is formed. In the semiconductor layer 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the semiconductor layer 110, a high-concentration impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

The low-concentration impurity region 186 formed in the semiconductor layer 106 is formed when the impurity element introduced in FIG. 23C penetrates the conductive film 182b. Accordingly, in the semiconductor layer 106, a channel formation region 150 is formed in a region overlapping with both the conductive film 182b and the conductive film 184b, and a low concentration impurity region 186 is formed in a region overlapping with the conductive film 182b and not overlapping with the conductive film 184b. A high concentration impurity region 152 is formed in a region which does not overlap with both the conductive film 182b and the conductive film 184b.

The low-concentration impurity region 158 formed in the semiconductor layer 108 is formed by the impurity element introduced in FIG. 23C penetrating through the stacked structure including the charge storage layer 121 and the charge storage layer 125. Accordingly, in the semiconductor layer 108, a channel formation region 154 is formed in a region overlapping with both the stacked structure including the conductive film 182c, the charge storage layer 121, and the charge storage layer 125, and the stack including the charge storage layer 121 and the charge storage layer 125 is formed. A low concentration impurity region 158 is formed in a region that overlaps with the structure and does not overlap with the conductive film 182c, and a high concentration impurity region 156 exists in a region that does not overlap with both the stacked structure including the charge storage layer 121 and the charge storage layer 125 and the conductive film 182c. It is formed. Note that in the case where the conductive film 182c is thin, the semiconductor layer 108 overlaps with both the stacked structure including the conductive film 182c, the charge storage layer 121, and the charge storage layer 125 and does not overlap with the conductive film 184c. In some cases, a low concentration impurity region having a concentration equal to or lower than that of the low concentration impurity region 158 may be formed.

The low-concentration impurity region 164 formed in the semiconductor layer 110 is formed by the impurity element introduced in FIG. 23C penetrating through the conductive film 182d. Accordingly, in the semiconductor layer 110, a channel formation region 160 is formed in a region overlapping with both the conductive film 182d and the conductive film 184d, and a low concentration impurity region 164 is formed in a region overlapping with the conductive film 182d and not overlapping with the conductive film 184d. A high concentration impurity region 162 is formed in a region which does not overlap with both the conductive film 182d and the conductive film 184d.

Next, a resist 166 is selectively formed so as to cover the semiconductor layers 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the semiconductor layer 104 using the resist 166 and the conductive film 140 as a mask ( (See FIG. 24A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the semiconductor layers 106, 108, and 110 in FIG. 23C is introduced. As a result, a high concentration impurity region 170 that forms a source region or a drain region, a low concentration impurity region 188 that forms an LDD region, and a channel formation region 168 are formed in the semiconductor layer 104.

The low-concentration impurity regions 188 formed in the semiconductor layer 104 are formed by the impurity element introduced in FIG. 24A penetrating through the conductive film 182a. Accordingly, in the semiconductor layer 104, a channel formation region 168 is formed in a region overlapping with both the conductive film 182a and the conductive film 184a, and a low-concentration impurity region 188 is formed in a region overlapping with the conductive film 182a and not overlapping with the conductive film 184a. A high concentration impurity region 170 is formed in a region which does not overlap with both the conductive film 182a and the conductive film 184a.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the semiconductor layers 104 and 106 are formed over the insulating layer 172. , 108, and 110, conductive films 174 that are electrically connected to the impurity regions 170, 152, 156, and 162, respectively, are formed (see FIG. 24B).

Even in the structure shown in this embodiment, the impurity region 194 may be provided as shown in FIGS.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor layer to the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a semiconductor device different from that in Embodiment 1 or 2 will be described with reference to drawings. In addition, when referring to the same thing as the said Example 1 or 2, it shows using the same code | symbol and abbreviate | omits description. 39 to 41 are top views, and FIGS. 28 to 30 are cross-sectional views taken along lines AB, CD, EF, and GH in FIGS. 39 to 41. Yes. In addition, a thin film transistor provided in the logic portion is shown between AB and CD, a non-volatile memory element provided in the memory portion is shown between EF, and a thin film transistor provided in the memory portion is shown between GH. Show.

First, after the formation up to FIG. 18C of the first embodiment, an impurity region 190 is formed by introducing an impurity element into the semiconductor layer 108 using the resist 122 as a mask (see FIG. 28A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is introduced into the semiconductor layer 108 as the impurity element. Note that in this embodiment, the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate is formed to have a width smaller than that of the semiconductor layer 108. That is, the stacked structure including the charge storage layer 121 and the charge storage layer 125 does not overcome the semiconductor layer 108 (the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate always overlaps). (See FIG. 39).

Next, the second insulating layer is formed so as to cover the semiconductor layers 104, 106, 110, the first insulating layer 116 formed above the semiconductor layer 108, the stacked structure including the charge storage layer 121 and the charge storage layer 125. 128 is formed (see FIG. 28B).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the semiconductor layers 108 and 110, and the second insulating layer 128 formed over the semiconductor layers 104 and 106 is formed. This is selectively removed (see FIG. 28C).

Next, third insulating layers 132 and 134 are formed so as to cover the semiconductor layers 104 and 106, respectively (see FIG. 29A).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the semiconductor layers 104 and 106 and the second insulating layer 128 formed above the semiconductor layers 108 and 110 (see FIG. (See FIG. 29B). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left over part of the semiconductor layers 104, 106, 108, and 110. Conductive films 140, 142, 144, and 146 each functioning as a gate electrode are formed (see FIGS. 29C and 40).

Note that in this embodiment, the width of the stacked structure in which the conductive film 144 formed over the semiconductor layer 108 includes the charge accumulation layer 121 and the charge accumulation layer 125 (at least in the direction substantially parallel to the direction in which carriers flow through the channel). It is formed so as to be larger.

Next, a resist 148 is selectively formed so as to cover the semiconductor layer 104, and an impurity element is introduced into the semiconductor layers 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 30A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 30A, a high-concentration impurity region 152 and a channel formation region 150 which form a source region or a drain region are formed in the semiconductor layer 106 by introducing an impurity element. In the semiconductor layer 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the semiconductor layer 110, a high-concentration impurity region 162 that forms a source region or a drain region and a channel formation region 160 are formed.

Next, a resist 166 is selectively formed so as to cover the semiconductor layers 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the semiconductor layer 104 using the resist 166 and the conductive film 140 as a mask ( (See FIG. 30B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the semiconductor layers 106, 108, and 110 in FIG. As a result, a high concentration impurity region 170 and a channel formation region 168 that form a source region or a drain region are formed in the semiconductor layer 104.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the semiconductor layers 104 and 106 are formed over the insulating layer 172. , 108, and 110, conductive films 174 that are electrically connected to the impurity regions 170, 152, 156, and 162, respectively, are formed (see FIGS. 30C and 41).

Note that in this embodiment, the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate in the nonvolatile memory element is provided to be smaller than the width of the semiconductor layer 108 (see FIG. 40). An end portion of the stacked structure including the charge storage layer 121 and the charge storage layer 125 is formed above the semiconductor layer 108, and the conductive layer 144 functioning as a control gate crosses over the end portion of the semiconductor layer 108. Is formed. Therefore, the end portion of the stacked structure including the charge storage layer 121 and the charge storage layer 125 may be formed in a non-uniform shape by etching or the like accompanying a manufacturing process, which may affect the characteristics of the nonvolatile memory element. is there. In addition, there is a possibility that the characteristics of the nonvolatile memory element may be affected by poor coverage of the first insulating layer 116 or accumulation of some charges accompanying the manufacturing process. Therefore, in the above-described configuration, the edge of the stacked structure including the charge storage layer 121 and the charge storage layer 125 (in this example, the direction in which carriers flow in the channel formation region (the direction connecting the source region and the drain region) is roughly illustrated. The impurity region 194 may be selectively provided in the semiconductor layer 108 that overlaps with the region of the stacked structure including the charge storage layer 121 and the charge storage layer 125 in the vertical direction and a region in the vicinity thereof (FIG. 42). reference).

The impurity region 194 is provided so as to have a different conductivity type from the impurity region 156 functioning as a source region or a drain region of the semiconductor layer 108. For example, when the impurity region 156 is provided with a conductivity type indicating n-type, the impurity region 194 is provided with a conductivity type indicating p-type.

42 shows an example in which the impurity region 194 is extended to a region that does not overlap with the conductive film 144, but may be formed only in a region that overlaps with the conductive film 144. Further, it may be provided on the entire outer peripheral portion of the semiconductor layer 108.

In this manner, by providing the impurity region 194, the adjacent portion of the impurity region 156 and the impurity region 194 has a high resistance due to the pn junction. Therefore, the end portion of the stacked structure including the charge storage layer 121 and the charge storage layer 125 is provided. It is possible to suppress the influence on the characteristics of the nonvolatile memory element depending on the shape and the like.

In this example, the nonvolatile memory element between E and F has been described. Similarly, the transistors provided between AB and between CD and GH are also illustrated in FIGS. As described above, an impurity region 194 may be provided.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor layer to the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a semiconductor device, which is different from those in Embodiments 1 to 3, will be described with reference to drawings. In addition, when the same thing as what was shown in either of the said Example 1 thru | or 3 is pointed out, it uses the same code | symbol and abbreviate | omits description. 43 to 45 are top views, and FIGS. 25 to 27 are cross-sectional views taken along lines AB, CD, EF, and GH in FIGS. 43 to 45. Yes. In addition, a thin film transistor provided in the logic portion is shown between AB and CD, a non-volatile memory element provided in the memory portion is shown between EF, and a thin film transistor provided in the memory portion is shown between GH. Show.

First, after forming similarly to FIG. 18C, a resist is formed so as to selectively cover the semiconductor layers 104, 106, and 108 and part of the semiconductor layer 110 as shown in FIG. 19A. Then, an impurity region 126 is formed by introducing an impurity element into the semiconductor layer 110 not covered with the resist. Then, the resist is removed, and the semiconductor layers 104, 106, 110, the first insulating layer 116 formed above the semiconductor layer 108, the charge storage layer 120, and the stacked structure including the charge storage layer 123 are covered. Two insulating layers 128 are formed (see FIGS. 25A and 43).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the semiconductor layers 108 and 110, and the second insulating layer 128 formed over the semiconductor layers 104 and 106 is formed. This is selectively removed (see FIG. 25B).

Next, third insulating layers 132 and 134 are formed so as to cover the semiconductor layers 104 and 106, respectively (see FIG. 25C).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the semiconductor layers 104 and 106 and the second insulating layer 128 formed above the semiconductor layers 108 and 110 (see FIG. (See FIG. 26A). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left over part of the semiconductor layers 104, 106, 108, and 110. Conductive films 140, 142, 144, and 146 each functioning as a gate electrode are formed (see FIG. 26B and FIG. 43). In this embodiment, the surfaces of the semiconductor layers 104, 106, 108, and 110 that do not overlap with the conductive films 140, 142, 144, and 146 are exposed.

Specifically, in the semiconductor layer 104, a portion of the third insulating layer 132 formed below the conductive film 140 that does not overlap with the conductive film 140 is selectively removed, so that the conductive film 140 and the third insulating layer are removed. The layer 132 is formed so that the end portions thereof substantially coincide with each other. Further, in the semiconductor layer 106, a portion of the third insulating layer 134 formed below the conductive film 142 that does not overlap with the conductive film 142 is selectively removed, so that the conductive film 142 and the third insulating layer 134 It forms so that an edge part may correspond substantially. Further, in the semiconductor layer 108, a stacked structure including the second insulating layer 128, the charge storage layer 120, and the charge storage layer 123 formed below the conductive film 144, and the conductive film 144 of the first insulating layer 116 A portion that does not overlap is selectively removed so that the conductive film 144, the second insulating layer 128, the stacked structure including the charge storage layer 121 and the charge storage layer 125, and the end portion of the first insulating layer 116 substantially coincide with each other. Form. In addition, in the semiconductor layer 110, a portion of the second insulating layer 128 formed below the conductive film 146 that does not overlap with the conductive film 146 is selectively removed, so that the ends of the conductive film 146 and the second insulating layer 128 are removed. The portions are formed so as to substantially match (see FIG. 44).

In this case, a portion of the insulating layer that does not overlap with the formation of the conductive films 140, 142, 144, and 146 may be removed, or the resist remaining after the formation of the conductive films 140, 142, 144, and 146 or the conductive film may be removed. 140, 142, 144, and 146 may be used as a mask to remove portions of the insulating layer that do not overlap.

Next, a resist 148 is selectively formed so as to cover the semiconductor layer 104, and an impurity element is introduced into the semiconductor layers 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 26C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 26C, an impurity element 152 and a channel formation region 150 which form a source region or a drain region are formed in the semiconductor layer 106 by introducing an impurity element. Further, an impurity region 156 and a channel formation region 154 that form a source region or a drain region are formed in the semiconductor layer 108. In the semiconductor layer 110, a high-concentration impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

Next, a resist 166 is selectively formed so as to cover the semiconductor layers 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the semiconductor layer 104 using the resist 166 and the conductive film 140 as a mask ( (See FIG. 27A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the semiconductor layers 106, 108, and 110 in FIG. 26C is introduced. As a result, an impurity region 170 and a channel formation region 168 that form a source region or a drain region are formed in the semiconductor layer 104.

Note that in this embodiment, the impurity element in FIG. 26C or FIG. 27A is exposed with the semiconductor layers 104, 106, 108, and 110 not overlapping with the conductive films 140, 142, 144, and 146 exposed. We are introducing. Therefore, the channel formation regions 150, 154, 160, and 168 formed in the semiconductor layers 104, 106, 108, and 110 can be formed in a self-aligned manner with the conductive films 140, 142, 144, and 146, respectively.

Next, an insulating layer 192 is formed so as to cover the exposed semiconductor layers 104, 106, 108, and 110 and the conductive films 140, 142, 144, and 146 (see FIG. 27B).

The insulating layer 192 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)) by CVD or sputtering. The insulating layer having oxygen or nitrogen such as DLC (diamond-like carbon) or the like can be used to form a single layer or a stacked structure.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the semiconductor layers 104 and 106 are formed over the insulating layer 172. , 108, and 110, conductive films 174 that are electrically connected to the impurity regions 170, 152, 156, and 162, respectively, are formed (see FIGS. 27C and 45).

As the insulating layer 172, any of the materials described in Embodiment 1 can be used. For example, the insulating layer 192 includes oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), or silicon nitride oxide (SiNxOy, (x> y)). An insulating layer containing an inorganic material can be used, and the insulating layer 172 can be formed using an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Needless to say, both the insulating layer 192 and the insulating layer 172 may be formed using an insulating layer containing an inorganic material.

Note that in this embodiment, LDD regions can be formed in the semiconductor layers 104, 106, 108, and 110 by using sidewalls. For example, after the formation up to FIG. 26B, a low concentration impurity element is introduced into the semiconductor layers 104, 106, 108, and 110 using the conductive films 140, 142, 144, and 146 as masks, and then the conductive films 140, 142, An insulating layer 198 (also referred to as a sidewall) in contact with the side surfaces of 144 and 146 is formed (see FIG. 31A).

Then, by introducing a high concentration impurity element using the insulating layer 198 and the conductive films 140, 142, 144, and 146 as masks, a high concentration impurity region 170 and an LDD region that form a source region or a drain region in the semiconductor layer 104. A low concentration impurity region 188 and a channel formation region 168 are formed. Further, a high concentration impurity region 152 for forming a source region or a drain region, a low concentration impurity region 186 for forming an LDD region, and a channel formation region 150 are formed in the semiconductor layer 106. In the semiconductor layer 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the semiconductor layer 110, a high-concentration impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed (see FIG. 31A).

Note that as a method for forming the insulating layer 198, a film containing an inorganic material of silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin by a plasma CVD method, a sputtering method, or the like. A single layer or a stacked layer is formed. Then, the insulating layer can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 140, 142, 144, and 146. Note that the insulating layer 198 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed. In this example, the insulating layer 198 is formed so as to be in contact with the side surfaces of the insulating layer and the charge storage layer formed below the conductive films 140, 142, 144, and 146.

After that, as described above, the insulating layers 192 and 172 and the conductive film 174 are formed, whereby a nonvolatile semiconductor memory device can be obtained (see FIG. 31B).

Even in the structure shown in this embodiment, the width of the stacked structure including the charge storage layer 121 and the charge storage layer 125 functioning as a floating gate is smaller than the width of the semiconductor layer 108 as shown in the third embodiment. It is good also as a structure provided. Also in the structure shown in this embodiment, the impurity region 194 may be provided as shown in FIGS.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor layer to the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, an application example of a semiconductor device including the above-described nonvolatile semiconductor memory device of the present invention and capable of inputting and outputting data without contact will be described with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 46A). The high frequency circuit 810 receives a signal from the antenna 890. The high frequency circuit 810 is a circuit that outputs the signal received from the data modulation circuit 860 from the antenna 890. The power supply circuit 820 is a circuit that generates a power supply potential from a reception signal, the reset circuit 830 is a circuit that generates a reset signal, and the clock generation circuit 840 generates various clock signals based on the reception signal input from the antenna 890. The data demodulating circuit 850 is a circuit that demodulates the received signal and outputs the demodulated signal to the control circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, the nonvolatile semiconductor memory device of the present invention can be applied to the memory circuit 880. In the nonvolatile semiconductor memory device of the present invention, since the driving voltage can be lowered, it is possible to extend the distance in which data can be communicated without contact.

As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). It is good also as a type which supplies a power supply voltage to.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 46B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 46C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

The nonvolatile semiconductor memory device of the present invention can be used for electronic devices in various fields equipped with a memory. For example, as an electronic device to which the nonvolatile semiconductor memory device of the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), Plays back recording media such as computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines or electronic books), and image playback devices (specifically DVDs (digital versatile discs)) equipped with recording media And an apparatus provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

17A and 17B show a digital camera. FIG. 17B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter 2115, and the like. In addition, a removable nonvolatile memory 2116 is provided, and data captured by the digital camera is stored in the nonvolatile memory 2116. A nonvolatile semiconductor memory device formed using the present invention can be applied to the nonvolatile memory 2116.

FIG. 17C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the nonvolatile memory 2125 and played back. A nonvolatile semiconductor memory device formed using the present invention can be applied to the nonvolatile memory 2125.

FIG. 17D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 17D includes a main body 2130, a display portion 2131, a nonvolatile memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the nonvolatile memory portion 2132, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating the operation unit 2133 using a NAND type nonvolatile memory having a recording capacity of 20 to 200 gigabytes. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable audio device. Note that the nonvolatile semiconductor memory device provided in the nonvolatile memory portion 2132 may be removable.

FIG. 17E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a nonvolatile memory portion 2144. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the nonvolatile memory portion 2144, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating an operation key 2143 using a NAND nonvolatile memory having a recording capacity of 20 to 200 gigabytes. Note that the nonvolatile semiconductor memory device provided in the nonvolatile memory portion 2144 may be removable.

As described above, the applicable range of the nonvolatile semiconductor memory device of the present invention is so wide that it can be used for electronic devices in various fields as long as it has a memory.

1 is a cross-sectional view for explaining a main structure of a nonvolatile semiconductor memory device according to the present invention. The band figure of the non-volatile memory in the initial state (charge discharge state). The band diagram of the non-volatile memory in the writing state. The band figure of the non-volatile memory in a charge retention state. The band diagram of the non-volatile memory in the erased state. 4A and 4B illustrate writing and reading operations of a nonvolatile memory. 10A and 10B illustrate an erase operation of a nonvolatile memory. The figure which shows an example of the equivalent circuit of a non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NOR type non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NAND type non-volatile memory cell array. 4A and 4B illustrate a write operation of a NAND nonvolatile memory. The figure explaining erase and read-out operation of NAND type non-volatile memory. The figure which shows the change of the threshold voltage of a non-volatile memory in the case of "0" with which charge was accumulate | stored, and the case of "1" erase | eliminated. 1 is a diagram illustrating an example of a circuit block diagram of a nonvolatile semiconductor memory device. The figure explaining the structure of a plasma processing apparatus. The band figure of the conventional non-volatile memory. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. 1 is a diagram showing an example of a nonvolatile semiconductor memory device of the present invention. 1 is a diagram showing an example of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention.

Explanation of symbols

M0 Non-volatile memory element M01 Non-volatile memory element M02 Non-volatile memory element M03 Non-volatile memory element M11 Non-volatile memory element M12 Non-volatile memory element M13 Non-volatile memory element S1 Select transistor S2 Select transistor S01 Select transistor S02 Select transistor S03 Select transistor S11 Select transistor S12 Select transistor S13 Select transistor MS01 Memory cell WL Word line WL0 Word line WL1 Word line WL11 Word line BL Bit line BL0 Bit line SL Source line NS1 NAND cell 01 Semiconductor layer 02 First insulating layer 03 Floating gate electrode 04 Second insulating layer 05 Control gate electrode 10 Substrate 12 Underlying insulating layer 14 Semiconductor layer 16 First insulating layer 16a Silicon oxide layer 16b Silicon nitride layer 18 Pure region 18a Source region 18b Drain region 20 Floating gate electrode 20a First floating gate electrode 20b Second floating gate electrode 22 Second insulating layer 22a Silicon nitride layer 22b Silicon oxide layer 24 Control gate electrode 24a Metal nitride layer 24b metal layer 26 gate 30 semiconductor layer 32 semiconductor layer 34 semiconductor layer 36 semiconductor layer 38 semiconductor layer 40 semiconductor layer 52 memory cell array 54 peripheral circuit 56 address buffer 58 control circuit 60 booster circuit 62 row decoder 64 column decoder 66 sense amplifier 68 data buffer 70 Data Input / Output Buffer 80 Antenna 82 Dielectric Plate 84 Gas Supply Unit 86 Exhaust Port 88 Support Stand 90 Temperature Control Unit 92 Microwave Supply Unit 94 Plasma 100 Substrate 101 Substrate 102 Insulating Layer 104 Semiconductor Layer 106 Semiconductor Layer 108 Semiconductor layer 110 Semiconductor layer 112 First insulating layer 116 First insulating layer 120 Charge storage layer 121 Charge storage layer 123 Charge storage layer 125 Charge storage layer 122 Resist 124 Resist 126 Impurity region 128 Second insulating layer 130 Resist 132 Insulating layer 136 insulating layer 136 conductive film 138 conductive film 142 conductive film 144 conductive film 146 conductive film 148 resist 150 channel formation region 152 impurity region 154 channel formation region 156 impurity region 158 low-concentration impurity region 160 channel formation region 162 impurity Region 164 Low-concentration impurity region 166 Resist 168 Channel formation region 170 Impurity region 172 Insulating layer 174 Conductive film 182a Conductive film 182b Conductive film 182c Conductive film 182d Conductive film 184a Conductive film 184b Conductive film 184 Conductive film 184d Conductive film 186 Low-concentration impurity region 188 Low-concentration impurity region 190 Impurity region 192 Insulating layer 194 Insulating layer 198 Insulating layer 200a Semiconductor layer 200b Semiconductor layer 202a NAND cell 202b NAND cell 800 Semiconductor device 810 High-frequency circuit 820 Power supply circuit 830 Reset Circuit 840 Clock generation circuit 850 Data demodulation circuit 860 Data modulation circuit 870 Control circuit 880 Storage circuit 890 Antenna 910 Code extraction circuit 920 Code determination circuit 930 CRC determination circuit 940 Output unit circuit 2111 Case 2112 Display unit 2113 Lens 2114 Operation key 2115 Shutter 2116 Nonvolatile memory 2121 Housing 2122 Display unit 2123 Operation key 2125 Nonvolatile memory 2130 Main body 2131 Display unit 2132 Non-volatile Source memory unit 2133 Operation unit 2134 Earphone 2141 Main body 2142 Display unit 2143 Operation key 2144 Non-volatile memory unit 3200 Reader / writer 3210 Display unit 3220 Product 3230 Semiconductor device 3240 Reader / writer 3250 Semiconductor device 3260 Product

Claims (9)

A semiconductor layer having a channel formation region between a pair of impurity regions;
A first insulating layer above the channel formation region;
A first gate above the first insulating layer;
A second insulating layer above the first gate;
A second gate above the second insulating layer;
The first gate has a first layer and a second layer;
The first layer is in contact with the first insulating layer;
The nonvolatile semiconductor memory device, wherein the first layer includes germanium and oxygen. A semiconductor layer having a channel formation region between a pair of impurity regions;
A first insulating layer above the channel formation region;
A first gate above the first insulating layer;
A second insulating layer above the first gate;
A second gate above the second insulating layer;
The first gate has a first layer and a second layer;
The first layer is in contact with the first insulating layer;
The nonvolatile semiconductor memory device, wherein the first layer includes germanium and nitrogen. In claim 1 or 2,
The nonvolatile semiconductor memory device, wherein a band gap of a material included in the semiconductor layer is larger than a band gap of a material included in the first layer. In claim 3 ,
Wherein the band gap of the material semiconductor layer is perforated, the first and the band gap of the layer to that timber fees Yes, the difference is non-volatile semiconductor memory device, characterized in that at 0.1V or more. In any one of Claims 1 thru | or 4,
A non-volatile semiconductor memory device, wherein an electron affinity of a material included in the semiconductor layer is smaller than an electron affinity of a material included in the first layer. In any one of Claims 1 thru | or 5,
The first insulating layer has a third layer and the fourth layer,
The third layer includes oxygen and silicon;
The fourth layer includes a non-volatile semiconductor memory device including nitrogen and silicon. In claim 6 ,
The nonvolatile semiconductor memory device, wherein the first layer is in contact with the fourth layer . In claim 6 or 7 ,
The third layer is obtained by oxidizing the semiconductor layer by plasma treatment.
The nonvolatile semiconductor memory device, wherein the fourth layer is obtained by nitriding the first layer by plasma treatment. In any one of Claims 1 thru | or 8,
The nonvolatile semiconductor memory device, wherein the second layer includes silicon and any one of nitrogen, carbon, and germanium.

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