JP5132171B2 - Nonvolatile semiconductor memory device and manufacturing method thereof, and semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory device which can be electrically written, read and erased, and a manufacturing method thereof.

The market for nonvolatile memories that can electrically rewrite data and store data even when the power is turned off is expanding. The nonvolatile memory has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is characterized in that a region capable of accumulating charges for a long period is provided on the channel formation region. In addition, since the charge storage region of the nonvolatile memory is formed on an insulating layer and is isolated from the surroundings, it is also called a floating gate. A control gate is further provided on the floating gate via an insulating layer (for example, Patent Document 1 and Patent Document 2).

In the so-called floating gate type nonvolatile memory having such a structure, an operation for accumulating and releasing electric charge in the floating gate is performed by a voltage applied to the control gate. In other words, data is stored by taking in and out charges held in the floating gate. Specifically, the injection and extraction of charges to and from the floating gate are performed by applying a high voltage between the semiconductor layer in which the channel formation region is formed and the control gate. Such a nonvolatile memory is not only built into a semiconductor wafer on a silicon wafer, but also a technique for forming a semiconductor memory device on a silicon wafer including a glass substrate, a plastic substrate, and an insulating layer has been developed. .

Patent Document 2 discloses a nonvolatile semiconductor memory device shown in FIG. 29 includes a channel region 2, a source region 7, a drain region 8, a first insulating film 3, a floating gate 4, a second insulating film 5 formed of a semiconductor layer on an insulator 1. A control gate 6, a source electrode 15, a drain electrode 11, and a gate electrode 9 are provided. The source region 7, the drain region 8, the source electrode 15, and the drain electrode 11 are formed so as to be in contact with each other through a contact hole formed in the interlayer film 13.
JP-A-5-189984 Japanese Patent Laid-Open No. 6-61501

Conventionally, in the nonvolatile semiconductor device as shown in FIG. 29, when the thickness of the semiconductor layer is thin and the selective ratio between the interlayer film 13 and the semiconductor layer is not sufficient, the interlayer film is formed when the contact hole is opened by dry etching. There is a problem that not only the semiconductor layer 13 but also the semiconductor layer is etched, and the contact resistance value is increased. When a nonvolatile semiconductor device is manufactured using a large glass substrate, the contact resistance value is further increased. However, when the thickness of the semiconductor layer is increased, the margin becomes narrower during laser crystallization (LC). Further, when the SOI substrate is used and the semiconductor layer is thickened, there is a problem that a parasitic transistor between the source region and the drain region cannot be suppressed and a fully depleted layer type TFT cannot be formed.

In addition, when the contact hole is opened by wet etching, the selectivity between the interlayer film and the semiconductor layer can be increased as much as possible. However, in the case of wet etching, contact holes with a high aspect ratio cannot be formed, so that high integration is difficult.

In addition, there is a method of reducing the etching time in the dry etching opening by reducing the thickness of the interlayer film, thereby suppressing the etching of the semiconductor layer. However, when the interlayer film is made thinner, the parasitic capacitance of the upper wiring and the gate electrode increases. Therefore, there is a risk of affecting the drive capability of the circuit.

In view of the above problems, an object of the present invention is to provide a nonvolatile semiconductor memory device having excellent writing characteristics and charge retention characteristics and a method for manufacturing the same.

The nonvolatile semiconductor memory device of the present invention is characterized in that a conductive layer is provided between a source region or a drain region and a source wiring or a drain wiring. The conductive layer is made of the same conductive layer as the conductive layer that forms the control gate electrode. In addition, an insulating film is provided so as to cover the conductive layer, and the insulating film has a contact hole in which a part of the surface of the conductive layer is exposed. The source wiring or drain wiring is formed so as to fill the contact hole.

The nonvolatile semiconductor memory device of the present invention includes a semiconductor layer having a channel formation region, a source region, and a drain region, a first insulating film that covers a part of the source region and the drain region, and the channel formation region, A floating gate electrode formed on the first insulating film; a second insulating film covering the floating gate electrode; a control gate electrode formed on the second insulating film; the source region; A conductive layer formed on the drain region, a second insulating film, a third insulating film formed on the control gate electrode and the conductive layer, and a contact hole formed in the third insulating film A source electrode or a drain electrode in contact with the conductive layer via the conductive layer, and the source region or the drain region and the source electrode or the drain electrode are electrically connected via the conductive layer. Characterized in that it connects.

The nonvolatile semiconductor memory device of the present invention includes a semiconductor layer having a channel formation region, a source region, and a drain region, a first insulating film that covers a part of the source region and drain region, and the channel region, and the first A floating gate electrode formed on the first insulating film; a second insulating film covering the floating gate electrode; a control gate electrode formed on the second insulating film; and the source region and the drain region Through a conductive layer formed on the second insulating film, a third insulating film formed on the second insulating film, the control gate electrode and the conductive layer, and a contact hole formed in the third insulating film. A source electrode or a drain electrode in contact with the conductive layer, and the source region or the drain region and the source electrode or the drain electrode are electrically connected through the conductive layer, and The control gate electrode is formed so as to cover the floating gate electrode through the second insulating film, and a sidewall is formed on the control gate electrode, and the sidewall is generated by the floating gate electrode. It is formed in the level | step-difference part of a gate electrode, It is characterized by the above-mentioned.

In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a channel formation region, a source region, and a drain region are formed in a semiconductor layer, and the first insulation is formed so as to cover the source region, the drain region, and the channel formation region. A film is formed, a floating gate electrode is formed on the first insulating film, a second insulating film is formed to cover the floating gate electrode, and the first insulating film and the second insulating film are formed. Etching a part to expose a part of the source region and the drain region, forming a first conductive layer on the second insulating film, the exposed source region and the drain region, Etching the first conductive layer to form a control gate electrode on the second insulating film and a second conductive layer on the exposed source and drain regions, and to form the second insulating film, Control gate power And forming a third insulating film on the second conductive layer, opening a contact hole in the third insulating film through which a part of the second conductive layer is exposed, and exposing the exposed second A source electrode or a drain electrode is formed over the conductive layer.

In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a channel formation region, a source region, and a drain region are formed in a semiconductor layer, and the first insulation is formed so as to cover the source region, the drain region, and the channel formation region. A film is formed, a floating gate electrode is formed on the first insulating film, a second insulating film is formed to cover the floating gate electrode, and the first insulating film and the second insulating film are formed. Etching a part to expose a part of the source region and the drain region, forming a first conductive layer on the second insulating film, the exposed source region and the drain region, A third insulating film is formed on the first conductive layer, the third insulating film is etched to form a sidewall at a stepped portion generated by the floating gate electrode, and the first conductive layer is etched. Before A control gate electrode is formed on the second insulating film, and a second conductive layer is formed on the exposed source and drain regions, and the second insulating film, the control gate electrode, and the second conductive layer are formed. A fourth insulating film is formed thereon, a contact hole in which a part of the second conductive layer is exposed is opened in the fourth insulating film, and a source electrode is formed on the exposed second conductive layer. Alternatively, a drain electrode is formed.

Note that germanium or a germanium compound, an oxide or nitride of germanium or a germanium compound, or an oxide or nitride containing a germanium or a germanium compound is used as a material for the floating gate electrode.

The floating gate electrode has a stacked structure of a first floating gate electrode and a second floating gate electrode.

The first floating gate electrode is provided on the first insulating film side, and a second floating gate electrode having a width shorter than that of the first floating gate electrode is provided on the first floating gate electrode. It is characterized by that.

Note that as the material of the first floating gate electrode, germanium or a germanium compound, an oxide or nitride of germanium or a germanium compound, or an oxide or nitride containing a germanium or a germanium compound is used, and the second floating gate is used. Silicon or a silicon compound is used as an electrode material.

By providing a conductive layer between the source region or the drain region and the source wiring or the drain wiring, when the contact hole is formed by etching the insulating layer, the semiconductor layer is not etched and the contact resistance value is reduced. An increase can be prevented. Therefore, it is possible to manufacture a nonvolatile semiconductor memory device capable of writing with high efficiency at a low voltage and having good charge retention characteristics.

In addition, since the conductive layer provided between the source region or the drain region and the source wiring or the drain wiring is formed using the control gate electrode material, the nonvolatile semiconductor memory having excellent characteristics without impairing the productivity. The device can be manufactured. Since the conductive layer can be manufactured in the same process as the control gate electrode, it is possible to perform high-efficiency writing at a low voltage without imposing a burden on manufacturing equipment, and a nonvolatile semiconductor with good charge retention characteristics A memory device can be manufactured.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings. Note that Embodiments 1 to 3 and Examples 1 to 3 described below can be used in any combination.

(Embodiment 1)
FIG. 1 is a cross-sectional view for explaining a main configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. 1 particularly shows the main part of the nonvolatile memory element.

In FIG. 1, 10 is a substrate, 12 is a base insulating film, 14 is a semiconductor layer, 29 is a channel formation region, 18a and 18b are source regions or drain regions, 16 is a first insulating film (also referred to as a tunnel insulating film), 20 is a floating gate electrode, 22 is a second insulating film (also called a control insulating film), 24 is a control gate electrode, 26a and 26b are conductive layers, and 28a and 28b are source regions or drains via the conductive layers 26a and 26b. Source electrodes or drain electrodes electrically connected to the regions 18a and 18b, 28c a gate wiring electrically connected to the control gate electrode, and 27 an insulating film for passivation.

In the configuration shown in FIG. 1, a base insulating film 12 is formed on a substrate 10, and a semiconductor layer 14 having source or drain regions 18 a and 18 b and a channel forming region 29 is formed on the base insulating film 12. The first insulating film 16 and the conductive layers 26 a and 26 b are formed on the first insulating film 16, the floating gate electrode 20 is formed on the first insulating film 16, and the second insulating film 16 is formed on the floating gate electrode 20 and the first insulating film 16. An insulating film 22 is formed, and a control gate electrode 24 is formed on the second insulating film 22. The source or drain electrodes 28 a and 28 b are electrically connected to the source or drain regions 18 a and 18 b through contact holes formed in the insulating film 27, and the gate wiring 28 c has a contact hole formed in the insulating film 27. And is electrically connected to the control gate electrode 24. The source or drain electrodes 28a and 28b and the source or drain regions 18a and 18b are electrically connected through the conductive layers 26a and 26b. Note that a planarization insulating film may be formed over the insulating film 27.

Next, a method for manufacturing the nonvolatile memory element illustrated in FIGS.

First, the semiconductor layer 14 is formed over the substrate 10 having an insulating surface (FIG. 2A). A base insulating film 12 may be provided between the substrate 10 and the semiconductor layer 14 (FIG. 2A). The base insulating film 12 prevents impurities such as alkali metals from diffusing from the substrate 10 to the semiconductor layer 14 and contaminates them, and may be provided as a blocking layer as appropriate.

As the substrate 10 having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating film formed on the surface, or the like can be used.

As the base insulating film 12, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like, using a CVD method, a sputtering method, or the like. It forms using. For example, in the case where the base insulating film 12 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film.

The semiconductor layer 14 is preferably formed using a single crystal semiconductor or a polycrystalline semiconductor. For example, after a semiconductor layer formed on the entire surface of the substrate 10 is crystallized on the substrate 10 by sputtering, plasma CVD, or low pressure CVD, the semiconductor layer 14 is formed by selective etching. That is, for the purpose of element isolation, it is preferable to form an island-shaped semiconductor layer on the insulating surface and to form one or more nonvolatile memory elements on the semiconductor layer. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, laser crystallization, rapid thermal annealing (RTA), crystallization by heat treatment using a furnace annealing furnace, crystallization using a metal element that promotes crystallization, or a combination of these methods Can be used. Further, instead of such a thin film process, a so-called SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface may be used.

Thus, by separating and forming the semiconductor layer formed on the insulating surface in an island shape, even when the memory element array and the peripheral circuit are formed on the same substrate, the element can be effectively separated. That is, a memory element array that needs to be written or erased at a voltage of 10 V or more and 20 V or less and a peripheral circuit that operates at a voltage of 3 V or more and 7 V or less and mainly performs data input / output and command control on the same substrate. Even when formed, mutual interference due to a difference in voltage applied to each element can be prevented.

Next, a first insulating film 16 is formed on the surface of the semiconductor layer 14 (FIG. 2B). The first insulating film 16 is formed of silicon oxide or a stacked structure of silicon oxide and silicon nitride. The first insulating film 16 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because an insulating film formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. Since the first insulating film 16 is used as a tunnel insulating film for injecting charges into the floating gate electrode 20, it is preferable that the first insulating film 16 be strong as described above. The first insulating film 16 is preferably formed to a thickness of 8 nm to 20 nm, preferably 8 nm to 10 nm. For example, when the gate length is 600 nm, the first insulating film 16 can be formed to a thickness of 8 nm to 10 nm.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating film is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

When the surface of the semiconductor layer 14 is oxidized by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) are used in an oxygen atmosphere. Or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . In the present embodiment, for example, Ar can be used as the rare gas. A gas in which Ar and Kr are mixed may be used.

FIG. 4 shows a configuration example of an apparatus for performing plasma processing. This plasma processing apparatus includes a support base 88 for arranging the substrate 10, a gas supply unit 84 for introducing gas, an exhaust port 86 connected to a vacuum pump for exhausting gas, an antenna 80, and a dielectric plate. 82, a microwave supply unit 92 for supplying microwaves for plasma generation. In addition, the temperature of the substrate 10 can be controlled by providing the temperature control unit 90 on the support base 88.

Hereinafter, the plasma treatment will be described. Note that plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating film, and a conductive layer. For these processes, a gas supplied from the gas supply unit 84 may be selected according to the purpose.

The oxidation treatment or nitridation treatment may be performed as follows. First, the processing chamber is evacuated and a plasma processing gas containing oxygen or nitrogen is introduced from the gas supply portion 84. The substrate 10 is heated to 100 ° C. or more and 550 ° C. or less by the room temperature or the temperature control unit 90. The interval between the substrate 10 and the dielectric plate 82 is about 20 nm to 80 mm (preferably 20 nm to 60 mm). Next, the microwave is supplied from the microwave supply unit 92 to the antenna 80. Then, plasma 94 is generated by introducing the microwave from the antenna 80 through the dielectric plate 82 into the processing chamber. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas. This method can perform oxidation, nitridation, or oxynitridation by solid-phase reaction at a low temperature of 500 ° C. or lower by effectively using active radicals excited by plasma.

In FIG. 2B, an example of a suitable first insulating film 16 formed by plasma treatment is to form a silicon oxide layer with a thickness of 8 nm to 10 nm on the surface of the semiconductor layer 14 by plasma treatment in an oxidizing atmosphere. Then, a laminated structure is formed in which a nitrogen plasma treatment layer is formed by treating the surface of the silicon oxide layer with a nitriding plasma in a nitrogen atmosphere. Specifically, first, a silicon oxide layer is formed with a thickness of 8 nm to 10 nm on the semiconductor layer 14 by plasma treatment in an oxygen atmosphere. Then, a nitrogen plasma treatment layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer by performing plasma treatment in a nitrogen atmosphere. Note that the vicinity of the surface means a depth of approximately 0.5 nm to 1.5 nm from the surface of the silicon oxide layer. For example, by performing plasma treatment in a nitrogen atmosphere, a structure in which nitrogen is contained at a ratio of 20 to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer is obtained.

In any case, by using a solid phase oxidation treatment or solid phase nitridation treatment by plasma treatment as described above, even if a glass substrate having a heat resistant temperature of 700 ° C. or less is used, it can be heated at about 950 ° C. to 1050 ° C. or less. An insulating film equivalent to the thermal oxide film to be formed can be obtained. That is, a highly reliable tunnel insulating film can be formed as the tunnel insulating film of the nonvolatile memory element.

Subsequently, a conductive layer 25 is formed over the first insulating film 16 (FIG. 2C). Then, the floating gate electrode 20 is formed over the first insulating film 16 by selectively etching the conductive layer 25 (FIG. 2D). The floating gate electrode 20 is a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), and germanium (Ge), or A film made of a nitride of the element (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film (typically, a Mo—W alloy or a Mo—Ta alloy) in combination with the element, Alternatively, a silicide film of the above elements (typically, a tungsten silicide film, a titanium silicide film, or a nickel silicide film) can be used. Impurities such as phosphorus and boron may be added to the silicon film. Although it may be formed of a single conductive layer, it may be a laminated film of two layers or three layers. It is formed by sputtering or CVD.

Note that the band gap of the semiconductor material forming the floating gate electrode 20 is preferably smaller than the band gap of the semiconductor layer 14. This is because the energy level at the bottom of the conduction band of the floating gate electrode 20 is made lower than the energy level at the bottom of the conduction band of the semiconductor layer 14, thereby improving the carrier (electron) injection property and improving the charge retention characteristics. is there.

The semiconductor material forming the floating gate electrode 20 is preferably formed of a material having a lower resistivity than the material forming the semiconductor layer 14. By forming the floating gate electrode 20 from a semiconductor material having a low resistivity, when a voltage is applied between the control gate electrode and the semiconductor layer, the electric field is not divided by the floating gate electrode, and the electric field is reduced. The semiconductor layer can be effectively acted on. For example, germanium is preferable because it has a specific resistance of 40 to 70 Ω · cm. Further, an n-type impurity may be added to the floating gate electrode 20 for the purpose of reducing the resistivity. As described above, when the floating gate electrode 20 is formed of a material having a small band gap and a low resistivity as compared with the semiconductor layer 14, writing characteristics can be improved.

The semiconductor material forming the floating gate electrode 20 is an electron of the floating gate electrode 20 formed by the first insulating layer 16 with respect to the barrier energy against the electrons of the semiconductor layer 14 formed by the first insulating layer 16. It is preferable that the barrier energy to be high. This is to facilitate the injection of carriers (electrons) from the semiconductor layer 14 to the floating gate electrode 20 and to prevent the charge from being lost from the floating gate electrode 20.

Typically, the floating gate electrode 20 can be formed of germanium or a germanium compound as satisfying such conditions. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the germanium concentration is 10 atomic% or less, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

The floating gate is applied to the nonvolatile semiconductor memory device according to the present invention for the purpose of accumulating electric charges, but other semiconductor materials can be applied as long as they have the same function. For example, a ternary semiconductor containing germanium may be used. Further, the semiconductor material may be hydrogenated. Further, as a function of a charge storage layer of a nonvolatile memory element, an oxide or nitride of the germanium or germanium compound, or an oxide or nitride layer containing the germanium or germanium compound can be used. .

Further, the floating gate electrode 20 may be provided in a stacked structure of a first floating gate electrode and a second floating gate electrode. In this case, the first floating gate electrode provided on the first insulating layer 16 side is preferably formed of germanium or a germanium compound, and the second floating gate electrode provided on the second insulating layer 22 side. The layer is preferably formed of silicon or a silicon compound. As the silicon compound, silicon nitride, silicon nitride oxide, silicon carbide, silicon germanium containing germanium at a concentration of less than 10 atomic%, metal nitride, metal oxide, or the like can be used. Silicon or silicon compounds have a larger energy gap than germanium or germanium compounds. In this manner, by forming the second floating gate electrode layer with a material having a larger band gap than the first floating gate electrode layer, the charge accumulated in the floating gate leaks to the second insulating layer 22 side. Can be prevented. Further, a metal nitride or a metal oxide can be used for forming the second floating gate electrode layer. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

In any case, by providing the second floating gate electrode of silicon or silicon compound, metal nitride, or metal oxide described above on the upper layer side of the first floating gate electrode formed of germanium or germanium compound, In the production process, it can be used as a barrier layer for the purpose of water resistance and chemical resistance. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the floating gate can be easily processed. However, the material of the first floating gate electrode and the second floating gate electrode is not limited to these. The floating gate electrode may have a stacked structure of two or more layers.

Next, an impurity element is introduced into the semiconductor layer 14 using the floating gate electrode 20 as a mask, so that source or drain regions 18a and 18b are formed (see FIG. 2D). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. For example, when boron is used as the p-type impurity, it is added at a concentration of 5 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁶ atoms / cm ³ or less. This is for controlling the threshold voltage of the transistor, and acts effectively when added to the channel formation region 29. The channel formation region 29 is formed below a floating gate electrode 20 described later, and is located between a pair of source or drain regions 18 a and 18 b of the semiconductor layer 14.

Next, a second insulating film 22 is formed over the floating gate electrode 20 (FIG. 3A). The second insulating film 22 includes silicon oxide, silicon oxynitride (SiOxNy) (x> y), silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), aluminum oxide (AlxOy), HfOx, or One layer or a plurality of layers such as TaOx is formed by a low pressure CVD method, a plasma CVD method, or the like. The second insulating film 22 is formed with a thickness of 20 nm to 60 nm, preferably 30 nm to 40 nm. For example, a stacked film in which a silicon oxide layer is formed with a thickness of 8 nm, a silicon nitride layer is formed thereon with a thickness of 2 nm, and a silicon oxynitride film is formed thereon with a thickness of 30 nm is used. it can. Alternatively, a plasma treatment may be performed on the floating gate electrode 20 to form a nitride film whose surface is nitrided. In any case, the first insulating film 16 and the second insulating film 22 are either a nitride film or a nitrided layer on one or both sides in contact with the floating gate electrode 20, so that the floating gate electrode 20 Oxidation can be prevented.

Next, the first insulating film 16 and the second insulating film 22 are selectively etched so that a part of the surface of the source region or the drain region 18a, 18b is exposed. The second insulating film 22 is removed (FIG. 3B). A resist 316 is formed on the semiconductor layer 14 so as to cover the floating gate electrode 20 and a part of the source or drain regions 18a and 18b. Then, the first insulating film 16 and the second insulating film 22 are removed by etching so that part of the source region or drain region 18a, 18b is exposed.

Next, a conductive layer 19 is formed over the second insulating film 22 and the source or drain regions 18a and 18b (FIG. 3C). Then, by selectively removing the conductive layer 19 by etching, the conductive layer 19 is left in a part above the semiconductor layer 14, and the control gate electrode 24 is formed on the channel formation region 29 in the source region or the drain region. First conductive layers 26a and 26b are formed on 18a and 18b (FIG. 3D). The control gate electrode 24 and the first conductive layers 26a and 26b are made of metal selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these metals as main components. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. Further, the control gate electrode 24 may be formed by a laminated structure of one or more metal nitride layers 24a and the metal layer 24b. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer 24a, the adhesion of the metal layer 24b can be improved and peeling can be prevented. Further, since the metal nitride such as tantalum nitride has a high work function, the thickness of the first insulating film 16 can be increased by a synergistic effect with the second insulating film 22. Note that the conductive layers 26 a and 26 b may be formed so as to cover a part of the first insulating film 16 or the second insulating film 22.

Next, a third insulating film 27 having a contact hole 315 is formed over the control gate electrode 24 and the first conductive layers 26a and 26b (FIG. 3E). The third insulating film 27 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) by CVD or sputtering. ) Such as an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin. It can be provided in a single layer or laminated structure. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Note that the contact hole 315 is formed so that a part of the conductive layers 26a and 26b is exposed by forming a resist mask over the third insulating film 27 and performing dry etching. In this embodiment mode, since the conductive layers 26a and 26b are provided over the source or drain regions 18a and 18b, the semiconductor layer functioning as the source or drain region is etched when the contact hole 315 is formed. There is nothing.

Next, source or drain electrodes (second conductive layers) 28 a and 28 b are formed so as to be in contact with the first conductive layers 26 a and 26 b through contact holes formed in the third insulating film 27. (FIG. 3E). Further, a gate wiring 28 c is formed so as to be in contact with the control gate electrode 24. Note that the source or drain regions 18a and 18b and the source or drain electrodes 28a and 28b are electrically connected via the first conductive layers 26a and 26b. The source or drain electrodes 28a and 28b and the gate wiring 28c are formed by CVD or sputtering or the like using aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni ), Platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these An alloy material or a compound material containing an element as a main component is formed by etching after forming a single layer or a laminated film. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon.

The source or drain electrodes 28a and 28b are, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier. A laminated structure of films may be employed. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Since aluminum and aluminum silicon have a low resistance value and are inexpensive, they are optimal materials for forming the source or drain electrodes 28a and 28b. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

In the nonvolatile memory element having the structure shown in FIG. 1, conductive layers 26a and 26b are provided between the source or drain regions 18a and 18b and the source or drain electrodes 28a and 28b. Therefore, when the third insulating film 27 is etched, the semiconductor layer is not etched, and an increase in the contact resistance value can be prevented. Therefore, it is possible to manufacture a memory that can perform high-efficiency writing with a low voltage and has good charge retention characteristics.

Various nonvolatile semiconductor memory devices can be obtained using such a nonvolatile memory element. FIG. 5 shows an example of an equivalent circuit of a nonvolatile memory cell array. The memory cell MS01 that stores 1-bit information includes a selection transistor S01 and a nonvolatile memory element M01. The nonvolatile memory element M01 is a memory element having the structure shown in FIG. In FIG. 5, nonvolatile memory elements M01 to M03 and M11 to M13 are nonvolatile memory elements having the structure shown in FIG. The nonvolatile memory elements M01 to M03 and M11 to M13 are controlled by selection transistors S01 to S03 and S11 to S13, respectively. Note that the number of nonvolatile memory elements or selection transistors is not limited to that shown in FIG.

The selection transistor S01 is inserted in series between the bit line BL0 and the nonvolatile memory element M01, and the gate is connected to the word line WL1. The gate of the nonvolatile memory element M01 is connected to the word line WL11. When data is written to the nonvolatile memory element M01, the word line WL1 and the bit line BL0 are set to the H level and BL1 is set to the L level, and a high voltage is applied to the word line WL11. Thereby, charges are accumulated in the floating gate, and data can be written into the nonvolatile memory element. When erasing data, the word line WL1 and the bit line BL0 are set to H level, and a negative high voltage is applied to the word line WL11.

In this memory cell MS01, the select transistor S01 and the non-volatile memory element M01 are formed by the semiconductor layers 30 and 32 formed in an island shape on the insulating surface, respectively, so that no element isolation region is provided. Interference with other selection transistors or nonvolatile memory elements can be prevented. Further, since both the select transistor S01 and the nonvolatile memory element M01 in the memory cell MS01 are n-channel type, by forming both of them in a semiconductor layer separated into one island shape, a wiring for connecting the two elements is formed. Can be omitted.

FIG. 6 shows a NOR-type equivalent circuit in which a nonvolatile memory element is directly connected to a bit line. In this memory cell array, word lines WL and bit lines BL are arranged so as to intersect with each other, and nonvolatile memory elements are arranged at each intersection. In the NOR type, the drain of each nonvolatile memory element is connected to the bit line BL. The sources of the nonvolatile memory elements are commonly connected to the source line SL.

Also in this case, in the memory cell MS01, the non-volatile memory element M01 is formed of the semiconductor layer 32 formed on the insulating surface so as to be separated into islands, so that other non-volatile elements can be provided without providing an element isolation region. Interference with the memory element can be prevented. Further, a plurality of nonvolatile memory elements (for example, M01 to M23 shown in FIG. 6) are handled as one block, and these nonvolatile memory elements are formed by a semiconductor layer separated into one island shape, thereby making a block unit. The erase operation can be performed with.

The NOR type operation is, for example, as follows. In data writing, the source line SL is set to 0 V, a high voltage is applied to the word line WL selected for writing data, and a potential corresponding to data “0” and “1” is applied to the bit line BL. For example, H level and L level potentials are applied to the bit line BL for “0” and “1”, respectively. In order to write “0” data, in the nonvolatile memory element to which H level is given, hot electrons are generated in the vicinity of the drain, and this is injected into the floating gate. In the case of “1” data, such electron injection does not occur.

In a memory cell to which “0” data is given, hot electrons are generated in the vicinity of the drain due to a strong lateral electric field between the drain and the source, and this is injected into the floating gate. As a result, the state where electrons are injected into the floating gate and the threshold voltage becomes high is “0”. In the case of “1” data, hot electrons are not generated, electrons are not injected into the floating gate, and a low threshold voltage state, that is, an erased state is maintained.

When erasing data, a positive voltage of about 10 V is applied to the source line SL, and the bit line BL is left floating. Then, a negative high voltage is applied to the word line (a negative high voltage is applied to the control gate), and electrons are extracted from the floating gate. As a result, the data “1” is erased.

For data reading, the source line SL is set to 0V and the bit line BL is set to about 0.8V, and the selected word line WL is set to an intermediate value between the threshold values of data “0” and “1”. A voltage is applied, and the presence / absence of current draw in the nonvolatile memory element is determined by a sense amplifier connected to the bit line BL.

FIG. 7 shows an equivalent circuit of the NAND memory cell array. A NAND cell NS1 in which a plurality of nonvolatile memory elements are connected in series is connected to the bit line BL. A plurality of NAND cells gather to constitute a block BLK. The block BLK1 shown in FIG. 7 has 32 word lines (word lines WL0 to WL31). The nonvolatile memory elements located in the same row of the block BLK1 are commonly connected to word lines corresponding to this row.

In this case, since the select transistors S1 and S2 and the nonvolatile memory elements M0 to M31 are connected in series, these may be formed as a single semiconductor layer 34. Accordingly, wiring for connecting the nonvolatile memory elements can be omitted, so that integration can be achieved. Further, it is possible to easily separate the adjacent NAND cells. Further, the semiconductor layer 36 of the select transistors S1 and S2 and the semiconductor layer 38 of the NAND cell may be formed separately. When performing an erasing operation for extracting charges from the floating gates of the nonvolatile memory elements M0 to M31, the erasing operation can be performed in units of the NAND cells. Further, the nonvolatile memory elements (for example, the row of M30) commonly connected to one word line may be formed by one semiconductor layer 40.

The write operation is executed after the NAND cell NS1 is in the erased state, that is, the threshold value of each nonvolatile memory element of the NAND cell NS1 is in a negative voltage state. Writing is performed in order from the memory element M0 on the source line SL side. An example of writing to the memory element M0 is as follows.

In FIG. 8A, when "0" is written, for example, Vcc (power supply voltage) is applied to the selection gate line SG2 to turn on the selection transistor S2 and to set the bit line BL0 to 0 V (ground voltage). The selection gate line SG1 is set to 0V, and the selection transistor S1 is turned off. Next, the word line WL0 of the memory cell MS0 is set to the high voltage Vpgm (about 20V), and the other word lines are set to the intermediate voltage Vpass (about 10V). Since the voltage of the bit line BL is 0V, the potential of the channel formation region of the selected memory cell MS0 is 0V. Since the potential difference between the word line WL0 and the channel formation region is large, electrons are injected into the floating gate of the memory cell MS0 by the FN tunnel current as described above. As a result, the threshold voltage of memory cell MS0 becomes positive (a state in which “0” is written).

On the other hand, when "1" is written, the bit line BL is set to Vcc (power supply voltage), for example, as shown in FIG. Since the voltage of the selection gate line SG2 is Vcc, the selection transistor S2 is cut off when Vcc minus Vth (Vcc−Vth) with respect to the threshold voltage Vth of the selection transistor S2. Accordingly, the channel formation region of the memory cell MS0 is in a floating state. Next, when the high voltage Vpgm (20 V) is applied to the word line WL0 and the intermediate voltage Vpass (10 V) is applied to the other word lines, the capacitive coupling between each word line and the channel formation region causes the channel formation region. The voltage rises from Vcc-Vth and becomes about 8V, for example. Since the voltage of the channel formation region is boosted to a high voltage, the potential difference between the word line WL0 and the channel formation region is small unlike the case of writing “0”. Therefore, electron injection due to the FN tunnel current does not occur in the floating gate of the memory cell MS0. Therefore, the threshold value of the memory cell MS1 is maintained in a negative state (a state in which “1” is written).

In the erase operation, as shown in FIG. 9A, a negative high voltage (Vers) is applied to all the word lines in the selected block. The bit line BL and the source line SL are brought into a floating state. Thereby, electrons in the floating gate are emitted to the semiconductor layer by the tunnel current in all the memory cells of the block. As a result, the threshold voltages of these memory cells shift in the negative direction.

In the reading operation shown in FIG. 9B, the voltage Vr (for example, 0 V) of the word line WL0 of the memory cell MS0 selected for reading is set, and the word lines WL1 to WL31 and the selection gate line SG1 of the non-selected memory cells are selected. SG2 is set to a read intermediate voltage Vread that is slightly higher than the power supply voltage. That is, as shown in FIG. 9, memory elements other than the selected memory element function as transfer transistors. Thus, it is detected whether or not a current flows through the memory cell MS0 selected for reading. That is, when the data stored in the memory cell MS0 is “0”, the memory cell MS0 is off, and the bit line BL is not discharged. On the other hand, when “1”, since the memory cell MS0 is turned on, the bit line BL is discharged.

FIG. 10 shows an example of a circuit block diagram of the nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, the memory cell array 52 and the peripheral circuit 54 are formed on the same substrate. The memory cell array 52 has a configuration as shown in FIGS. The configuration of the peripheral circuit 54 is as follows.

A row decoder 62 for selecting a word line and a column decoder 64 for selecting a bit line are provided around the memory cell array 52. The address is sent to the control circuit 58 via the address buffer 56, and the internal row address signal and the internal column address signal are transferred to the row decoder 62 and the column decoder 64, respectively.

For writing and erasing data, a potential obtained by boosting the power supply potential is used. Therefore, a booster circuit 60 controlled by the control circuit 58 according to the operation mode is provided. The output of the booster circuit 60 is supplied to the word line WL and the bit line BL via the row decoder 62 and the column decoder 64. The sense amplifier 66 receives the data output from the column decoder 64. Data read by the sense amplifier 66 is held in the data buffer 68, and the data is randomly accessed under the control of the control circuit 58 and output via the data input / output buffer 70. The write data is temporarily held in the data buffer 68 via the data input / output buffer 70 and transferred to the column decoder 64 under the control of the control circuit 58.

Thus, in the nonvolatile semiconductor memory device, it is necessary to use a potential different from the power supply potential in the memory cell array 52. Therefore, it is desirable that at least the memory cell array 52 and the peripheral circuit 54 are electrically isolated from each other. In this case, insulation isolation can be easily performed by forming a nonvolatile memory element and a transistor of a peripheral circuit with a semiconductor layer formed on an insulating surface as in an embodiment described below. Thus, a non-volatile semiconductor memory device with no malfunction and low power consumption can be obtained.

(Embodiment 2)
In this embodiment, a method for manufacturing a nonvolatile memory element having a structure different from that of the nonvolatile memory element illustrated in FIGS. In this embodiment, the nonvolatile memory element illustrated in FIG. 11 is described. In the nonvolatile memory element shown in FIG. 11, a sidewall 300 is provided on the control gate electrode 24.

In FIG. 11, 10 is a substrate, 12 is a base insulating film, 14 is a semiconductor layer, 29 is a channel formation region, 18a and 18b are source regions or drain regions, 16 is a first insulating film (also referred to as a tunnel insulating film), 20 is a floating gate electrode, 22 is a second insulating film (also called a control insulating film), 24 is a control gate electrode, 300 is a side wall, 26a and 26b are conductive layers, and 28a and 28b are via conductive layers 26a and 26b. The source electrode or drain electrode electrically connected to the source region or drain region 18a, 18b, 28c, a gate wiring electrically connected to the control gate electrode, and 27, an insulating film for passivation.

In the configuration shown in FIG. 11, the base insulating film 12 is formed over the substrate 10, and the semiconductor layer 14 having the source or drain regions 18 a and 18 b and the channel forming region 29 is formed over the base insulating film 12. The first insulating film 16 and the conductive layers 26 a and 26 b are formed on the first insulating film 16, the floating gate electrode 20 is formed on the first insulating film 16, and the second insulating film 16 is formed on the floating gate electrode 20 and the first insulating film 16. The control gate electrode 24 is formed on the second insulating film 22, and the sidewall 300 is formed on the control gate electrode 24. An insulating film 27 is formed on the second insulating film 22, the control gate electrode 24, and the sidewall 300. The source or drain electrodes 28a and 28b are electrically connected to the source or drain regions 18a and 18b through the insulating film 27 and the conductive layers 26a and 26b, and the gate wiring 28c has a contact hole formed in the insulating film 27. And is electrically connected to the control gate electrode 24. The source or drain electrodes 28a and 28b and the source or drain regions 18a and 18b are electrically connected through the conductive layers 26a and 26b. Note that a planarization insulating film may be formed over the insulating film 27.

Next, a method for manufacturing the nonvolatile memory element illustrated in FIG. 11 is described with reference to FIGS. Note that the steps up to the step of forming the conductive layer 19 over the second insulating film 22 and the source or drain regions 18a and 18b are the same as the steps up to FIG.

After the conductive layer 19 is formed over the second insulating film 22 and the source or drain regions 18a and 18b, an insulating film 301 for forming the sidewall 300 is formed over the conductive layer 19 (FIG. 12A). ). As the insulating film 301, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or the like can be used. Instead of the insulating film, a conductive layer such as tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W) may be used. Any film type can be used as long as it has an etching selectivity when etching the control gate electrode and has isotropic coverage with respect to the step shape. Further, it may be a single layer or a laminated film.

Thereafter, anisotropic etching is performed on the insulating film 301. As a result, the sidewall 300 is formed in a self-aligned manner at the step portion 302 generated in the conductive layer 19 due to the presence of the floating gate electrode 20 (FIG. 12B). The sidewall 300 formed in the stepped portion 302 is formed in a symmetrical place or a substantially symmetrical place with the floating gate electrode 20 as the center. Both sidewalls 300 are formed at the same length or almost the same length from the end of the floating gate electrode 20 in the gate length direction.

Next, a resist mask 303 is formed over the conductive layer 19 (FIG. 12C). By etching the conductive layer 19 using the resist mask 303 and the sidewall 300 as a mask, the control gate electrode 24 can be formed in a self-aligned manner with respect to the floating gate electrode 20 (FIG. 12D). In addition, the conductive layers 26a and 26b can be formed. Next, the resist mask 303 is removed.

Next, an insulating film 27 is formed over the entire surface including the second insulating film 22, the conductive layers 26a and 26b, the control gate electrode 24, and the sidewalls 300, and hydrogenation is performed (FIG. 12E). As the insulating film 27, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used. In the case where the above-described activation or the like is not performed, heat treatment, light irradiation with laser light or strong light, RTA treatment, or the like may be performed at this stage in order to activate the source region and the drain region.

Next, a resist mask is formed on the insulating film 27, and the insulating film 27 is etched using the resist mask, thereby forming contact holes located on the source and drain regions 18a and 18b and the control gate electrode 24. .

After the resist mask is removed and a conductive layer is formed, etching is performed using another resist mask to form source or drain electrodes 28a and 28b, gate wiring 28c, and other wiring (source wiring or the like) ( FIG. 12 (E)). Here, the electrode and the wiring are integrally formed, but the electrode and the wiring may be separately formed and electrically connected. As the conductive layer, a laminated film made of Ti, TiN, Al, an Al alloy film, or a combination thereof can be used.

Here, the electrodes and wiring are preferably routed so that the corners are rounded when the substrate 10 is viewed from the vertical direction (ie, the top surface direction). By rounding the corners, dust and the like can be prevented from remaining at the corners of the wiring, and defects caused by the dust can be suppressed and the yield can be improved.

Note that in the above manufacturing method, the n-type or p-type impurity is added only once when forming the source region and the drain regions 18a and 18b, but the low concentration impurity region (LDD region) is added multiple times. It is good also as a structure which provides. Hereinafter, this manufacturing method will be described.

After the structure shown in FIG. 12C is formed, the resist mask is removed, and as shown in FIG. 13A, the source or drain regions 18a and 18b, the sidewall 300, the control gate electrode 24, and the conductive layer 26a. , 26b, etc. Next, an n-type or p-type impurity is added to the semiconductor layer including the source or drain regions 18a and 18b (FIG. 13B). As the n-type or p-type impurity, an impurity imparting the same conductivity as that added to the source or drain regions 18a and 18b is used. As a result, no impurity is added to the portion where the control gate electrode 24 is formed, and the LDD regions 313a and 313b are formed. On the other hand, high-concentration impurity regions 314a and 314b are formed in portions where the control gate electrode 24 is not formed. The high concentration impurity regions 314a and 314b function as a source region and a drain region.

Then, an insulating film 27 is formed on the control gate electrode 24, the conductive layers 26a and 26b, and the source or drain electrodes 28a and 28b and the gate wiring 28c are formed to complete the structure shown in FIG. To do.

In the present embodiment, conductive layers 26a and 26b are provided between the high-concentration impurity regions 314a and 314b and the source or drain electrodes 28a and 28b. Therefore, when the third insulating film 27 is etched, the semiconductor layer is not etched, and an increase in the contact resistance value can be prevented. Therefore, it is possible to manufacture a memory that can perform high-efficiency writing with a low voltage and has good charge retention characteristics.

(Embodiment 3)
In this embodiment, a structure of a nonvolatile memory having a structure different from that illustrated in FIGS. 1 and 11 will be described with reference to FIGS.

The nonvolatile memory element illustrated in FIG. 14A is floating in that first impurity regions (source regions or drain regions) 306a and 306b, second impurity regions 307a and 307b, and the like are provided in the semiconductor layer 14. The gate electrode 20 is different from the structure shown in FIGS. 1 and 11 in that the gate electrode 20 is formed of a first floating gate electrode 20a and a second floating gate electrode 20b.

14A, the base insulating film 12 is formed over the substrate 10, and the first impurity regions 306a and 306b, the second impurity regions 307a and 307b, and the channel formation region are formed over the base insulating film 12. 29, a first insulating film 16 and conductive layers 26a and 26b are formed on the semiconductor layer 14, a floating gate electrode 20 is formed on the first insulating film 16, and a floating gate electrode is formed. 20 and the first insulating film 16, the second insulating film 22 is formed, the control gate electrode 24 is formed on the second insulating film 22, and the sidewall 300 is formed on the control gate electrode 24. Yes. An insulating film 27 is formed on the first insulating film 22, the conductive layers 26 a and 26 b, the control gate electrode 24, and the sidewall 300. The source or drain electrodes 28 a and 28 b are electrically connected to the first impurity regions 306 a and 306 b through contact holes formed in the insulating film 27, and the gate wiring 28 c has contact holes formed in the insulating film 27. And is electrically connected to the control gate electrode 24. Note that the source or drain electrodes 28a and 28b and the first impurity regions 306a and 306b are electrically connected to each other through the conductive layers 26a and 26b. Further, a planarization insulating film may be formed over the insulating film 27.

Next, a method for manufacturing the nonvolatile memory element illustrated in FIG. However, many of the manufacturing methods overlap with those of the second embodiment. Therefore, here, a step different from that of the second embodiment, a step of forming the floating gate electrode 20, and a step of forming the first impurity region and the like will be described.

After the first insulating film 16 is formed on the semiconductor layer 14, a first conductive layer 19a is formed, and a second conductive layer 19b is formed on the first conductive layer 19a (FIG. 15A). )). The first conductive layer 19a and the second conductive layer 19b are preferably formed using different conductive materials. The first conductive layer 19a is preferably formed using a conductive material having good adhesion to the first insulating film 16, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), It is preferably formed using tantalum (Ta), tungsten (W), silicon (Si), or the like. The first conductive layer is preferably formed with a thickness in the range of 25 nm to 35 nm.

The second conductive layer 19b is preferably formed using a conductive material having a low resistivity. For example, tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), or these It is preferably formed using an alloy containing a metal as a main component or a metal compound. Examples of the alloy include an alloy of aluminum and silicon, an alloy of aluminum and neodymium, and the like. Examples of the metal compound include tungsten nitride. The thickness of the second conductive layer is preferably in the range of 100 nm to 600 nm.

There is no particular limitation on the method for forming the first conductive layer 19a and the second conductive layer 19b, and any method such as a sputtering method or a vapor deposition method may be used.

Next, a mask 308 is formed over the second conductive layer 19b. Then, the first conductive layer 19a and the second conductive layer 19b are etched, and the first floating gate electrode 20a and the third conductive layer 19c are etched with respect to the horizontal plane of the respective conductive layers. It is formed so as to have a shape having an inclination (FIG. 15B).

Next, with the mask 308 provided, the third conductive layer 19c is selectively etched to form the second floating gate electrode 20b. At this time, it is preferable that the second floating gate electrode 20b is etched and processed under a highly anisotropic condition so that the side wall of the second floating gate electrode 20b is perpendicular to the horizontal plane. In this manner, the second floating layer is shorter on the first floating gate electrode 20a provided on the first insulating film 16 side than the first floating gate electrode 20a (that is, the gate length is shorter). A gate electrode 20b is formed (FIG. 15C). In the present embodiment, a combination of the first floating gate electrode 20a and the second floating gate electrode 20b is referred to as a floating gate electrode 20.

Next, n-type or p-type impurities are added using the floating gate electrode 20 as a mask to provide first impurity regions 306a and 306b and second impurity regions 307a and 307b (FIG. 15D). The second impurity regions 307a and 307b become low concentration impurity regions by the first floating gate electrode 20a. Note that a portion sandwiched between the second impurity regions 307 a and 307 b becomes a channel formation region 29.

After the structure of FIG. 15D is manufactured, the sidewall 300 is formed by the method described in Embodiment 2, the control gate electrode 24, the conductive layers 26a and 26b are formed, the insulating film 27 is formed, and the source The electrode or drain electrodes 28a and 28b and the gate wiring 28c are formed to complete the configuration shown in FIG.

In this embodiment, the sidewall 300 is provided in the control gate electrode 24. However, the sidewall 300 is not necessarily provided. As described in Embodiment 1, the sidewall may not be provided.

Further, as illustrated in FIG. 14B, a structure in which first impurity regions 312a and 312b, second impurity regions 311a and 311b, and third impurity regions 310a and 310b are provided may be employed. Here, the first impurity regions 312a and 312b function as a source region or a drain region.

After the structure of FIG. 15D is manufactured, a second insulating film 22 is formed as shown in FIG. 16A by the method shown in Embodiment Mode 2, a sidewall 300 is formed, and a control gate electrode is formed. 24. Conductive layers 26a and 26b are formed.

Next, an n-type or p-type impurity is added. As the n-type or p-type impurity, an impurity imparting the same conductivity as that added to the first impurity region and the second impurity region is used. Impurities are not added under the control gate electrode 24, and the first impurity regions 312a and 312b, the second impurity regions 311a and 311b, and the third impurity regions 310a and 310b can be formed. In this case, the n-type or p-type impurity concentration included in the first impurity regions 312a and 312b is higher than the n-type or p-type impurity concentration included in the second impurity regions 311a and 311b. The n-type or p-type impurity concentration included in the impurity regions 311a and 311b is higher than the n-type or p-type impurity concentration included in the third impurity regions 310a and 310b.

Then, as described in Embodiment 1, the insulating film 27 is formed on the control gate electrode 24, the conductive layers 26a and 26b, and the source or drain electrodes 28a and 28b and the gate wiring 28c are formed. The configuration shown in FIG. 16B and FIG. 14B is completed.

In the present embodiment, conductive layers 26a and 26b are provided between the first impurity regions 312a and 312b and the source or drain electrodes 28a and 28b. Therefore, when the third insulating film 27 is etched, the semiconductor layer is not etched, and an increase in the contact resistance value can be prevented. Therefore, it is possible to manufacture a memory that can perform high-efficiency writing with a low voltage and has good charge retention characteristics.

The nonvolatile semiconductor memory device according to the present invention will be described below. In the structure of the present invention described below, reference numerals indicating the same elements are used in common in different drawings, and repetitive description in that case may be omitted.

In this embodiment, an example of a manufacturing process of a nonvolatile semiconductor memory device will be described with reference to drawings. Here, in the nonvolatile semiconductor memory device, an element such as a non-volatile memory element that constitutes a memory portion and a transistor that constitutes a logic portion that is provided on the same substrate as the memory portion and controls the memory portion. Are shown simultaneously. FIG. 5 is a schematic diagram of a memory portion in the nonvolatile semiconductor memory device described in this embodiment.

The memory portion shown in this embodiment includes a plurality of memory cells each having a control transistor S and a nonvolatile memory element M. In FIG. 5, one memory cell MS01 is formed by the control transistor S01 and the nonvolatile memory element M01. Similarly, the control transistor S02 and the nonvolatile memory element M02, the control transistor S03 and the nonvolatile memory element M03, the control transistor S11 and the nonvolatile memory element M11, the control transistor S12 and the nonvolatile memory element M12, the control A memory cell is formed by the transistor S13 and the nonvolatile memory element M13.

The gate electrode of the control transistor S01 is connected to the word line WL1, one of the source and the drain is connected to the bit line BL0, and the other is connected to the source or the drain of the nonvolatile memory element M01. The gate electrode of the nonvolatile memory element M01 is connected to the word line WL11, one of the source and the drain is connected to the source or the drain of the control transistor S01, and the other is connected to the source line SL.

Note that the control transistor provided in the memory portion has a higher driving voltage than the transistor provided in the logic portion. Therefore, the gate insulating film of the transistor provided in the memory portion and the transistor provided in the logic portion are formed with different thicknesses. It is preferable to do. For example, it is preferable to provide a thin film transistor with a thin gate insulating film when the driving voltage is small and it is desired to reduce the variation in threshold voltage. When the driving voltage is large and the gate insulating film is required to have a withstand voltage, the gate insulating film is It is preferable to provide a thick thin film transistor.

Therefore, in this embodiment, an insulating film having a small film thickness is formed for a transistor in the logic portion where the driving voltage is small and the threshold voltage variation is to be small, and the withstanding voltage of the gate insulating film is required because the driving voltage is large. A case where an insulating film having a large thickness is formed for a transistor in a memory portion will be described below with reference to the drawings. 17A, 18A, and 19A are top views of the elements in the memory portion, and FIGS. 17B, 18B, and 19B are top views of the elements in the logic portion. 20 to 24 are sectional views taken along lines A-B, C-D, EF, and GH in FIGS. In addition, a thin film transistor provided in the logic portion is shown between AB and CD, a non-volatile memory element provided in the memory portion is shown between EF, and a thin film transistor provided in the memory portion is shown between GH. Show. In this embodiment, a thin film transistor provided between A and B is a p-channel type, a thin film transistor provided between C and D, a thin film transistor provided between GH and an n channel type, and a carrier of a nonvolatile memory element provided between EFs. Although the case where movement is performed by electrons will be described, the nonvolatile semiconductor device of the present invention is not limited to this.

First, island-shaped semiconductor layers 104, 106, 108, and 110 are formed over the substrate 100 with the insulating film 102 interposed therebetween, and the first insulating film is formed so as to cover the island-shaped semiconductor layers 104, 106, 108, and 110. 112, 114, 116, and 118 are formed (FIG. 20A).

The island-shaped semiconductor layers 104, 106, 108, and 110 are formed using silicon (Si) as a main component by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over the insulating film 102 formed in advance on the substrate 100. An amorphous semiconductor layer can be formed using (for example, Si _x Ge _1-x ) or the like, and the amorphous semiconductor layer can be crystallized and then selectively etched. The crystallization of the amorphous semiconductor layer may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed.

In the case where the semiconductor layer is crystallized or recrystallized by laser light irradiation, an LD-excited continuous wave (CW) laser (YVO ₄ , second harmonic (wavelength 532 nm)) is used as a laser light source. Can be used. The second harmonic is not particularly limited to the second harmonic, but the second harmonic is superior to higher harmonics in terms of energy efficiency. When the semiconductor layer is irradiated with the CW laser, energy is continuously given to the semiconductor layer. Therefore, once the semiconductor layer is in a molten state, the molten state can be continued. Furthermore, the solid-liquid interface of the semiconductor layer can be moved by scanning with a CW laser, and crystal grains that are long in one direction can be formed along the direction of this movement. The solid laser is used because the output stability is higher than that of a gas laser or the like, and stable processing is expected. Note that not only the CW laser but also a pulse laser having a repetition frequency of 10 MHz or more can be used. If a pulse laser with a high repetition frequency is used, the semiconductor layer can always remain in a molten state if the laser pulse interval is shorter than the time from when the semiconductor layer melts until it solidifies. A semiconductor layer including crystal grains that are long in one direction can be formed. Other CW lasers and pulse lasers with a repetition frequency of 10 MHz or more can also be used. For example, examples of the gas laser include an Ar laser, a Kr laser, and a CO ₂ laser. Examples of the solid-state laser include a YAG laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a Y ₂ O ₃ laser, and a YVO ₄ laser. Further, there are ceramic lasers such as YAG laser, Y ₂ O ₃ laser, GdVO ₄ laser, and YVO ₄ laser. Examples of the metal vapor laser include a helium cadmium laser. In addition, it is preferable to emit laser light in TEM ₀₀ (single transverse mode) in a laser oscillator because energy uniformity of a linear beam spot obtained on the irradiated surface can be improved. In addition, a pulsed excimer laser may be used.

The substrate 100 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate), a semiconductor substrate such as a ceramic substrate, and a Si substrate. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate.

The insulating film 102 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. Form. For example, in the case where the insulating film 102 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. In this manner, by forming the insulating film 102 functioning as a blocking layer, alkali metal such as Na or alkaline earth metal from the substrate 100 can be prevented from adversely affecting the element formed thereon. Note that the insulating film 102 may be omitted when quartz is used for the substrate 100.

The first insulating films 112, 114, 116, and 118 can be formed by performing heat treatment, plasma treatment, or the like on the semiconductor layers 104, 106, 108, and 110. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layers 104, 106, 108, and 110 by high-density plasma treatment, an oxide film and a nitride film are formed on the semiconductor layers 104, 106, 108, and 110, respectively. Alternatively, first insulating films 112, 114, 116, and 118 that are to be oxynitride films are formed. In addition, you may form by plasma CVD method or a sputtering method.

For example, in the case where a semiconductor layer containing Si as a main component is used as the semiconductor layers 104, 106, 108, and 110 and oxidation treatment or nitridation treatment is performed by high-density plasma treatment, the first insulating films 112, 114, 116, and 118 are performed. As a result, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is formed. Further, after the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the semiconductor layers 104, 106, 108, and 110, and a film containing oxygen and nitrogen (hereinafter referred to as a “silicon oxynitride film”) is formed over the silicon oxide film. The first insulating films 112, 114, 116, and 118 are films in which a silicon oxide film and a silicon oxynitride film are stacked.

Here, the first insulating films 112, 114, 116, and 118 are formed with a thickness of 8 nm to 20 nm, preferably 8 nm to 10 nm. For example, the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment to form a silicon oxide film of about 10 nm on the surface of the semiconductor layers 104, 106, 108, and 110, and then the high-density plasma treatment is performed. Nitriding is performed to form a silicon oxynitride film having a thickness of about 2 nm on the surface of the silicon oxide film. In this case, the thickness of the silicon oxide film formed on the surface of the semiconductor layers 104, 106, 108, 110 is about 8 nm. This is because the silicon oxynitride film is reduced by the amount formed. At this time, it is preferable that the oxidation treatment and the nitriding treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

Note that in the case where the semiconductor layer is oxidized by high-density plasma treatment, an atmosphere containing oxygen (for example, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr And at least one of Xe), oxygen, or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas atmosphere. On the other hand, in the case of nitriding a semiconductor layer by high-density plasma treatment, an atmosphere containing nitrogen (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe)) Under nitrogen, hydrogen, and rare gas atmosphere, or NH ₃ and rare gas atmosphere).

As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. When the high-density plasma treatment is performed in a rare gas atmosphere, the first insulating films 112, 114, 116, and 118 are formed of at least one of the rare gases (He, Ne, Ar, Kr, and Xe) used for the plasma treatment. In the case where Ar is used, the first insulating films 112, 114, 116, and 118 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor layers 104, 106, 108, and 110) formed on the substrate 100 is low, the object to be processed is damaged by the plasma. Can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. When plasma is formed, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

In this embodiment, when an object to be processed is oxidized by high-density plasma treatment, a mixed gas of oxygen (O ₂ ), hydrogen (H ₂ ), and argon (Ar) is introduced. The mixed gas used here may be introduced with oxygen in a range of 0.1 sccm to 100 sccm, hydrogen in a range of 0.1 sccm to 100 sccm, and argon in a range of 100 sccm to 5000 sccm. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

In addition, when performing nitriding treatment by high-density plasma treatment, a mixed gas of nitrogen (N ₂ ) and argon (Ar) is introduced. The mixed gas used here may be introduced with nitrogen at 20 sccm to 2000 sccm and argon at 100 sccm to 10,000 sccm. For example, nitrogen may be introduced at 200 sccm and argon at 1000 sccm.

In this embodiment, the first insulating film 116 formed over the semiconductor layer 108 provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating film 116 is, the easier it is for the tunnel current to flow and the higher speed operation of the memory becomes possible. In addition, the thinner the first insulating film 116 is, the more charge can be accumulated in a floating gate formed later at a low voltage, so that power consumption of the semiconductor device can be reduced. Therefore, the first insulating films 112, 114, 116, and 118 are preferably formed thin.

In general, there is a thermal oxidation method as a method for forming a thin insulating film over a semiconductor layer. However, when a substrate having a sufficiently low melting point such as a glass substrate is used as the substrate 100, the first method is performed by the thermal oxidation method. It is very difficult to form the insulating films 112, 114, 116, and 118. In addition, an insulating film formed by a CVD method or a sputtering method includes defects inside the film, so that the film quality is not sufficient, and there is a problem that defects such as pinholes occur when the film thickness is thin. Further, in the case where an insulating film is formed by a CVD method or a sputtering method, the end of the semiconductor layer is not sufficiently covered, and the conductive layer and the like which are formed later on the first insulating film 116 and the semiconductor layer leak. There is a case. Therefore, as shown in this embodiment, by forming the first insulating films 112, 114, 116, and 118 by high-density plasma treatment, an insulating film denser than the insulating film formed by the CVD method, the sputtering method, or the like can be obtained. In addition, end portions of the semiconductor layers 104, 106, 108, and 110 can be sufficiently covered with the first insulating films 112, 114, 116, and 118. As a result, high-speed operation and charge retention characteristics as a memory can be improved. Note that in the case where the first insulating films 112, 114, 116, and 118 are formed by CVD or sputtering, high-density plasma treatment is performed after forming the insulating film, and the surface of the insulating film is oxidized or nitrided. Alternatively, oxynitriding treatment is preferably performed.

Thereafter, a resist 123 is formed on the first insulating films 112, 114, 116, and 118, and the first insulating film 118 formed on the semiconductor layer 110 so that the surface of the semiconductor layer 110 is partially exposed. Is selectively removed. Then, an impurity region 162 is formed by introducing an impurity element into the semiconductor layer 110 using a portion covered with the first insulating film 118 as a mask (see FIG. 20B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into the semiconductor layer 110 as the impurity element. Note that the impurity region 162 functions as a source region or a drain region.

Then, the resist 123 is removed, and the first conductive layer 120 is formed so as to cover the first insulating films 112, 114, 116, and 118 and the impurity region 162 formed in the semiconductor layer 110 (FIG. 20C )). In this embodiment, the first conductive layer 120 is preferably formed with a thickness of 10 nm to 50 nm in order to facilitate introduction of impurities into the semiconductor layer 110 in a later step.

The first conductive layer 120 is made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si) by sputtering or CVD. A film made of a nitride of the element (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film (typically a Mo—W alloy or Mo—Ta) in which the elements are combined. Alloy) or a silicide film of the above elements (typically, a tungsten silicide film, a titanium silicide film, or a nickel silicide film). Impurities such as phosphorus and boron may be added to the silicon film. Alternatively, germanium or a germanium compound film may be used.

Next, the first conductive layer 120 formed over the first insulating films 112, 114, 116, and 118 is selectively removed, and the first conductive layer 120 is partially formed over the semiconductor layers 104, 106, 108, and 110. The conductive layer 120 is left, and second conductive layers 121 and 127 are formed (FIG. 21A). Here, the first conductive layer 120 formed over the semiconductor layers 104, 106, 108, and 110 is partially covered with a resist 122, and the first conductive layer 120 is etched to form the first conductive layer 120. This is selectively removed (FIGS. 17 and 21A). Note that here, the conductive layer 120 over the channel formation region 160 sandwiched between the impurity regions 162 of the semiconductor layer 110 is removed, and the second conductive layer 127 formed over the semiconductor layer 110 serves as an impurity of the semiconductor layer 110. It is formed so as to be in contact with the region 162. Here, the second conductive layer 121 formed over the semiconductor layer 108 functions as a floating gate electrode of the memory portion.

Next, impurity regions are formed in specific regions of the semiconductor layers 106 and 108. Here, a resist 124 is formed so as to cover the semiconductor layers 104 and 110, and an impurity element is introduced into the semiconductor layers 106 and 108 that are not covered with the resist 124 or the second conductive layer 121, thereby the impurity region 126. 156 are formed (FIG. 21B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into the semiconductor layers 106 and 108 as the impurity element. Note that the impurity regions 126 and 156 function as a source region or a drain region.

Next, an impurity region is formed in a specific region of the semiconductor layer 104. Here, the resist 124 covering the semiconductor layers 104 and 110 is removed, a resist 164 is formed so as to cover the semiconductor layers 106, 108, and 110, and the second conductive layer 121 over the resist 164 or the semiconductor layer 104 is covered. An impurity region 125 is formed by introducing an impurity element into the uncovered semiconductor layer 104 (FIG. 21C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the semiconductor layer 104 as the impurity element. Note that the impurity region 125 functions as a source region or a drain region.

Next, a second insulating film 128 is formed over the second conductive layers 121 and 125 and the first insulating films 112, 114, 116, and 118 so as to cover the semiconductor layers 104, 106, 108, and 110 ( FIG. 22 (A)).

The second insulating film 128 is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by using a CVD method, a sputtering method, or the like. A single layer or a stacked layer is formed using materials. For example, when the second insulating film 128 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 20 nm to 60 nm by a CVD method. In the case where the second insulating film 128 is provided in a three-layer structure, a silicon oxynitride film is formed as the first insulating film, a silicon nitride film is formed as the second insulating film, A silicon oxynitride film is formed as the insulating film. Alternatively, germanium nitride may be used for the second insulating film 128.

Note that the second insulating film 128 formed over the semiconductor layer 108 functions as a control insulating film in a nonvolatile memory element to be completed later.

Next, a resist 130 is formed so as to cover the second insulating film 128 formed above the semiconductor layers 104, 106, 108, and 110 (FIG. 22B). Note that the resist 130 formed above the semiconductor layers 104, 106, and 108 is formed so as to cover the upper portion of the second conductive layer 121 and not to cover a part of the upper portions of the impurity regions 125, 126, and 156. After that, the second insulating film 128 is removed by etching so that part of the impurity regions 125, 126, and 156 is exposed.

Next, a conductive layer 136 is formed so as to cover the semiconductor layers 104, 106, 108, and 110 (see FIG. 23A). Here, an example is shown in which the conductive layer 136 is formed as a single layer as the conductive layer. Needless to say, the conductive layer may be formed of a stacked structure of two layers or three or more layers.

The conductive layer 136 was selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. It can be formed of an element or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

Here, the conductive layer 136 is formed using tungsten. In addition, as the conductive layer 136, a single layer or a stacked film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used.

Next, the conductive layer 136 is selectively etched and removed, so that the conductive layer 136 is left in a part above the semiconductor layers 104, 106, 108, and 110, so that the conductive layer 136 is over the semiconductor layers 104, 106, and 108. Third conductive layers 140, 142, and 144 are formed on the formed second conductive layer 121, and a third conductive layer 146 is formed above the channel formation region 160 formed in the semiconductor layer 110. In addition, the conductive layer 136 is left on part of the impurity regions 125, 126, and 156 of the semiconductor layers 104, 106, and 108 to form a third conductive layer 138 (see FIGS. 23B and 18). Note that the conductive layer 144 formed over the semiconductor layer 108 in the memory portion functions as a control gate in a nonvolatile memory element to be completed later. In addition, the conductive layer 146 provided over the semiconductor layer 110 functions as a gate electrode in a transistor to be completed later. Further, the conductive layer 140 formed over the semiconductor layer 104 is electrically connected to the second conductive layer 121, so that the conductive layer 140 and the conductive layer 121 function as a gate electrode in a transistor which is completed later. In addition, the conductive layer 142 formed over the semiconductor layer 106 is electrically connected to the second conductive layer 121, so that the conductive layer 142 and the conductive layer 121 function as a gate electrode in a transistor which is completed later.

Next, an insulating film 172 is formed so as to cover the second insulating film 128 and the third conductive layers 138, 140, 142, 144, and 146. After that, a resist is selectively formed over the insulating film 172, and dry etching is performed to form contact holes in which the second conductive layer 127 and the third conductive layer 138 are exposed. Then, a conductive layer 174 in contact with the second conductive layer 127 and the third conductive layer 138 is formed through the contact hole (see FIGS. 24 and 19). Note that the impurity regions 125, 126, 156, and 162 formed in the semiconductor layers 104, 106, 108, and 110 are electrically connected to the conductive layer 174. In addition, the conductive layer 174 functions as a source wiring or a drain wiring.

The insulating film 172 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like by CVD or sputtering. Single layer made of an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as siloxane resin Alternatively, a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

The conductive layer 174 is formed by a CVD method, a sputtering method, or the like using aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper ( Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive layer 174 has, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. Adopt it. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive layer 174 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

In this embodiment, the third conductive layer is provided between the impurity region functioning as the source region or the drain region and the wiring functioning as the source electrode or the drain electrode. Therefore, when the insulating film provided on the third conductive layer is etched, the semiconductor layer is not etched, and an increase in the contact resistance value can be prevented. Therefore, it is possible to manufacture a memory that can perform high-efficiency writing with a low voltage and has good charge retention characteristics. As shown in this embodiment, the transistor of the logic portion as well as the memory portion has the structure of the present invention, so that the contact resistance value is further prevented and a high-performance nonvolatile semiconductor memory device is manufactured. be able to. This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

  In this embodiment, a case where a plurality of nonvolatile memory elements are provided in one island-like semiconductor layer in the structure shown in Embodiment 1 will be described with reference to the drawings. In addition, when referring to the same thing as the said Example, it shows using the same code | symbol and abbreviate | omits description. 25 is a top view, and FIG. 26 is a cross-sectional view taken along lines EF and GH in FIG.

  The nonvolatile semiconductor memory device shown in this embodiment includes island-shaped semiconductor layers 200a and 200b that are electrically connected to the bit lines BL0 and BL1, respectively. The island-shaped semiconductor layers 200a and 200b are provided in the island-shaped semiconductor layers 200a and 200b, respectively. A plurality of nonvolatile memory elements are provided (see FIGS. 25 and 26). Specifically, in the semiconductor layer 200a, a NAND cell 202a having a plurality of nonvolatile memory elements M0 to M31 is provided between the select transistors S01 and S02. In the semiconductor layer 200b, a NAND cell 202b having a plurality of nonvolatile memory elements is provided between the select transistors. Further, by providing the semiconductor layers 200a and 200b separately, the adjacent NAND cells 202a and NAND cells 202b can be insulated and separated.

  Further, by providing a plurality of nonvolatile memory elements in one island-like semiconductor layer, the nonvolatile memory elements can be more integrated and a large-capacity nonvolatile semiconductor memory device can be formed.

  This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, an application example of a semiconductor device including the above-described nonvolatile semiconductor memory device of the present invention and capable of inputting and outputting data without contact will be described with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 27A). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control the circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, the nonvolatile semiconductor memory device of the present invention can be applied to the memory circuit 880. In the nonvolatile semiconductor memory device of the present invention, since the driving voltage can be lowered, it is possible to extend the distance in which data can be communicated without contact.

As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). It is good also as a type which supplies a power supply voltage to.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 27B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by a belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 27C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

In addition, the nonvolatile semiconductor memory device of the present invention can be used for electronic devices in various fields equipped with a memory. For example, as an electronic device to which the nonvolatile semiconductor memory device of the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), Plays back recording media such as computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines or electronic books), and image playback devices (specifically DVDs (digital versatile discs)) equipped with recording media And an apparatus provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

28A and 28B show a digital camera. FIG. 28B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter button 2115, and the like. In addition, a nonvolatile memory 2116 that can be taken out is provided, and data captured by the digital camera is stored in the memory 2116. A nonvolatile semiconductor memory device formed using the present invention can be applied to the memory 2116.

FIG. 28C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the memory 2125 and played back. A nonvolatile semiconductor memory device formed using the present invention can be applied to the memory 2125.

FIG. 28D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 28D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the memory portion 2132, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating the operation unit 2133 using a NAND-type nonvolatile memory having a recording capacity of 20 gigabytes or more and 200 gigabytes (GB) or less. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable audio device. Note that the nonvolatile semiconductor memory device provided in the memory portion 2132 may be removable.

FIG. 28E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, a memory portion 2144, and the like. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the memory portion 2144, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating an operation key 2143 using a NAND nonvolatile memory having a recording capacity of 20 gigabytes or more and 200 gigabytes (GB) or less. Note that the nonvolatile semiconductor memory device provided in the memory portion 2144 may be removable.

As described above, the applicable range of the nonvolatile semiconductor memory device of the present invention is so wide that it can be used for electronic devices in various fields as long as it has a memory.

1 is a cross-sectional view for explaining a main structure of a nonvolatile semiconductor memory device according to the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. The figure explaining the structure of a plasma processing apparatus. The figure which shows an example of the equivalent circuit of a non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NOR type non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NAND type non-volatile memory cell array. 4A and 4B illustrate a write operation of a NAND nonvolatile memory. The figure explaining erase and read-out operation of NAND type non-volatile memory. 1 is a diagram illustrating an example of a circuit block diagram of a nonvolatile semiconductor memory device. 1 is a cross-sectional view for explaining a main structure of a nonvolatile semiconductor memory device according to the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 1 is a cross-sectional view for explaining a main structure of a nonvolatile semiconductor memory device according to the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. 1 is a diagram showing an example of a nonvolatile semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention. The figure for demonstrating the structure of the conventional non-volatile semiconductor memory device.

Explanation of symbols

10 Substrate 12 Underlying insulating film 14 Semiconductor layer 16 Insulating film 20 Floating gate electrode 22 Insulating film 24 Control gate electrodes 26a and 26b Conductive layer 27 Insulating film 29 Channel formation region

Claims (6)

A semiconductor layer having a channel formation region, a source region and a drain region;
A first insulating film covering a part of the source region and the drain region and the channel formation region;
A floating gate electrode on the first insulating film;
A second insulating film covering the floating gate electrode;
A control gate electrode on the second insulating film;
A first conductive layer on the source region;
A second conductive layer on the drain region;
A third insulating film on the second insulating film, the control gate electrode, the first conductive layer and the second conductive layer;
A third conductive layer in contact with the first conductive layer through the third contact hole formed in the insulating film, and a fourth conductive layer in contact with the second conductive layer, and
Said third conductive layer and the source region is electrically connected through the first conductive layer, the fourth conductive layer and the drain region is electrically through the second conductive layer Connected to
The non-volatile semiconductor memory device, wherein the first conductive layer, the second conductive layer, and the control gate electrode are formed by selectively etching the same conductive layer. A semiconductor layer having a channel formation region, a source region and a drain region;
A first insulating film covering a part of the source region and the drain region and the channel formation region;
A floating gate electrode on the first insulating film;
A second insulating film covering the floating gate electrode;
A control gate electrode on the second insulating film;
A first conductive layer on the source region;
A second conductive layer on the drain region;
A third insulating film on the second insulating film, the control gate electrode, the first conductive layer and the second conductive layer;
A third conductive layer in contact with the first conductive layer through the third contact hole formed in the insulating film, and a fourth conductive layer in contact with the second conductive layer, and
Said third conductive layer and the source region is electrically connected through the first conductive layer, the fourth conductive layer and the drain region is electrically through the second conductive layer Connected to
The control gate electrode is formed so as to cover the floating gate electrode through the second insulating film,
A side wall is formed in the step portion of the control gate electrode generated by the floating gate electrode,
The non-volatile semiconductor memory device, wherein the first conductive layer, the second conductive layer, and the control gate electrode are formed by selectively etching the same conductive layer. In claim 1 or claim 2,
The non-volatile semiconductor memory device, wherein the floating gate electrode has a stacked structure of a first floating gate electrode and a second floating gate electrode. In claim 3 ,
The first floating gate electrode is provided on the first insulating film side, and the second floating gate electrode having a shorter width than the first floating gate electrode is provided on the first floating gate electrode. A non-volatile semiconductor memory device. Forming a first insulating film on the semiconductor layer;
Forming a floating gate electrode on the first insulating film;
An impurity element is introduced into the semiconductor layer using the floating gate electrode as a mask to form a source region and a drain region,
Forming a second insulating film covering the floating gate electrode;
Etching a part of the first insulating film and the second insulating film to expose a part of the source region and the drain region,
Forming a first conductive layer on the second insulating film, the exposed source region and the drain region;
Etching the first conductive layer to form a control gate electrode on the second insulating film;
Forming a second conductive layer on the exposed source region and a third conductive layer on the exposed drain region;
Forming a third insulating film on the second insulating film, the control gate electrode, the second conductive layer, and the third conductive layer;
Opening a contact hole in the third insulating film through which the second conductive layer and a part of the third conductive layer are exposed;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a source electrode on the exposed second conductive layer; and forming a drain electrode on the exposed third conductive layer. Forming a first insulating film on the semiconductor layer;
Forming a floating gate electrode on the first insulating film;
An impurity element is introduced into the semiconductor layer using the floating gate electrode as a mask to form a source region and a drain region,
Forming a second insulating film covering the floating gate electrode;
Etching a part of the first insulating film and the second insulating film to expose a part of the source region and the drain region,
Forming a first conductive layer on the second insulating film, the exposed source region and the drain region;
Forming a third insulating film on the first conductive layer;
Etching the third insulating film to form a side wall at the step formed by the floating gate electrode,
Etching the first conductive layer to form a control gate electrode on the second insulating film;
Forming a second conductive layer on the exposed source region and a third conductive layer on the exposed drain region;
Forming a fourth insulating film on the second insulating film, the control gate electrode, the second conductive layer, and the third conductive layer;
Opening a contact hole in the fourth insulating film through which a part of the second conductive layer and the third conductive layer is exposed;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a source electrode on the exposed second conductive layer; and forming a drain electrode on the exposed third conductive layer.

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