JP3429941B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, flash EE has been realized by using a MOSFET having a floating gate and a control gate.
Non-volatile storage devices such as PROMs have been implemented.
By storing carriers in the floating gate, the MOSFE
The change in the threshold voltage of T is used to store information,
It is for reading. Polycrystalline silicon is usually used for the floating gate. This floating gate MOSFET
By using, it is possible to store 1-bit information for a long time with only one transistor. Flash EEP
As a memory cell structure of ROM, Nikkei Electronics n
The conventional structure and contactless cell structure described in o.444 pp151-157, 1988 are listed.

Another prior art related to the present invention is K. K.
Yano et al, IEEE International Electron Devices Me
eting pp541-544, 1993, and T. Ishii et al, Inter.
national Conference on Solid State Devices and
Materials pp201-203, 1995 describes single-electron memory using polycrystalline silicon. In this technique, a channel that is a current path and a storage region that captures electrons are simultaneously formed by a polycrystalline silicon thin film.
Information is stored by utilizing the fact that the threshold voltage changes when electrons are trapped in the storage area. 1 by storing one electron
It is characterized by storing bits. By utilizing the crystal grains of polycrystalline silicon, a structure that is effectively smaller than the processed dimension is realized, and it is possible to operate even at room temperature.

[0004]

Due to the progress of the fine structure, the area of memory cells of various memories such as DRAM, SRAM and flash memory has been reduced. Correspondence between processing dimensions and cell area is generally decided by the memory method,
This is evaluated from the area occupied when the structure required for one cell is arranged on the semiconductor substrate surface. A DRAM can realize one cell with one transistor and one capacitor, and realizes a storage capacity one generation ahead even with the same processing size as an SRAM that requires six transistors. Therefore, it is important to realize a smaller area cell with the same processing size. Currently 1
A single-cell flash memory with a transistor can realize a cell with the smallest area.
This is considered to be the limit in the memory forming the S structure.

On the other hand, a single-electron element utilizing the fact that the Coulomb repulsive force works effectively when electrons are taken in and out from a minute dot of metal or semiconductor, operates in a very small structure of about 10 nm in principle. It has the advantage of being possible. However, in the actual device fabrication, the processing size is limited by lithography technology and the like. Furthermore, in the conventional device, the size of the lead-out portion such as the source region and the drain region is large, and no device structure has been proposed that takes advantage of the fact that it can be integrated and made smaller.

Therefore, it is an object of the present invention to provide a semiconductor memory device and a semiconductor memory device which are suitable for high integration in a small area and which overcome the conventional limit.

[0007]

The present invention provides a source region,
It is characterized in that it can be manufactured in a small area by providing drain regions above and below and running a channel in the vertical direction.

More specifically, the semiconductor device according to the exemplary embodiment of the present invention includes a source (76) and a drain region (77).
The drain region (77) has a source through the insulating film (82).
It is provided above or below the source region (76), and the source region (7
6) is connected to the drain region (77) via the channel region (78), and the channel region (78) is connected to the gate electrode (80) via the gate insulating film (81). , Having a carrier confinement region (79) in the vicinity of the channel region (78) and retaining the carrier in the carrier confinement region (79) to change the threshold voltage of the semiconductor element for storage. (See FIG. 1).

Further, in the embodiment in which a plurality of gate electrodes are provided in the vertical direction and a channel is provided on the side surface of the step, a small area can be formed in the source (21),
The gate electrode (19) has a drain region (22) and a plurality of gate electrodes (19) (20) provided above and below each other with an insulating film (85) interposed therebetween, and with the insulating film (26) interposed therebetween. ) (20) has a channel region (24) (25) provided on the side surface of the source region (2
1) is connected to the drain region (2) via the channel region (24) (25).
2) and has a carrier confinement region (24) (25) in the vicinity of the channel region (24) (25). Memorization is performed by changing the threshold voltage, and the carrier confinement region (24) (25) has an average minor axis of 10 nm.
It is characterized by comprising the following fine particles of semiconductor or metal (see FIG. 4).

Other means, objects and features of the present invention will be apparent from the following embodiments.

[0011]

DETAILED DESCRIPTION OF THE INVENTION

Example 1 A memory element according to a specific example of the present invention will be described below. FIG. 1 shows a structural diagram of a memory element according to this embodiment. FIG. 1A is a bird's-eye view and FIG. 1B is a sectional view.
The source (76) and the drain (77) are regions made of high-impurity-concentration n-type polycrystalline silicon with a SiO2 insulating film (82) therebetween. A channel portion (78) having a thickness of 20 nm and a width of 150 nm made of P-type polycrystalline silicon is formed on the side surface of the SiO2 insulating film (82), and a carrier made of polycrystalline silicon is provided with a thin insulating film (87) interposed therebetween. Confinement Area (79)
Are formed. The channel part (78) and the carrier confinement region (79) are covered with the gate electrode (8) through the SiO2 insulating film (81).
Connected to 0). The distance between the gate electrode (80) and the carrier confinement region (79) is 30 nm. Channel part (7
By separately providing 8) and the carrier confinement region (79), the channel part and the carrier confinement region described later in Example 3 are separately designed, respectively, as compared with the structure in which they are collectively formed.
Since it can be formed, it has a high degree of freedom.
In particular, there is an advantage that the height and width of the potential barrier can be artificially determined by selecting the material and film thickness of the insulating film (87) between the channel part (78) and the carrier confinement region (79).
In this embodiment, the source is located below the drain and the drain, but this may be reversed. Further, in the present embodiment, the carrier is an electron, and in the following embodiments, it is also an electron, but the carrier may be a hole.

In the memory element of this embodiment, the source (76) and drain (77) regions are vertically overlapped with each other, and the area can be reduced accordingly. Further, the channel area (78) also has a vertically running structure to reduce the element area. The storage elements of this embodiment can be repeatedly arranged to store more data. This also applies to the storage elements of the following embodiments.

The operation of the storage element of this embodiment will be described. Writing and erasing are performed by changing the potential of the gate electrode (80). Apply a constant voltage between the source (76) and drain (77),
When a gate voltage is applied, electrons are induced in the polycrystalline silicon thin film of the channel (78) and current starts flowing. When a large gate voltage is applied, the potential difference between the channel region (78) and the carrier confinement region (79) increases, and eventually the electrons cross the potential barrier of the insulating film (87) between them due to tunneling or thermal excitation. It is injected into the carrier confinement region (79). As a result, the threshold value shifts to the larger side, and the current value decreases even with the same gate voltage. Information is read by observing the magnitude of this current value. Erasing is performed by swinging the gate voltage in the opposite direction.

Next, the manufacturing process of this embodiment will be described. After the surface of the P type substrate (86) is oxidized to form the SiO2 film (84), n
-Type polycrystalline silicon film, SiO2 film, n-type polycrystalline silicon film, and SiO2 film are deposited in this order, and the deposited four layers are collectively etched by using a photoresist as a mask to form a source (76) and a drain (77). ) Region, SiO2 films (82) and (83) are formed (FIG. 16A). Since they are collectively formed in this way, the number of lithography steps is small even if the structure is a laminated structure. Then, after depositing 20 nm of a (amorphous) -Si, it is crystallized by heat treatment. This polycrystalline silicon is etched using the photoresist as a mask to
(76) and the drain (77) region are processed into a linear shape to form a channel portion (78) (FIG. 16B). In this etching process, the SiO2 film (83) provided on the source (76) and drain (77) regions prevents excessive scraping of the drain (77) region. After that, a thin SiO2 film (87) is deposited, and then polycrystalline silicon in the carrier confinement region (79) is deposited and etching is performed. After that, a SiO2 film (81) is deposited and then an n-type polycrystalline silicon film is deposited, and the gate electrode (80) is formed by etching using a photoresist as a mask.

Embodiment 2 FIG. 15 is a structural diagram of a storage element according to another embodiment of the present invention. The source (1) and the drain (2) are regions made of high-impurity-concentration n-type polycrystalline silicon, with SiO 2 between them.
2 There is an insulating film (7). The SiO2 insulating film (7) has a side surface with a thickness of 10 nm and a width of 20 n made of non-doped polycrystalline silicon.
A channel portion (3) of m is formed, and a carrier confinement region (4) composed of a plurality of silicon crystal grains having an average diameter of 6 nm is formed across a thin insulating film. The channel part (3) and the carrier confinement region (4) are SiO2 insulating film.
It is connected to the gate electrode (4) via (6). The distance between the gate electrode and the carrier confinement region (4) is 30 nm. The element is provided on the SiO2 insulating film (8). The point that the element is provided on the insulating film is the same in the following examples unless otherwise specified. In this example, the channel
(3) and the carrier confinement region (4) were formed separately,
There is also a method of integrally forming, and this method may be adopted. This also applies to the following examples. Further, the SiO2 film (18) processed to have the same width as the source (1) and the drain (2) above the drain (2) is the SiO2 film described in the first embodiment.
As with (83), prevents excessive scraping of the drain (2).

Regarding the operation of the memory element of this embodiment, the part different from that of the first embodiment will be described. In this embodiment, when the carriers are trapped in the carrier confinement region (4), the channel (3) is thin, so that the capacitance between the gate electrode (5) and the channel (3) becomes small, and the influence of small charge accumulation can be read. I can put it out. In the present example, three electron stores can be read as a threshold voltage shift of about 1V. However, the desired threshold voltage shift may be realized by increasing the channel width and increasing the number of silicon crystal grains in the carrier confinement region to increase the number of accumulated electrons. If the channel width is increased, a large current can be passed, and the lithography process is easy. The size of the carrier confinement region is 10 nm
The total capacitance with the surroundings is 3 aF or less. Therefore, assuming room temperature and taking thermal disturbances into consideration, the stable number of carriers in the carrier confinement region is determined in units of one. For this reason, phenomena such as excessive carriers entering and accumulated carriers falling out are less likely to occur. Erasing is performed by swinging the gate voltage in the opposite direction.

Embodiment 3 FIG. 2 shows a third embodiment of the present invention. In this embodiment, the channel portion and the carrier confinement region (11) are integrally formed, and the channel portion (11) is provided on both sides of the source (9) and the drain (10). Two
Different from The material of the channel portion and the carrier confinement region (11) is a non-doped polycrystalline silicon thin film, and the average thickness is about 3 nm. In this embodiment, the fact that the channel and the carrier confinement region are naturally formed in the thin film (11) is utilized by utilizing the fact that the potential of the polycrystalline silicon thin film having an average thickness of 5 nm or less is highly undulated. However, there is an advantage that a small structure suitable for room temperature operation can be effectively realized by a simple manufacturing process. In this embodiment, since the crystal grain size is about 3 nm in thickness, it is 10 nm in the lateral direction.
The size of each carrier confinement region is also about this. By providing the channel part and the carrier confinement region (11) on both sides of the source (9) and the drain (10) and controlling them by the same gate electrode (12), the channel width is effectively doubled, It has the feature that it can take a large current. When the channel line width is increased and the current value is increased, the area generally increases, but in this structure, the area does not increase. In particular, in the structure in which the channel portion and the carrier confinement region are integrally provided, there is a problem that a simple increase of the channel line width tends to reduce the threshold voltage fluctuation due to carrier capture, but they are separated from each other like this structure. This problem does not occur when multiple channels are prepared.

Example 4 FIG. 3 shows a fourth embodiment of the present invention.

It has two drain regions and a drain 1 (1
3), the source (14) and the drain 2 (15) have a three-layer structure, which is different from the third embodiment. In the structure of this embodiment,
A storage capacity twice as large as that of the structure of the first embodiment can be realized without increasing the area. In addition to using the source (14) in common, the source (14), the drain 1 (13) and the channel portion and carrier confinement region (16) connecting the source (14), the source (14) and the drain 2 (15) Memory is also stored in the channel part and the carrier confinement region (88) that connect them. The two channel portions and the carrier confinement regions (16) (88) are deposited and formed at the same time, and their roles differ only in the positional relationship with the source and drain. Although these have the same gate electrode (17), only one of them can be written and erased by changing the voltage of the drain 1 (13) and the drain 2 (15).
Also, the source (14), drain 1 (13), drain 2 (1
Since 5) can be processed in a batch, and the channel part and the carrier confinement regions (16) (88) can be processed in a batch, there is an advantage that the number of steps can be reduced.
Although the channel portion and the carrier confinement region are integrally formed in this embodiment, they may be separately formed.

Example 5 FIG. 4 shows a fifth embodiment of the present invention.

The present embodiment is different from Embodiments 1 to 4 in which the source and drain have a laminated structure, and is characterized in that the gate electrode has a laminated structure. An SiO2 insulating film is formed on the outside of the laminated gate electrode 1 (19) and gate electrode 2 (20).
A source (21) and a drain (22) regions are provided to separate the source (21) and the drain (2) on the side surface of the SiO2 insulating film (26).
A non-doped polycrystalline silicon thin film (23) having a thickness of about 3 nm is provided in a shape that connects 2). The thin film (23) functions as a channel part and a carrier confinement region. The polycrystalline silicon thin film (23) is very thin and has crystal grains in an island shape, and has a high threshold voltage. Therefore, when the gate voltage is applied, only the thin film portion beside the gate electrode exhibits conductivity, and
(19) The thin film portion (24) on the side surface and the thin film portion (25) on the side surface of the gate electrode 2 (20) become independent channel portions and carrier confinement regions, respectively, even though they are not separated by etching. Therefore, this device can store more than 2 bits. Although only two gate electrodes are stacked in this embodiment, more gate electrodes may be stacked. In the structure in which the source and the drain are stacked as in the third embodiment, it is usually difficult to share the drain in common, so a structure in which four or more layers of the source and the drain are stacked and formed collectively Although difficult to take, this structure has an advantage that the storage capacity can be increased by the number of stacked gate electrodes.

Example 6 FIG. 5 shows a sixth embodiment of the present invention.

The present embodiment is a storage element for storing information of 2 bits or more. The device structure and operation of this embodiment are basically the same as those of the case where two devices of the third embodiment are formed.
Only the manufacturing method that realizes this structure is different.

The manufacturing process of this embodiment will be described. After oxidizing the surface of the P-type substrate, an n-type polycrystalline silicon film, a SiO2 film,
The n-type polycrystalline silicon film is deposited in this order, and the source (27) and drain are formed by etching using the photoresist as a mask.
(28) and SiO2 (31) between them are formed. Next, a thin Si3N4 film of 15 nm is deposited, and a SiO2 film (32) is further deposited. After that, the SiO2 film and the Si3N4 film are etched by using a photoresist having a hole pattern having a step portion at the end of the drain (27) region as a mask (FIG. 5A). At this time, the side surface (30) of the Si3N4 film appears. Next this Si
3 nm of a-Si is deposited on the surface (30) of the 3N4 film. At this time, when the underlayer is SiO2, the time from when the gas source starts flowing until when Si actually reaches the wafer surface is longer than when the underlayer is Si3N4.
2 a-Si is hardly deposited on the film surface. Therefore
Source (27) and drain (28) on the Si3N4 film surface (30)
An a-Si thin wire having a width of about 15 nm is formed in a shape connecting the two. The a-Si is crystallized by heat treatment to integrally form the channel part and the carrier confinement region. SiO2 film
After depositing (33), an n-type polycrystalline silicon film is deposited and etched using the photoresist as a mask to obtain the gate electrode 1.
(29), the gate electrode 2 (34) is formed (FIG. 5 (b)).

In this embodiment, two gate electrodes (29) (34)
Can store each separately, and can store at least 2 bits. If multi-valued storage is performed, a larger number of bits can be stored. The present embodiment is characterized in that fine lines can be formed with good controllability. Variations between elements can be reduced, and a large threshold voltage shift can be achieved with a small number of stored electrons. In this embodiment, a hole is formed so as to include one stepped portion at the end of the drain (28) region, but a hole is formed on both sides, two channel portions and carrier confinement regions are provided, and control is performed by the same gate electrode. May be This structure has a feature that a large channel current can be obtained. further,
Although only the two layers of the source (27) and the drain (28) are stacked in this embodiment, a three-layer structure of the drain 1, the source and the drain 2 may be adopted as in the embodiment 4, and higher density storage is possible. Becomes

Example 7 FIG. 6 shows a seventh embodiment of the present invention.

The present embodiment is carried out only in two points that the channel portion and the carrier confinement region are separately provided, and that the two channel portions formed in the same hole pattern are controlled by the same gate electrode (35). Different from Example 6. The advantage of providing the channel portion and the carrier confinement region separately is that in the first embodiment.
Is the same as. Further, by adopting a structure in which two channel portions formed in the same hole pattern are controlled by one gate electrode (35), the gate electrode (35) can be easily processed. The manufacturing process is different from that of the sixth embodiment in that a thin SiO2 film is deposited immediately after channel deposition to form silicon crystal grains in the carrier confining region.

Example 8 FIG. 7 shows an eighth embodiment of the present invention.

This embodiment differs from the seventh embodiment in the manufacturing process and the positional relationship between the channel portion and the carrier confinement region. Differences in manufacturing process from Example 6 will be described. After forming the source (36) and drain (37) regions, deposit a thin Si3N4 film (38) of 15 nm, then deposit a SiO2 film (40) of 5 nm, and
The difference is that the i3N4 film (39) is deposited to a thickness of 10 nm. After this S
An iO2 film (41) is deposited, and SiO2 is formed using a hole pattern photoresist having a shape including a step portion at the end of the drain (37) region as a mask.
After the step of etching the film and the Si3N4 film, the steps are the same as those in the sixth embodiment. The deposited film thickness of a-Si is 5 nm. In this structure, in the step of depositing a-Si,
On the side of the Si3N4 film (38), next to the channel portion which can be formed by connecting the source (36) and the drain (37), the other Si3N4 film (3
9) Carrier confinement region is formed on the side surface. This structure is characterized by good controllability of the distance between the channel and the carrier confinement region.

Example 9 FIG. 8 shows a ninth embodiment of the present invention.

Four storage elements of the first embodiment are arranged in a matrix,
Two elements share the source and drain, and two elements share the gate electrode. Two drains (42) (43) as data lines, two gates (46)
Rows and columns can be controlled by using (47) as a word line. Increase the number of elements sharing the source and drain,
In other words, the number of elements controlled by the same data line may be increased. Also, the number of elements sharing the gate electrode may be increased, in other words, the number of elements controlled by the same word line may be increased. The same applies to the other examples. In addition, in order to reduce the resistance of the data line, a metal material (for example, Al, W, TiN, WSi2, MoSi, TiSi) is used.
And so on), and this method may be adopted. The word lines may also be lined with a metal material to reduce resistance. This also applies to the other embodiments.

Example 10 FIG. 9 shows a tenth embodiment of the present invention.

Four storage elements of the fourth embodiment are arranged in a matrix,
The source, the drain 1, and the drain 2 are shared by two elements, and the gate electrode is shared by two elements. The shared polysilicon of drain and gate can be used as it is as a data line and a word line. In this embodiment, a total of four data lines 1 to 4 (48) to (5
Controlled by 1) and word lines 1 (54), 2 (55), it is possible to store information of 8 bits or more. Here, the data lines 1 to 4 and (48) to (51) in the drawing correspond to the ascending order of the numbers, and will be described below in this sense. In this embodiment, the lowermost layer of n-type polycrystalline silicon stacked in three layers is the data line 1 (48), 3 (50), and the upper layer is the source line 1 (52),
2 (53), and the uppermost layer is the data lines 2 (49), 4 (51).

In this embodiment, the contact portion is also shown. The contact process will be described.
First, an n-type polycrystalline silicon film for forming the data lines 1 (48), 3 (50), a SiO2 film, and an n-type polycrystalline silicon film for forming the source lines 1 (52), 2 (53) are deposited respectively. To do. Here, the n-type polycrystalline silicon film for forming the source lines 1 (52), 2 (53) is pierced by the first hole pattern (56).
Next, the SiO2 film and n for forming the data lines 2 (49) and 4 (51) are formed.
After depositing the polycrystalline silicon film, the second hole pattern (5
The polycrystalline silicon for forming the data lines 2 (49) and 4 (51) is also removed by 7). After that, when a data line and a source line are collectively formed after depositing a SiO2 film, the contact patterns are connected to each other in the contact portion ((58), (59),
(60) combined pattern). As a result, in (60), the data line 2 is the uppermost polycrystal silicon, but in (59), the polycrystal silicon of the data line 2 is not removed and the polycrystal silicon of the source line is the highest. It is the upper layer. Further, in (58), both the polycrystalline silicon of the data line 2 and the polycrystalline silicon of the source line are lost, and the polycrystalline silicon of the data line 1 is the uppermost layer. Therefore, it is not necessary to prepare separate steps for forming contact holes in the above layers. This contact process is effective for other laminated structures, and may be used for a laminated structure of gate electrodes as in the fifth embodiment, for example. Of course, a contact process other than this method may be used,
This also applies to other embodiments.

Example 11 10 to 12 and 17 show an eleventh embodiment of the present invention.

Eight memory elements of Example 4 are arranged in a matrix of 4 × 2, and the source, the drain 1, and the drain 2 are shared by four elements, and the gate electrode is formed by two elements. It is shared. As in the tenth embodiment, the shared drain and gate polycrystalline silicon can be used as it is as a data line and a word line. The three layers of polycrystalline silicon that are collectively etched are stacked in the order of the data line 1, the source line, and the data line 2 from the lower layer. In this embodiment, the selection transistor portion of the data line is also shown. The cell part is a part (61) surrounded by a dotted line.
In this embodiment, it is controlled by four data lines (62), four select transistor gates (63), and a word line (64),
Information of 16 bits or more can be stored. As the memory cell becomes smaller, it is necessary to reduce the area of the contact and the peripheral circuit portion. Especially as in the present invention,
When the gate, drain, or gate has a laminated structure, it may be impossible to perform the layout if the contact or the peripheral circuit portion is large.

The structure will be described together with the manufacturing process. First, select transistors are formed on a silicon substrate (see FIG. 10).
(a)). (66), (67) and (68) in the figure are diffusion layers. At the same time, other peripheral circuits are formed, but here, only transistors for selecting data lines are shown. After forming the gate electrode (63) of the select transistor, an oxide film is deposited to form a field oxide film.
A memory cell is formed on (69). The method of forming the cell portion is almost the same as that of the fourth embodiment, and different portions will be described below. Before depositing the n-type polycrystalline silicon film of the lower data line 1, the oxide film is etched using a photoresist as a mask to expose a part of the diffusion layer (66) of the select transistor (70) (FIG. 10 (b)). . After depositing the n-type polycrystalline silicon film of the lower data line 1 and before depositing the n-type polycrystalline silicon film of the source line, the polycrystalline silicon of the data line 1 is etched with a photoresist as a mask (71) (FIG. 11). (a)). Further SiO2
Film, source line n-type polycrystalline silicon film, SiO2 film, data line 2 n-type polycrystalline silicon film, and before patterning data and source lines collectively, pattern of holes (72)
Then, the polycrystalline silicon film of the data line 2 is etched. Therefore, when batch etching data and source lines,
There is no polycrystalline silicon on the data line 1 outside the pattern shown by (71), and there is no polycrystalline silicon on the data line 2 in the pattern part shown by (72). By performing the above steps, after the data and source lines are collectively etched (FIG. 11 (b)), the data line 1 is directly connected to the diffusion layer (66) of the select transistor without interposing a metal. There is no need to perform a separate process, the process is simple and at the same time the area is small. Further, the common source lines are connected to each other by polycrystalline silicon, and the polycrystalline silicon of the upper data line 2 is removed at a part (65) thereof. Therefore, contacts and wirings may be made only in this portion, and the area can be small. Oxide film deposition,
After polycrystal silicon deposition and word line processing, oxide film deposition and flattening steps are performed to form contact holes, and then metal wiring (75) in the first layer is formed as shown in FIG. 12 (a). As a result, the data line 2 (73) and the diffusion layer (68) of the selection transistor
Are connected. FIG. 17 is a sectional view taken along the line AB in FIG.
Shown in. However, in FIG. 12, metal wiring for the gate (63) of the selection transistor and the word line (64) is omitted to avoid complexity of the drawing. Further, a contact hole is opened to the diffusion layer (67) of the selection transistor, and the second layer metal wiring (62) is formed as shown in the figure. As a result, by selecting the voltage applied to the gate electrodes of the two selection transistors, the metal data line 62 is electrically connected to only one of the data line 1 and the data line 2.

In this embodiment, a small-scale memory is used to simplify the structure, but the number of data lines and word lines is larger when a memory device is actually realized. For example, 1000 stacked data lines, 1000 source lines, and 16 word lines.
Storage elements are arranged in a matrix having a book, and a select transistor is provided in each data line as in this embodiment. This structure is called a block for convenience. A storage device is realized by repeatedly arranging a plurality of blocks in a direction perpendicular to the word lines. The set of stacked data lines 1 and 2 can be controlled by a single data line outside the block using a select transistor.
The metal data lines of multiple blocks are connected together. As a result, it suffices if there are as many metal data lines as there are data lines in one block. In such a structure in which the blocks are divided and arranged, the data line portion of the polycrystalline silicon is short, and the resistance does not increase.

Example 12 FIG. 13 shows a twelfth embodiment of the present invention.

This embodiment is different from the fifth embodiment only in that the source line 74 is not made of polycrystalline silicon but the diffusion layer of the substrate is used. The source line may be common to each cell and uses the substrate surface. The present embodiment is characterized in that the resistance of the source line (74) is small and the process can be shortened because the amount of polycrystalline silicon can be further reduced. Such a structure in which the source line serves as the diffusion layer of the substrate can also be used in the element of the first embodiment.

Example 13 FIG. 14 shows a thirteenth embodiment of the present invention.

In this embodiment, the memory elements of the first embodiment are arranged,
It is a structure that is further stacked in two layers. FIG. 14 shows a cross-sectional view taken along the data line. Since the memory element and the memory device of the present invention can be formed over the insulating film, they can be stacked unlike the memory element formed over the surface of the substrate. It has the feature that a higher degree of integration can be achieved by adopting a stacked structure. Further, in the case where such a stacked structure is adopted, the channel of the memory element and the memory device of the present invention runs vertically, so that the gate electrode of the upper or lower cell is more affected than the planar structure. It has the characteristic of being difficult.

[0043]

According to the present invention, it is possible to provide a semiconductor memory device and a semiconductor memory device which have a small area and are suitable for high integration.

[Brief description of drawings]

FIG. 1 is a structural diagram of a semiconductor device according to a first embodiment of the present invention. (a) is a bird's-eye view and (b) is a sectional view.

FIG. 2 is a structural diagram of a semiconductor device of Example 3 of the present invention. (a) is a bird's-eye view and (b) is a sectional view.

FIG. 3 is a structural diagram of a semiconductor device of Example 4 of the present invention. (a) is a bird's-eye view and (b) is a sectional view.

FIG. 4 is a structural diagram of a semiconductor device of Example 5 of the present invention. (a) is a bird's-eye view, (b) is a sectional view in a section including a channel portion, and (c) is a sectional view in a section including a source.

FIG. 5 is a structural diagram of a semiconductor device of Example 6 of the present invention. (a) is a bird's-eye view when the channel is formed, and (b) is a bird's-eye view after the gate is formed.

FIG. 6 is a structural diagram of a semiconductor device of Example 7 of the present invention.

FIG. 7 is a structural diagram of a semiconductor device of Example 8 of the present invention. (a) is a bird's-eye view when the channel is formed, and (b) is a bird's-eye view after the gate is formed.

FIG. 8 is a diagram showing a semiconductor device of Example 9 of the present invention. (a) is a bird's eye view and (b) is a top view.

FIG. 9 is a diagram showing a semiconductor device according to a tenth embodiment of the present invention. (a) is a bird's eye view and (b) is a top view.

FIG. 10 is a top view showing a manufacturing process of a semiconductor device according to an embodiment 11 of the present invention.

FIG. 11 is a top view showing the manufacturing process of the semiconductor device according to example 11 of the present invention.

FIG. 12 is a top view showing a semiconductor device and a manufacturing process thereof according to an eleventh embodiment of the present invention.

FIG. 13 is a structural diagram of a semiconductor device according to Example 12 of the present invention.

FIG. 14 is a diagram showing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 15 is a diagram showing a semiconductor device according to a second embodiment of the present invention. (a) is a bird's-eye view and (b) is a sectional view.

FIG. 16 is a bird's-eye view showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a sectional view showing the structure of a contact portion of a semiconductor device according to Example 11 of the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-153955 (JP, A) JP-A-3-84964 (JP, A) JP-A-3-6856 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 29/788

Claims (11)

(57) [Claims] 1. A first conductive region and a second conductive region,
The second conductive region is provided above or below the first conductive region via a first insulating film, and the first conductive region is a first conductive region .
Connected to the second conductive region through a 1- channel region,
The first channel region is connected to the gate electrode via a gate insulating film, and is connected to the gate electrode and the first channel region.
A first channel region near the first channel region so as to be sandwiched between the regions .
A semiconductor memory device having one carrier confinement region, wherein storage is performed by changing the threshold voltage of the semiconductor device by retaining carriers in the first carrier confinement region. 2. The semiconductor device according to claim 1, wherein the carrier confinement region is made of semiconductor or metal fine particles. 3. The semiconductor device according to claim 1, wherein the distance between the gate electrode and the uppermost insulating film of the first conductive region or the second conductive region is equal to that of the first conductive region or the second conductive region. A semiconductor device characterized in that the distance is larger than the distance between the carrier confining region on the side wall of the conductive region and the gate electrode. 4. The semiconductor element according to claim 1, further comprising a third conductive region through the second insulating film, and the second conductive region.
Formed between the second conductive region and the third conductive region.
Forming a second channel region and in front of the second channel region
The second carrier is confined so that it is sandwiched between the gate electrodes.
A semiconductor memory device characterized by forming a region . 5. A first conductive region, a second conductive region, and a third conductive region, wherein the first conductive region, the second conductive region, and the third conductive region are each a first conductive region through an insulating film. , A second conductive region, and a third conductive region are provided one above the other in this order, and the second conductive region is provided with the first conductive region via a channel region,
The channel region is connected to the third conductive region, the channel region is connected to a gate electrode via a gate insulating film, and the gate region is connected to the gate electrode.
Electrode and having a carrier confinement region in the channel region near so as to be interposed between the channel area, the gate
The width of the electrode, carrier confinement area, and channel area is
Smaller than the first conductive region, the second conductive region, and the third conductive region
A semiconductor memory device characterized in that storage is performed by holding a carrier in the carrier confinement region with a narrow width to change a threshold voltage of the semiconductor device. 6. A plurality of semiconductor elements according to claim 5 are arranged, and the gate electrodes of the semiconductor elements are connected to each other,
The first conductive region and the third conductive region of the semiconductor element are respectively connected to the same data line via a selection transistor, and the plurality of semiconductor elements are controlled by the data line and the gate electrode. Semiconductor memory device. 7. A plurality of gate electrodes having a first conductive region and a second conductive region, which are provided above and below each other with a first insulating film interposed therebetween, and with the second insulating film interposed therebetween. A channel region of the semiconductor thin film is provided on a side surface of the gate electrode, the first conductive region is connected to the second conductive region through the channel region, and semiconductor or metal fine particles are formed in the vicinity of the channel region. A semiconductor memory device having the following carrier confinement region, and storing by changing the threshold voltage of the semiconductor device by holding the carrier in the carrier confinement region. 8. A semiconductor memory device having a gate electrode, a first conductive region, a second conductive region, a channel region and a carrier confining region on a substrate, wherein the first conductive region and the second conductive region are located between them. Is laminated in a direction perpendicular to the main plane of the substrate with an insulating film interposed therebetween, and the channel region is
The carrier confinement region is formed so as to connect between the stacked first conductive region and second conductive region, and the carrier confinement region is provided between the gate electrode and the channel region and is formed in the channel region. that channels are formed in the direction substantially perpendicular to the main plane of the substrate, the gate
The width of the electrode, carrier confinement area, and channel area is
Serial first conductive region, a semiconductor memory device according to claim small width der Rukoto than the second conductive region. 9. A semiconductor memory device having a gate electrode, a first conductive region, a second conductive region, a third conductive region, a channel region and a carrier confinement region on a substrate, wherein the first conductive region, the second conductive region and the second conductive region are provided. The third conductive region sandwiches a first insulating film between the first conductive region and the second conductive region,
And a second gap between the first conductive region and the third conductive region.
Is laminated in a direction perpendicular to the main plane of the substrate with the insulating film sandwiched therebetween, and the channel region is formed so as to connect the laminated first conductive region to the second and third conductive regions. is, the carrier confinement region is provided between the gate electrode and the channel region, the gate
The width of the electrode / carrier confinement area / channel area is as described above.
Smaller than the first conductive region, the second conductive region, and the third conductive region
The semiconductor memory device is characterized in that the channel formed in the channel region with a certain width is formed in a direction substantially perpendicular to the main plane of the substrate. 10. The method according to claim 5, 8, or 9.
In the semiconductor device of, the carrier confinement region is half
A semiconductor characterized by being formed of fine particles of a conductor or metal
Storage element. 11. The method according to any one of claims 1 to 10.
In a semiconductor device, the channel region has a thickness of 20 nm or less
A semiconductor memory device having a thickness of.