JP2817234B2 - Thin film transistor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor memory.

[Conventional technology]

Recently, E ² PROM that can be electrically written / erased / read
For example, a thin film transistor memory in which a memory element is formed of a thin film transistor has been considered as a memory.

FIG. 9 is a circuit diagram of a conventional thin film transistor memory, in which T1 is a thin film transistor for memory (hereinafter referred to as a memory transistor), and T2 is a thin film transistor for selection (hereinafter referred to as a selective transistor) provided in series with each memory transistor T1. Transistor). The source electrode S of the select transistor T2 is connected to the drain electrode D of the memory transistor T1 forming a pair with the source electrode S. One memory element M is formed by each of the pair of memory transistors T1 and select transistor T2 connected to each other. Have been. GL1 and GL2 denote two pairs of gate lines (address lines), SL and DL denote source and drain lines (data lines), and gate lines GL1 and GL2.
The GL2 and the source and drain lines SL and DL are arranged in a matrix at right angles to each other. The memory element M is disposed at each intersection of the gate lines GL1 and GL2 and the source and drain lines SL and DL. The gate electrode G of the memory transistor T1 is connected to the gate electrode GL1 of the pair of gate lines GL1 and GL2. Connected to the first gate line GL1,
The gate electrode G of the selection transistor T2 is connected to the second gate line GL2. The source electrode S of the memory transistor T1 is connected to the source line SL, and the drain electrode D of the select transistor T2 is connected to the drain line DL.

Writing, erasing, and reading of this thin film transistor memory are performed as follows.

In FIG. 9, (a) shows a voltage applied state at the time of writing, (b) shows an erased state, and (c) shows a voltage applied state at the time of reading. Note that (a), (b), and (c) all show the state when one memory element M at the upper left in the figure is selected.

First, the writing will be described, upon writing, as shown in FIG. 9 (a), 1/2 of the write and erase voltage V _P of the first and second gate lines GL1, respectively GL2 memory transistor T1 for selecting The corresponding positive voltage + 1 / 2V _P and the ON voltage V _ON (for example, + 10V) of the selection transistor T2 are applied, and the selected source and drain lines SL and DL respectively correspond to 1/2 of the above-mentioned write / erase voltage V _P Negative voltage −1 / 2V _P
Is applied, the potential of the unselected first gate line GL1 and the source and drain lines SL and DL is 0 (ground), and the potential of the unselected second gate line GL2 is V _OFF (for example, 0 V). Note that the write / erase voltage V _P of the memory transistor T1 is
Is 40V, for example, + 1 / 2V _P is + 20V and -1 / 2V _P is-
20V. When such a voltage signal is applied, the selected gate lines GL1 and GL2 and the source and drain lines SL and
Selection transistors T2 of the memory device (hereinafter referred to as the selected memory element) M is turned on at the intersection of the DL, the gate and source of the memory transistor T1, a potential difference corresponding to the write erase voltage V _P between the drain (+ 1 / 2V _P and -1 / potential difference between 2V _P) is generated, the memory transistor T1 is written state. In addition, in other memory elements (hereinafter, referred to as unselected memory elements) M on the selected gate lines GL1 and GL2,
The gate and source of the memory transistor T1, and the potential difference generated between the drain only 1 / 2V _P, thus the memory transistor T1 is in the write inhibiting state. Regarding the memory elements on the gate lines GL1 and GL2 that are not selected, the memory element at the lower left in the figure has a potential difference between the gate and the source and drain of the memory transistor T1 similar to the unselected memory element M. is only 1 / 2V _P, thus the memory transistor T1 is in the write inhibiting state. Further, as for the memory element at the lower right in the figure, the potential generated between the gate and the source and drain of the memory transistor T1 is 0 (no voltage is applied), as in the case of the non-selected memory element M. That is, the potential is equal between the gate and the source and drain, and therefore, the memory transistor T1 is also in the write-protected state.

At the time of erasing, as shown in FIG. 9 (b), the selected first and second gate lines GL1 and GL2 are supplied with -1 / 2V _P and V, respectively.
Applies a _ON, the applied source, drain line SL, the respective DL + 1 / 2V _P to select. Note that unselected gate lines GL1, GL2 and source / drain lines SL,
The signal applied to the DL is the same as that at the time of writing. The application of such a voltage signal, and a potential difference occurs in the reverse potential corresponding to the write erase voltage V _P between the gate and the source, the drain of the memory transistor T1 of the selected memory device M, is held in the memory transistor T1 Data is erased. Again, the potential difference generated between the gate and the source, the drain of the memory transistor T1 of the non-selected memory device M is only 1 / 2V _P, the memory transistor T1 is in the erasing blocking state.

On the other hand, at the time of reading, as shown in FIG. 9 (c), the first and second gate lines GL1 and GL2 to be selected have V _SEL ,
While applying V _ON , V _D is applied to the drain line DL of the selected source and drain lines SL and DL, and the potential of the source line SL is set to 0. Note that V _SEL and V _D are
The voltage is sufficiently lower than the write / erase voltage V _P (40 V) of the memory transistor T1, for example, V _SEL = 0V and V _D = 10V. Also, during this read operation, the unselected gate lines GL1,
The signals applied to GL2 and the source and drain lines SL and DL are the same as those at the time of writing and erasing. When such a voltage signal is applied, a current flows from the drain line SL to the source line SL according to the data held in the memory transistor T1 of the selected memory element M, and this is output as read data.

In addition, in any of the above-described writing, erasing, and reading, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. However, the gate potential of the selection transistor T2 of the unselected memory element M is V _OFF.
Is in the off state because of the
Are not affected by the applied voltage. That is, the selection transistor T2 functions not only to select the memory transistor T1, but also to function as a guard transistor that guards the memory transistor T1 from a voltage applied when the memory transistor T1 is not selected.

[Problems to be solved by the invention]

However, the above-described conventional thin film transistor memory has only one selection transistor T2 provided for the memory transistor T1, and therefore, if the selection transistor T20 has a characteristic defect, the selection transistor T2 is not provided.
Since it becomes impossible to select and guard the memory transistor T10 selected by 20,
It had the problem of low reliability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor memory having significantly improved reliability.

[Means for solving the problem]

In order to achieve the above object, the thin film transistor memory of the present invention has a thin film transistor for selection provided in series on both sides of the thin film transistor for memory.

[Action]

In the thin film transistor memory of the present invention, the thin film transistor for selection is provided in series on both sides of the thin film transistor for memory. Therefore, even if the characteristics of one thin film transistor for selection are defective, the thin film transistor for another memory is selected by another thin film transistor for selection. Can be selected and guarded, so that the reliability can be greatly improved.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 to 6 show a first embodiment of the present invention.

First, the basic configuration of the thin-film transistor memory of this embodiment will be described. FIG. 1 is a circuit diagram of the thin-film transistor memory, where T10 is a memory thin-film transistor (hereinafter referred to as a memory transistor), and T20a and T20b are each a memory transistor T10. A pair of two thin film transistors for selection (hereinafter, referred to as selection transistors) provided in correspondence with each other. This pair of select transistors T20a, 20b
Are provided on both sides of the memory transistor T10. Then, the pair of selection transistors T20
a and T20b, one of the selection transistors T20a has its source electrode S integrated with the drain electrode D of the memory transistor T10 to form a memory transistor T10a.
The other select transistor T20b is connected in series to the memory transistor T10 by making its drain electrode D an electrode integral with the source electrode S of the memory transistor T10. , T20b and the memory transistor T10 therebetween constitute one memory element M. Also, GL
Is a gate line (address line), SL and DL are source and drain lines (data lines), and the gate line GL and the source and drain lines SL and DL are arranged in a matrix at right angles to each other. The memory element M is disposed at the intersection of the gate line GL and the source and drain lines SL and DL, respectively, and includes the memory transistor T10 and both select transistors T20a,
The gate electrode G of T20b is connected to a common gate line GL. The drain electrode D of one select transistor T20a of the memory element M is connected to the drain line DL, and the source electrode S of the other select transistor T20b is connected to the source line SL.

Writing, erasing and reading of the thin film transistor memory are performed as follows.

In FIG. 1, (a) shows a voltage application state at the time of writing, (b) shows an erasing time, and (c) shows a voltage applying state at the time of reading. Note that (a), (b), and (c) all show the state when one memory element M at the upper left in the figure is selected.

First, writing will be described. At the time of writing, as shown in FIG. 1 (a), the selected gate line GL is applied with 1/1/40 of the write / erase voltage V _P (for example, 40 V) of the memory transistor T10.
Applies a positive voltage corresponding to _{2 + 1 / 2V P (+} 20V), the negative voltage -1 / 2V which corresponds to 1/2 of the source to be selected, the drain line SL, respectively the write erase voltage V _P to the DL
_P (−20 V) is applied, and the potentials of the unselected gate line GL and the source / drain lines SL and DL are set to 0. When such a voltage signal is applied, the selection transistors T20a and T20b of the selected memory element M at the intersection of the selected gate line GL and the source and drain lines SL and DL are turned on by applying a voltage to the gate electrode G. , the gate electrode G and the source of the memory transistor T10, the drain electrode S, and a potential difference occurs corresponding to the write erase voltage V _P between as D, the memory transistor T10 becomes written state. In the other unselected memory elements M on the selected gate line GL, the gate electrode G and the source / drain electrodes S, D of the memory transistor T10 and the select transistors T20a, T20b are provided.
Is only 1/2 V _P , and therefore, the memory transistor T10 is in a write-protected state. Also,
For the memory element on the gate line GL that is not selected,
The memory element at the lower left in the figure is the gate and source of the memory transistor T10, like the unselected memory element M.
The potential difference generated between the drain and the drain is only 1/2 V _P , and therefore, the memory transistor T10 is in a write-protected state. Further, as for the memory element at the lower right in the figure, similarly to the non-selected memory element M, the potential generated between the gate and the source and drain of the memory transistor T10 is 0 (no voltage is applied). That is, the potential is equal between the gate and the source / drain, so that the memory transistor T10 is also in the write-protected state.

The erasing, as shown in Fig. 1 (b), is applied to apply a -1 / 2V _P to the gate lines GL for selecting the source for selecting, drain line SL, respectively + 1 / 2V _P to DL . Note that unselected gate lines GL and sources,
The signals applied to the drain lines SL and DL are the same as those at the time of writing. The application of such a voltage signal, the gate electrode G and the source of the memory transistor T10 of the selected memory device M, the drain electrode S, a potential difference of opposite potential corresponding to the write erase voltage V _P between the D occurs. At this time, both sides of the select transistors T20a of the memory transistor T10, the gate electrode Ga and the source of T20b, the drain electrode S, between D are likewise the voltage of -V _P is applied to the memory transistor T10. Normally, a thin film transistor using amorphous silicon, polysilicon or the like as a semiconductor layer is electrically connected between the source and the drain even when a high negative voltage is applied to the gate electrode, and the thin film transistor is turned on. Therefore, the selection transistor T2
0a, T20b is turned ON by the high negative voltage -V _P, data held in the memory transistor T10 are erased. Also in this case, the memory transistor T1 of the unselected memory element M
0 gate electrode G and the source of potential difference generated between the drain electrode S, D is only 1 / 2V _P, the memory transistor T1 is in the erasing blocking state.

On the other hand, at the time of reading, as shown in FIG. 1 (c), V _ON is applied to the selected gate line GL, and the drain line D of the selected source and drain lines SL and DL is selected.
The V _D is applied to the L, and the potential of the source line SL is set to 0. Note that the V _ON and V _D is sufficiently smaller voltage than the write erase voltage V _P of the memory transistor T10 (40V), for example, V _ON
= 10V, V _D = 10V. In addition, unselected gate line GL
_VOFF (0 V) is applied to the source, and the potentials of the unselected source and drain lines SL and DL are set to 0. When such a voltage signal is applied, the memory transistor T10 of the selected memory element M
Current flows from the drain line DL to the source line SL in accordance with the data held in the memory cell, and is output as read data.

In addition, in any of the above-described writing, erasing, and reading, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. but is the selection transistor T20a of the non-selected memory device M, T20b, since in the off state because its gate potential is a negative voltage -1 / 2V _P or V _oFF (0V), the unselected memory device M Of the memory transistor T10 is not affected by the applied voltage. That is, also in this thin film transistor memory, the selection transistors T20a and T20b not only select the memory transistor T10 but also function as a guard transistor that guards the memory transistor T10 from a voltage applied when the memory transistor T10 is not selected.

Next, a specific structure of the thin film transistor memory will be described.

2 and 3 are a sectional view and a plan view of one memory element M of the thin film transistor memory. To explain the structure of the memory element M, reference numeral 11 denotes an insulating substrate made of glass or the like, and a gate electrode G shared by the thin film transistors T10, T20a, T20b for memory and selection is provided on the substrate 11. Then, a gate line GL connected to the gate electrode G is formed. On the substrate 11, a first gate insulating film 12 is formed to cover both sides of the gate electrode G except for the center, that is, the gate electrodes of the select transistors T20a and T20b. Is formed with a second gate insulating film 13 covering the entire gate electrode G. The gate insulating films 12 and 13 respectively have a stoichiometric ratio (Si / N =
0.75), and is formed of silicon nitride (SiN) substantially the same as that of the first gate insulating film 12.
The thickness of the second gate insulating film 13 is 3500 mm.
It is a thin film of about 500Å1500Å. In other words, the gate insulating film on the gate electrode G is the first and second select transistors T20a and T20b on both sides of the gate electrode G.
And a second gate insulating film 13 in the central portion of the memory transistor T10.
It is a thin film consisting of only Since the second gate insulating film 13 in the memory transistor T10 has a small thickness, the second gate insulating film 13 has a charge storage function even when the composition ratio Si / N is almost the same as the stoichiometric ratio. Note that the gate insulating films 12 and 13 of the select transistors T20a and T20b do not have a charge storage function because the entire film thickness is large. An i-type semiconductor layer 14 shared by the memory transistor T10 and the select transistors T20a and T20b is formed on the second gate insulating film 13 so as to face the entire area of the gate electrode G. . This i-type semiconductor layer 14 is made of ia-Si (i
Type amorphous silicon). And
On both sides of the i-type semiconductor layer 14, n ⁺ -a-Si (n
A source electrode S and a drain electrode D are formed via an n-type semiconductor layer 15 made of amorphous silicon doped with a type impurity, and the source electrode S10 is connected to a source line SL integrated therewith, The electrode D is connected to a drain line DL integral with the electrode D. Reference numeral 16 denotes a protective insulating film that covers the memory element M.

That is, the thin film transistor memory of this embodiment is:
The memory element M has a configuration in which a memory transistor T10 and two paired select transistors T20a and T20b are formed in one thin film transistor. The memory transistor T10 includes a gate electrode G and a second Gate insulating film 13, i-type semiconductor layer 14 and n-type semiconductor layer 15
And the source and drain electrodes S and D. The selection transistors T20a and T20b are respectively provided with the gate electrode G and
The semiconductor device includes first and second lower gate insulating films 12 and 13, the i-type semiconductor layer 14 and the n-type semiconductor layer 15, and the source and drain electrodes S and D.

FIG. 4 shows a method of manufacturing the above thin film transistor memory. This thin film transistor memory is manufactured by the following steps.

First, a metal film such as chromium is formed on the substrate 11, and the metal film is patterned. As shown in FIG. 4A, the gate electrode G and the gate line GL connected to the gate electrode G are simultaneously formed. Then, a first gate insulating film 12 is deposited on the entire surface of the substrate 11.

Next, as shown in FIG. 4 (b), the substantially central portion of the gate electrode G in the first gate insulating film 12 is removed by etching to expose the gate electrode G in the memory transistor T10.

Thereafter, as shown in FIG. 4 (c), a second gate insulating film 13 is deposited over the entire surface of the substrate 11, and an i-type semiconductor layer 14 made of ia-Si is deposited thereon. When,
An n-type semiconductor layer 15 of n ⁺ -a-Si and a metal film 19 of chromium or the like serving as source and drain electrodes S and D are sequentially deposited.

Next, as shown in FIG.
After patterning the type semiconductor layer 15 to form the source electrode S and the source line SL and the drain electrode D and the drain line DL, and then patterning the i-type semiconductor layer 14 into the shape of the memory element region, After forming the protective insulating film 16, the thin film transistor memory shown in FIGS. 2 and 3 is completed.

FIG. 5 shows a circuit of the memory element M, and FIG. 6 shows an equivalent circuit thereof. The circuit of each memory element M shown in FIG. 1 corresponds to the equivalent circuit of FIG.

Thus, in this thin film transistor memory,
Since each memory element M has a configuration in which the selection transistors T20a and T20b are provided in series on both sides of the memory transistor T10, even if one of the pair of selection transistors T20a and T20b has a defective characteristic, The selection and guard of the memory transistor T10 can be performed by one selection transistor, so that the reliability can be improved.

Further, in the thin film transistor memory of the above embodiment, the gate electrodes G of the memory transistor T10 and the select transistors T20a and T20b are connected to a common gate line GL, and the signal to the gate electrode G of the memory transistor T10 and the select transistors T20a and T20b is connected. Is applied from the common gate line GL, the number of gate lines is half that of the conventional thin film transistor memory, and therefore the area required for the gate line wiring can be reduced by that much. Can be increased without increasing the area. Moreover, in the thin-film transistor memory of the above embodiment, the memory element M has a configuration in which the memory transistor T10 and the select transistors T20a and T20b are formed in one thin-film transistor. Since the size can be reduced, the degree of integration can be further increased.

 Next, another embodiment of the present invention will be described.

7 and 8 show a second embodiment of the present invention. FIG. 7 has a cross section of one memory element M of the thin film transistor memory. In the drawings, those corresponding to the first embodiment shown in FIG. 3 and FIG. 4 are denoted by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 7, the thin film transistor memory of this embodiment has a memory transistor T10 of the memory element M.
Of the gate insulating film, the composition ratio of Si / N to the stoichiometric ratio (Si / N = 0.
75), a non-memory insulating film 17 made of silicon nitride (SiN) having no charge storage function and a composition ratio of Si /
N is set to be larger than the stoichiometric ratio (Si / N = 0.85 to 1.15) to form a two-layer film with the memory insulating film 18 made of silicon nitride having a charge storage function, and select transistors T20a and T20b.
Is a non-memory insulating film 17 alone, and the non-memory insulating film 17 is provided on a gate electrode G shared by the thin film transistors T10, T20a, and T20b for memory and selection. Is formed so as to cover the entire area. Further, the memory insulating film 18 is formed on the non-memory insulating film 17 so as to oppose a portion of the gate electrode G to be a gate electrode of the memory transistor T10 (a central portion of the gate electrode G). . The thickness of the non-memory insulating film 17 is about 2000 、, and the thickness of the memory insulating film 18 is about 100 Å.
It is a very thin film.

The thin-film transistor memory of the second embodiment also has a configuration in which the memory element M has a configuration in which a memory transistor T10 and two select transistors T20a and T20b are formed in one thin-film transistor.
Comprises a gate electrode G, a gate insulating film including a non-memory insulating film 17 and a memory insulating film 18, an i-type semiconductor layer 14 and an n-type semiconductor layer 15, and source and drain electrodes S and D. Then, the select transistors T20a and T20b respectively include the gate electrode Ga, the gate insulating film including the non-memory insulating film 17, the i-type semiconductor layer 14 and the n-type semiconductor layer 15,
And the source and drain electrodes S and D.

FIG. 8 shows a method for manufacturing the above-mentioned thin film transistor memory. This thin film transistor memory is manufactured by the following steps.

First, a metal film such as chromium is formed on the substrate 11, and the metal film is patterned. As shown in FIG. 8A, the gate electrode G and the gate line GL connected to the gate electrode G are simultaneously formed. A non-memory insulating film 17 and a memory insulating film 18 are sequentially deposited over the entire surface of the substrate 11.

Next, as shown in FIG. 8B, portions other than the memory transistor T10 portion of the memory insulating film 18 are removed by etching, and then, as shown in FIG.
An i-type semiconductor layer 14 of ia-Si, an n-type semiconductor layer 15 of n ⁺ -a-Si, and a metal film 19 of chromium or the like serving as source and drain electrodes S and D are formed on the entire surface of the substrate 11. Deposit sequentially.

Next, as shown in FIG. 8D, the metal film 19 and n
After patterning the type semiconductor layer 15 to form a source electrode S and a source line and a drain electrode D and a drain line, the i-type semiconductor layer 14 is patterned into the shape of a memory element region, and then a protective insulating film is formed thereon. 16 are formed to complete the thin film transistor memory shown in FIG.

The circuit of the memory element M of the second embodiment is the same as that of FIG. 5, and its equivalent circuit is as shown in FIG.

Thus, in the thin film transistor memory of the second embodiment, each memory element M has a configuration in which the selection transistors T20a and T20b are provided in series on both sides of the memory transistor T10.
Even if one of the characteristics of T20a or T20b is bad, the memory transistor is selected by another selection transistor.
T10 can be selected and guarded, thus improving reliability.

Also in the second embodiment, since the gate electrodes G of the memory transistor T10 and the select transistors T20a and T20b are connected to a common gate line GL, the number of gate lines is reduced to half that of the conventional thin film transistor memory, and Since the integration degree can be increased without increasing the area of the memory element, and the memory element M has a configuration in which the memory transistor T10 and the two select transistors T20a and T20b are formed in one thin film transistor, It is possible to further increase the degree of integration by reducing the element area of M.

In the first and second embodiments, each memory element M of the thin film transistor memory has a configuration in which the memory transistor T10 and the two select transistors T20a and T20b are formed in one thin film transistor. The memory transistor T10 and the two select transistors T20a and T20b constituting the element M may be separate thin-film transistors. In this case, the gate electrodes G of the memory transistor T10 and the select transistors T20a and T20b are the same as those in the above embodiment. If the common gate line GL is connected, the number of gate lines can be reduced to half that of the conventional thin film transistor memory, and the degree of integration can be increased without increasing the area of the entire memory. However, when the memory transistor T10 and the two select transistors T20a and T20b are formed as separate thin film transistors, the gate electrode of the memory transistor T10 and the gate electrodes of the select transistors T20a and T20b are connected to different gate lines. In such a case, the signal shown in FIG. 9 may be applied to each line to perform writing, erasing, and reading.

〔The invention's effect〕

In the thin film transistor memory of the present invention, the thin film transistor for selection is provided in series on both sides of the thin film transistor for memory. Therefore, even if the characteristics of one thin film transistor for selection are defective, the thin film transistor for another memory is selected by another thin film transistor for selection. Can be selected and guarded, so that the reliability can be greatly improved.

[Brief description of the drawings]

1 to 6 show a first embodiment of the present invention. FIG. 1 is a circuit diagram of a thin film transistor memory, and FIGS. 2 and 3 are cross-sectional views of one memory element of the thin film transistor memory. FIG. 4 is a manufacturing process diagram of the thin film transistor memory, and FIGS. 5 and 6 are a circuit diagram of the memory element and an equivalent circuit diagram thereof. 7 and 8 are a sectional view of one memory element of a thin film transistor memory and a manufacturing process thereof according to a second embodiment of the present invention. FIG. 9 is a circuit diagram of a conventional thin film transistor memory. M: memory element, T10: thin film transistor for memory, T20a, T20b ... thin film transistor for selection, G: gate electrode, 12, 13, ... gate insulating film, 17, 18 ... gate insulating film (17 ... non- Memory insulating film, 18 ... Memory insulating film), 14 ... i-type semiconductor layer, 15 ... N-type semiconductor layer, S ...
... source electrode, D ... drain electrode, GL ... gate line, SL ... source line, DL ... drain line.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (1)

(57) [Claims] 1. A thin film transistor memory comprising a memory thin film transistor and a selection thin film transistor for selecting the memory thin film transistor, wherein the selection thin film transistor is provided in series on both sides of the memory thin film transistor. .