JPH0360168A - Thin film transistor memory - Google Patents

Abstract

PURPOSE:To reduce element area, increase integration degree, and enable manufacturing with a few working processes, by constituting a thin film transistor for memory use, of a gate electrode, a part of a gate insulating film having charge storage function, a semiconductor layer, and source and drain electrodes, and constituting a thin film transistor for selection use, of a part of the gate insulating film having no charge storage function. CONSTITUTION:A memory element M is constituted by forming a memory transistor T10 and a selection transistor T20 in a thin film transistor. The memory transistor T10 is constituted of the following; a gate electrode G, a second gate insulating film 13 to which charge storage function is imparted by thinning the thickness, an I-type semiconductor layer 14, an N-type semiconductor layer 15, and source and drain electrodes S, D. The selection transistor T20 is constituted of the following; the gate electrode G, a gate insulating film which is constituted of a first and the second gate insulating films 12, 13 and has not the charge storage function, the I-type semiconductor layer 14, the N-type semiconductor layer 15, and the source and drain electrodes S, D.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistor memories.

[Conventional technology]

Recently, E2FR that can be written/erased/read electrically
As a memory such as OM, a thin film transistor memory in which a memory element is formed of a thin film transistor is considered.

FIG. 14 shows a cross section of one memory element M of a conventional thin film transistor memory. This thin film transistor memory has a memory thin film transistor T1 and a selection thin film transistor T2 formed adjacent to each other on an insulating substrate 1 made of glass or the like. A gate electrode G1 formed on the gate electrode G1, and a gate insulating film 2 having a charge storage function formed on the gate electrode G1 over the entire surface of the substrate 1.
An i-type semiconductor layer 3 made of ia-5t (i-type amorphous φ silicon) formed on this gate insulating film 2 to face the gate electrode G1, and an i-type semiconductor layer 3 formed on this i-type semiconductor layer 3 to face the gate electrode G1. An n-type semiconductor layer 4 made of n·-a-Si (amorphous silicon doped with n-type impurities) on both sides.
It consists of a source electrode S1 and a drain electrode D1 that are formed via a source electrode S1 and a drain electrode D1. The gate insulating film 2 of the memory transistor T1 has a composition ratio S i /N of silicon atoms S1 and nitrogen atoms N determined by a stoichiometric ratio (Sl/N −0
,75) thicker (Sl/N-0,85~1.
15) silicon nitride (S) with a charge storage function.
IN). The selection thin film transistor (hereinafter referred to as selection transistor) T2 includes a gate electrode G2 formed on the gate insulating film 2 of the memory transistor T1, and a gate insulating film without a charge storage function formed over the entire surface of the substrate 1. 5, an i-type semiconductor layer 6 made of 1-a-Si formed on this gate insulating layer 145 facing the gate electrode G2, and an i-type semiconductor layer 6 made of 1-a-Si formed on this i-type semiconductor layer 6 from n''-a-31. A source electrode S2 and a drain electrode p2 formed via an n-type semiconductor layer 7
It consists of The gate insulating film 5 of the selection transistor T2 changes the composition ratio SI/N to the stoichiometric ratio (Si/N
-0,75) is made of silicon nitride. The source electrode S2 of the selection transistor T2 is connected to the drain electrode D1 of the memory transistor T1 via a connection wiring 8 formed integrally with the source electrode S2.
A memory element M is constituted by the selection transistor T2 and the selection transistor T2. Further, the gate electrode G1 of the memory transistor T1 is connected to a first gate line GL1 formed integrally therewith, and the gate electrode G2 of the selection transistor T2 is connected to a second gate line GL1 formed integrally therewith.
Furthermore, the source electrode S1 of the memory transistor T1 is connected to a source line (not shown) integrated therewith, and the drain electrode D of the selection transistor T2 is connected to the source line (not shown).
2 is connected to an integral drain line (not shown). Note that 9 is a protective insulating film that covers the memory element M.

FIG. 15 is a circuit diagram of the conventional thin film transistor memory described above. In FIG. 15, GLI.

GL2 is a pair of gate lines (address lines),
SL and DL are source and drain lines (data lines), gate lines GL1. GL2 and source and drain lines SL.

The DLs are arranged in a matrix so as to be perpendicular to each other. The memory element M including the memory transistor T1 and the selection transistor T2 has a source connected to the gate lines GLI and GL2.

The gate electrode G1 of the memory transistor T1 is connected to the first gate line GLI of the pair of gate lines GLI and GL2, and the gate electrode of the selection transistor T2 is arranged at the intersection with the drain lines SL and DL, respectively. G2 is connected to the second gate line GL2. Further, the source electrode S1 of the memory transistor T1 is connected to the source line SL, and the drain electrode D2 of the selection transistor T2 is connected to the drain line DL.

Writing, erasing, and reading from this thin film transistor memory are performed as follows.

In FIG. 15, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading. Note that (a), (b), and (c) all show the state when one memory element M at the upper left in the figure is selected.

First, to explain writing, during writing, as shown in FIG. 15(a), the selected first and second gate lines GLI and GL2 are applied with a voltage corresponding to 1/2 of the write/erase voltage vP of the memory transistor T1, respectively. positive voltage +1/2
V, and the on-voltage VON (for example, +IOV) of the selection transistor T2 are applied, and a negative voltage -1/2VP corresponding to 1/2 of the write/erase voltage vP is applied to the selected source and drain lines SL and DL, respectively. The potential of the unselected first gate line GL1 and the source and drain lines SL and DL is O (ground), and the potential of the unselected second gate line GL2 is V. pp (for example, OV). Note that when the write/erase voltage V of the memory transistor T1 is, for example, 40V, "l/2V
p is +20V, -1/2Vp is 20V.

When such a voltage signal is applied, the selected gate lines GLI, GL2 and the source and drain lines SL, D
The selection transistor T2 of the memory element (hereinafter referred to as selected memory element) M located at the intersection with L is turned on, and a potential difference Di/2Vp corresponding to the write/erase voltage VP is created between the gate, source, and drain of the memory transistor T1. 11/
2VP (!: (7) potential difference) is generated, and this memory transistor T1 enters the write state. Note that in other memory elements (hereinafter referred to as non-selected memory elements) M on the selected gate lines GLI and GL2, the potential difference that occurs between the gate, source, and drain of the memory transistor T1 is only 1/2 Vp. , so this memory transistor T1 is in a write inhibited state. Also, regarding the memory elements on the unselected gate lines GLI and GL2, the memory element at the lower left in the figure is similar to the unselected memory element M described above, and the memory element is formed between the gate, source, and drain of the memory transistor T1. Potential difference is 1/2V p
Therefore, this memory transistor T1 is in a write inhibited state. Furthermore, regarding the memory element at the lower right of the figure, the potential generated between the gate, source, and drain of the memory transistor T1 is 0 (no voltage applied).
It is. That is, the gate, source, and drain are at the same potential, so this memory transistor T1
is also in a write-blocked state.

Further, during erasing, as shown in FIG. 15(b), the first and second gate lines GLI are selected.

Apply 1/2 Vp r VON to GL2 and select the source and drain lines SL.

+1/2Vp is applied to each DL. Note that unselected gate lines GLI, GL2 and sources.

The signals applied to the drain lines SL and DL are the same as in the above writing. When such a voltage signal is applied, an opposite potential difference corresponding to the write/erase voltage VP is generated between the gate, source, and drain of the memory transistor T1 of the selected memory element M, and the voltage is held in the memory transistor T1. The existing data will be deleted. In this case as well, the potential difference generated between the gate and source drain of the memory transistor T1 of the unselected memory element M is only 1/2 VP, and this memory transistor T1 is in the erasure inhibited state.

On the other hand, during reading, as shown in FIG. 15(c), the first and second gate lines GLI are selected.

V SEL r VON is applied to each of GL2, and VD is applied to the drain line DL of the selected source and drain lines SL and DL, and the potential of the source line SL is set to 0. In addition, the above V5ILL and VD
is the write/erase voltage Vp of the memory transistor T1
(40V), for example, Vsgt
, -OV% Vo =10Vte.

Also, during this reading, unselected gate lines GLI,
The signals applied to GL2 and the source and drain lines SL and DL are the same as those during writing and erasing. When such a voltage signal is applied, a current flows from the drain line DL to the source line SL in accordance with the data held in the memory transistor T1 of the selected memory element M.
This is output as read data.

In addition, in any of the above write, erase, and read operations, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. However, the gate potential of the selection transistor T2 of this unselected memory element M is . 1. Therefore, the memory transistor T1 of the unselected memory element M is not affected by the applied voltage. That is, the selection transistor T2 not only selects the memory transistor T1, but also functions as a guard transistor that guards the memory transistor T1 from the voltage applied when it is not selected.

[Problem to be solved by the invention]

However, the conventional thin film transistor memory described above is
Since the memory transistor T1 and the selection transistor T2 constituting each memory element M are formed adjacent to each other, the element area of one memory element M is large;
Therefore, there was a problem in that it was difficult to increase the degree of integration. Furthermore, the conventional thin film transistor memory described above has a memory transistor T1 formed on a substrate 1 and a selection transistor T2 formed on a gate insulating film 2 of this memory transistor T1. and must be manufactured in separate processes, which requires a large number of processes to manufacture a thin film transistor memory.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to increase the degree of integration by reducing the element area of a memory element composed of a memory thin film transistor and a selection thin film transistor. It is an object of the present invention to provide a thin film transistor memory that can be easily manufactured with a small number of steps.

[Means to solve the problem]

In order to achieve the above object, the thin film transistor memory of the present invention has a gate electrode and a part of the region corresponding to the gate electrode having a charge storage function, and other regions having a gate insulation function without a charge storage function. A film, a semiconductor layer, and source and drain electrodes formed on both sides of this semiconductor layer are stacked, and the gate electrode and a portion of the gate insulating film having a charge storage function, the semiconductor layer, and the source and drain electrodes are stacked. The electrode constitutes a memory thin film transistor, and the gate electrode, the portion of the gate insulating film that does not have a charge storage function, the semiconductor layer, and the source and drain electrodes constitute a selection thin film transistor.

[Effect]

That is, in the thin film transistor memory of the present invention, by making the gate insulating film of the thin film transistor an insulating film that has a charge storage function only in a part of the region corresponding to the gate electrode, the thin film transistor memory has a charge storage function. A thin film transistor for memory and a thin film transistor for selection are formed, and according to this thin film transistor memory, the element area of the memory element composed of the thin film transistor for memory and the thin film transistor for selection can be reduced and the degree of integration can be increased. Furthermore, since the memory thin film transistor and the selection thin film transistor constituting the memory element can be formed in the process of manufacturing one thin film transistor, manufacturing can be easily performed with a small number of steps.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 6 show a first embodiment of the present invention, and FIGS. 1 and 2 are a sectional view and a plan view of one memory element M of a thin film transistor memory.

To explain the structure of this memory element M, reference numeral 11 in the figure is an insulating substrate made of glass or the like, and on this substrate 11 are thin film transistors TIO and T2 for both memory and selection.
A gate electrode G shared by O and a gate line GL connected to this gate electrode G are formed. Further, a first gate insulating film 12 is formed on the substrate 11, covering approximately half of the gate electrode G, that is, the gate electrode portion of the selection transistor 72G, and further on top of that, the first gate insulating film 12 covers approximately half of the gate electrode G, that is, the gate electrode portion of the selection transistor 72G. A second gate insulating film 13 is formed to cover the entire structure. These first and second gate insulating films 12.
13 is the composition ratio Si/N of silicon atoms Sl and nitrogen atoms N, respectively, as the stoichiometric ratio (S i / N −0,7
The first gate insulating film 12 is made of silicon nitride (SIN), which is approximately the same as 5), and the first gate insulating film 12 has a film thickness of approximately 2.5 cm.
The second gate insulating film 13 is a thin film with a thickness of about 500 Å to 1,500 Å. That is, the gate insulating film on the gate electrode G is
Approximately half of the selection transistor 720 portion of the gate electrode G is a two-layer film consisting of the first and second gate insulating films 12 and 13, and the other half of the memory transistor T10
In some parts, it is a thin film consisting only of the second gate insulating film 13. Since the second gate insulating film 13 in the memory transistor T10 portion is thin, it has a charge storage function even though its composition ratio Si/N is almost the same as the stoichiometric ratio.

Note that the gate insulating film 12 of the selection transistor T20 portion
．． 13 does not have a charge storage function because its entire film thickness is thick. Further, on the second gate insulating film 13, an i-type semiconductor layer 14 is formed so as to face the entire area of the gate electrode G and is shared by the memory transistor TIO and the selection transistor T20. This i-type semiconductor layer 14 is made of 1-a-st (i-type amorphous silicon). Then, this i-type semiconductor layer 14
A source electrode S and a drain electrode are connected to both sides above the electrode via an n-type semiconductor layer 15 made of n''-a-Si (amorphous silicon doped with n-type impurities). The source electrode S10 is connected to a source line SL that is integrated with this, and the drain electrode is connected to a drain line DL that is integrated with this.Note that 16 is a protective insulating film that covers the memory element M.

That is, in the thin film transistor memory of this embodiment, the memory element M has a structure in which a memory transistor TIO and a selection transistor T20 are formed in one thin film transistor, and the memory transistor TIO has a gate electrode G and a film. The selection transistor T20 is composed of a second gate insulating film 13 having a thinner thickness and having a charge storage function, an i-type semiconductor layer 14, an n-type semiconductor layer 15, and source and drain electrodes S and D. The gate electrode G, the gate insulating film having no charge storage function consisting of the first and second gate insulating films 1.2.13, the i-type semiconductor layer 14 and the n-type semiconductor layer 15, and the source and drain It is composed of electrodes S and D.

FIG. 3 shows a method for manufacturing the thin film transistor memory described above, and this thin film transistor memory is manufactured through the following steps.

First, a metal film such as chromium is deposited on the substrate 11, and this metal film is patterned to form a gate electrode G and a gate line GL connected to the gate electrode G, as shown in FIG. 3(a). At the same time, a first gate insulating film 12 is deposited thereon over the entire surface of the substrate 11.

Next, as shown in FIG. 3(b), one side of the first gate insulating film 12 from approximately the center of the gate electrode G is removed by etching, and the memory transistor T1 is etched.
The 0 portion of the gate electrode G is exposed.

Thereafter, as shown in FIG. 3(c), a second gate insulating film 13 is deposited over the entire surface of the substrate 11, and an i-type semiconductor layer 14 made of 1-a-Si is placed thereon.
and an n-type semiconductor layer 15 consisting of n''-a-3l are sequentially deposited.

Next, as shown in FIG. 3(d), the n-type semiconductor layer 1
5 is patterned into the shape of the source and drain electrodes S and D, and then the i-type semiconductor layer 14 is patterned into the shape of the memory element region.

After this, a metal film such as chromium, which will become the source and drain electrodes S and D, is deposited over the entire surface of the substrate 11, and this metal film is patterned to form the source and drain electrodes S and D, as shown in FIG. 3(e). A source line SL, a drain electrode layer, and a drain line DL are formed, and a protective insulating film 16 is formed thereon to complete the thin film transistor memory shown in FIGS. 1 and 2.

In this embodiment, approximately half of the gate electrode G is used as the gate electrode of the selection transistor T20, and the other half is used as the gate electrode of the memory transistor T10. However, the areas of the gate electrodes of the memory transistor TIO and the selection transistor T20 are as follows. The area of the first gate insulating film 12 to be left on the gate electrode G can be determined based on how the characteristics of each transistor TIO and T2O are selected.

FIG. 4 shows the circuit of the memory element M, and FIG. 5 shows its equivalent circuit.

FIG. 6 is a circuit diagram of a thin film transistor memory configured by arranging the memory elements M in a matrix, and in the figure, each memory element M is shown as an equivalent circuit of FIG. 5.

In FIG. 6, GL is a gate line (address line), SL and DL are source and drain lines (data lines), and the gate line GL and source and drain lines SL and DL are arranged in a matrix so as to be perpendicular to each other. has been done. The memory element M is
Gate line GL and source and drain lines SL and DL
The gate electrodes (common electrodes) G of the memory transistor TIO and the selection transistor T20 are connected to the gate line GL. Further, the source electrode S of the memory transistor TLG is connected to the source line SL, and the drain electrode of the selection transistor T20 is connected to the drain line DL.

Writing, erasing, and reading from this thin film transistor memory are performed as follows.

In FIG. 6, (a) is when writing, (b) is when erasing,
(c) shows the voltage application state during reading. In addition,
(a), (b), and (c) all show the state when one memory element M in the upper left corner of the figure is selected.

First, to explain about writing, when writing, Figure 6 (a
), the write/erase voltage Vp (for example, 40V) of the memory transistor TIO is applied to the gate line GL to be selected.
) is a positive voltage corresponding to 1/2 of p (+2
0V) Apply the above write/erase voltage V to the selected source and drain lines SL and DL, respectively.
Negative voltage -1/2VP (-20
V) The potential of the voltage applied L, the master non-selection select line GL, and the source and drain lines SL and DL is 0 (ground).
shall be. When such a voltage signal is applied, the selected gate line GL and source/drain lines SL, DL
The selection transistor 720 of the selected memory element M located at the intersection with is turned on, and a potential difference corresponding to the write/erase voltage vP is generated between the gate, source, and drain of the memory transistor TIO, and this memory transistor TIO is placed in the write state. becomes. In addition, in other unselected memory elements M on the selected gate line GL, the potential difference between the gate, source, and drain of the memory transistor TIO and the selection transistor T20 is only 1/2V P, and therefore this memory Transistor TIO is in a write inhibited state. Regarding the memory elements on the unselected gate line GL, the memory element at the lower left in the figure is similar to the unselected memory element M described above, and the potential difference between the gate, source, and drain of the memory transistor TIO is 1/ 2V, so this memory transistor TIO is in a write inhibited state. Furthermore, regarding the memory element at the bottom right of the figure, the unselected memory element M
Similarly, if the potential generated between the gate, source, and drain of the memory transistor TIO is 0 (no voltage applied)
It is.

That is, the gate, source, and drain are at the same potential, so this memory transistor TIO is also in a write inhibited state.

Further, during erasing, as shown in FIG. 6(b), 11/2 VP is applied to the selected gate line GL, and the selected source and drain lines SL.

+l/2Vp is applied to each DL. Note that the unselected gate line GL and source/drain line SL
, DL are the same as in the above writing. When such a voltage signal is applied, an opposite potential difference corresponding to the write/erase voltage VP is generated between the gate, source, and drain of the memory transistor TIO of the selected/selected memory element M. At this time, a voltage of -VP is applied between the gate electrode G and the source and drain electrodes S and D of the transistor T20, similarly to the memory transistor TIO. Normally, in a thin film transistor whose semiconductor layer is made of amorphous silicon, polysilicon, or the like, even when a high negative voltage is applied to the gate electrode, conduction occurs between the source and drain, and the thin film transistor is turned on. Therefore, selection transistor T
20 is turned on by a high negative voltage -■, and the data held in the memory transistor TIO is erased.

In this case as well, the potential difference that occurs between the gate, source, and drain of the memory transistor TIO of the unselected memory element M is only 1/2Vp, and this memory transistor TIO
1 is in the erasure inhibited state.

On the other hand, at the time of reading, as shown in FIG. 6(c), VOS is applied to the selected gate line GL, and the selected source and drain lines SL.

VD is applied to the drain line DL of DL, and the potential of the source line SL is set to O. In addition, the above VON and VD
is the write/erase voltage Vp of the memory transistor TIO
(40V), for example, V O
N-10V, Vo=LOV. In addition, V is applied to the unselected gate line GL. Apply pp (OV) to unselected source and drain lines SL.

The potential of DL is set to 0. When such a voltage signal is applied, a current flows from the drain line DL to the source line SL in accordance with the data held in the memory transistor TIO of the selected memory element M, and this is output as read data.

In addition, in any of the above write, erase, and read operations, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. However, the selection transistor T20 of this unselected memory element M has its gate potential at a negative voltage -i/2vPttahaVopp (OV
) The memory transistor TIO of the non-selected memory element M is not affected by the applied voltage because it is in the off state due to the presence of the voltage. That is, in this thin film transistor memory as well, the selection transistor T20 not only selects the memory transistor TIO but also functions as a guard transistor that guards the memory transistor T10 from the voltage applied when it is not selected.

However, in the thin film transistor memory of the above embodiment,
Since the memory element M has a structure in which the memory transistor TIO and the selection transistor T20 are formed in one thin film transistor, the element area of the memory element M can be made extremely small, and therefore the degree of integration can be further increased. Furthermore, since the memory transistor TIO and the selection transistor T20 constituting the memory element M can be formed in the process of manufacturing one thin film transistor, it can be easily manufactured with a small number of steps.

Moreover, in this thin film transistor memory, since the gate electrode G of the memory transistor TIO and the selection transistor T20 constituting the memory element M is a common electrode, the gate line GL connecting the memory transistor TIO and the gate electrode G of the selection transistor T20 is a common electrode. Since the gate line GL may be a common line, the number of gate lines is half that of a conventional thin film transistor memory, and the area required for wiring the gate line GL can be reduced by that much, thereby reducing the area of the entire memory.

Next, another embodiment of the present invention will be described.

7 and 8 show a second embodiment of the present invention, and FIG. 7 shows a cross section of one memory element M of a thin film transistor memory. Components in the figures corresponding to the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals and their explanations will be omitted.

As shown in FIG. 7, the thin film transistor memory of this embodiment has a memory transistor TIO of the memory element M.
The gate insulating film is a non-memory insulating film made of silicon nitride (SjN), which does not have a charge storage function and has a composition ratio S i /N almost the same as the stoichiometric ratio (St /N-0,75). The film 17 and the composition ratio Si/N are made thicker than the stoichiometric ratio (S i / N −0,1115 to 1.15
) and a memory insulating film 18 made of silicon nitride which has a charge storage function, and the gate insulating film of the selection transistor T20 is only the non-memory insulating film 17. The insulating film 17 is used for both memory and selection thin film transistors T10. T
It is formed on the gate electrode G shared by the gate electrode G, covering the entire area thereof.

Further, the memory insulating film 18 is a non-memory insulating film 1.
7, the memory transistor TI of the gate electrode G
It is formed to face a portion of O that will become the gate electrode (approximately half of the gate electrode G in the figure). The thickness of the non-memory insulating film 17 is about 2000, and the memory insulating film 18 is an extremely thin film with a thickness of 100λ. The memory transistor TIO includes a gate electrode G, a gate insulating film consisting of a non-memory insulating film 17 and a memory insulating film 18, an i-type semiconductor layer 14, an n-type semiconductor layer 15, and source and drain electrodes S. , D, and the selection transistor T20 is composed of the gate electrode G and
A gate insulating film made of the non-memory insulating film 17, the i-type semiconductor layer 14 and the n-type semiconductor layer 15, and the source and drain electrodes S.

It is composed of D.

FIG. 8 shows a method of manufacturing the above-mentioned thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, a metal film such as chromium is deposited on the substrate 11, and this metal film is patterned to form a gate electrode G and a gate line GL connected to the gate electrode G at the same time, as shown in FIG. 8(a). A non-memory insulating film 17 and a memory insulating film 18 are sequentially deposited thereon over the entire surface of the substrate 11.

Next, as shown in FIG. 8(b), a portion of the memory insulating film 18 other than the memory transistor T10 portion is removed by etching, and then, as shown in FIG. 8(c), the entire surface of the substrate 11 is etched. , an i-type semiconductor layer 14 made of 1-a-Sl, an n-type semiconductor layer 15 made of n+-a-Sl, and a source.

One metal film such as chromium, which will become the drain electrodes S and D, is sequentially deposited.

After this, as shown in FIG. 8(d), one metal film and the n-type semiconductor layer 15 are patterned to form a source electrode S.
After forming a source line, a drain electrode, and a drain line, and then patterning the i-type semiconductor layer 14 in the shape of the memory element region, a protective insulating film 16 is formed thereon.
is formed to complete the thin film transistor memory shown in FIG.

In this embodiment as well, the areas of the gate electrodes of the memory transistor TIO and the selection transistor T20 may be determined depending on how the characteristics of each transistor TIO and T2O are selected.
All you have to do is choose the area of .

The circuit of the memory element M is the same as that shown in FIG. 5, and its equivalent circuit is shown in FIG.

Since the thin film transistor memory of this second embodiment also has a structure in which the memory transistor TIO and the selection transistor T20 are formed in one thin film transistor, the element area of the memory element M can be made very small. , Therefore, the degree of integration can be further increased, and the memory transistor T constituting the memory element M can be reduced in the process of manufacturing one thin film transistor.
Since the selection transistor T20 and the selection transistor T20 can be formed, it can be easily manufactured with a small number of steps.

Furthermore, in this embodiment as well, the gate line GL connecting the gate electrode G of the memory transistor TIO and the selection transistor T20 may be a common line, so the area required for the wiring of the gate line GL can be reduced, and the area of the entire memory can be reduced. Can be made smaller.

Further, FIGS. 9 and 10 show third and fourth embodiments of the present invention, respectively, and in each of the thin film transistor memories of these embodiments, the memory element M is connected to two selection transistors. This structure has T2G provided on both sides of the memory transistor TIO.

That is, the third embodiment shown in FIG. M9 is the same as the first embodiment shown in FIGS. 1 and 2.

The first gate insulating film 12 is a memory transistor TIO.
By forming the gate electrode G, which is common to the selection transistors 720 and 720, except for the central part, the central part of the memory element M becomes the memory transistor Tlo, and both sides thereof become the selection transistors T2Q. In addition,
The structure of the thin film transistor memory of this embodiment is the same as that of the first embodiment except that the selection transistor T20 is formed on both sides of the memory transistor TIO. omitted.

Furthermore, in the fourth embodiment shown in FIG. 10, the memory insulating film 18 in the second embodiment shown in FIG. The central part of the memory element M is formed as a memory transistor TIO, and both sides thereof are respectively formed as selection transistors T20. Note that the thin film transistor memory of this example also has the following characteristics:
A selection transistor T is placed on both sides of the memory transistor TIO.
Since the configuration other than the formation of 2o is the same as that of the second embodiment, a description thereof will be omitted by assigning the same reference numerals to corresponding parts in the drawings.

FIG. 11 shows the memory element M of the third and fourth embodiments.
Figure 12 shows the equivalent circuit.
FIG. 13 shows a circuit configuration of a thin film transistor memory to which the third and fourth embodiments are applied. Note that in the thin film transistor memories of the third and fourth embodiments, the voltages shown in FIG. 6 are applied to the gate line GL and the source and drain lines S for writing, erasing, and reading.

This can be done by applying it to D.

Also in the thin film transistor memories of the third and fourth embodiments, the memory element M has a structure in which the memory transistor TIO and the two selection transistors T20 are formed in one thin film transistor. The device area of 1
Since the memory transistor TIO and the selection transistor T20 constituting the memory element M can be formed in the process of manufacturing one thin film transistor, the memory transistor TIO and the selection transistor T20 can be easily manufactured with a small number of steps. As a common line, the gate line GL connecting the gate electrodes G of
The entire memory area can be reduced. moreover,
In the third and fourth embodiments, since the two selection transistors T20 are provided on both sides of the memory transistor T10, even if one of the selection transistors T20 has poor characteristics, the other selection transistor T
20 allows selection and guarding of the memory transistor TIO, thus improving reliability.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, the gate insulating film of the thin film transistor is an insulating film that has a charge storage function in a part of the region corresponding to the gate electrode, so that a memory thin film transistor is included in one thin film transistor. and a selective thin film transistor, it is possible to reduce the element area of the memory element consisting of the memory thin film transistor and the selective thin film transistor and increase the degree of integration, and it can be easily manufactured with a small number of steps. can do.

[Brief explanation of drawings]

1 to 6 show a first embodiment of the present invention, FIGS. 1 and 2 are a sectional view and a plan view of one memory element of a thin film transistor memory, and FIG. 3 is a thin film transistor memory. 4 and 5 are a circuit diagram of a memory element and its equivalent circuit diagram, and FIG. 6 is a circuit diagram of a thin film transistor memory. Figures 7 and 8
The figure is a cross-sectional view of one memory element of a thin film transistor memory showing a second embodiment of the present invention, and a diagram of its manufacturing process;
9 and 10 are cross-sectional views of one memory element of a thin film transistor memory showing third and fourth embodiments of the present invention, and FIGS. 11 and 12 are memories of the third and fourth embodiments. Circuit diagram of the element and its equivalent circuit diagram, 1st
FIG. 3 is a circuit diagram of the thin film transistor memory of the third and fourth embodiments. FIG. 14 is a sectional view of one memory element of a conventional thin film transistor memory, and FIG. 15 is a circuit diagram of the conventional thin film transistor memory. M...Memory element, TIO...Thin film transistor for memory, 720...Thin film transistor for selection, G...
・Gate electrode, 12.13... Gate insulating film, 14.
...i-type semiconductor layer, 15...n-type semiconductor layer, S...
Source electrode, D... Drain electrode, 17... Non-memory insulating film (gate insulating film without charge storage function), 18
...Insulating film for memory (gate insulating film with charge storage function).

Claims (1)

[Claims] In a thin film transistor memory that includes a memory thin film transistor and a selection thin film transistor that selects the memory thin film transistor, a gate electrode and a part of the region corresponding to the gate electrode have a charge storage function, and other regions have a charge storage function. A gate insulating film that does not have a charge storage function, a semiconductor layer, and source and drain electrodes formed on both sides of this semiconductor layer are stacked, and the gate electrode and the portion of the gate insulating film that has a charge storage function and the The semiconductor layer and the source and drain electrodes constitute a memory thin film transistor, and the gate electrode and a portion of the gate insulating film that does not have a charge storage function, the semiconductor layer and the source and drain electrodes constitute a selection thin film transistor. A thin film transistor memory characterized by: