JPH0472673A - Thin-film transistor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase an integration density by a method wherein the channel region of a memory transistor and the channel region of a selective transistor are connected at a part corresponding to the side edge of a lower-part gate electrode. CONSTITUTION:A lower-part gate electrode G1 whose shape is the same as that of a gate insulating film 4 for memory transistor use is formed on it; and its line part is wired on a substrate 1. The insulating film 4 is formed also under the line part of the lower-part gate electrode G1. Selective transistors T2 are constituted of the following: a source electrode and a drain electrode S, D; a semiconductor layer 3; a gate insulating film 5 for selective transistor use; and an upper-part gate G2. Then, a transistor T1 and two transistors T2 situated on both sides are formed. As a result, it is possible to reduce the rear of a transistor memory constituted of the transistor T1 and the transistors T2 and to increase an integration density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor memory and a method for manufacturing the same.

[Conventional technology]

Recently, E2FR that can be electrically written, erased, and read
As a memory such as an OM, a thin film transistor memory is considered in which a memory transistor and a selection transistor for selecting the memory transistor are thin film transistors.

Conventionally, this thin film transistor memory is formed by forming a thin film transistor for memory (hereinafter referred to as a memory transistor) and a thin film transistor for selection (hereinafter referred to as a selection transistor) adjacent to each other on an insulating substrate made of glass or the like. A transistor memory is known in which a transistor and a selection transistor are connected in series through a connection wiring that connects the source electrode of one transistor and the drain electrode of the other transistor. Note that the memory transistor and the selection transistor are, for example, stagger-type thin film transistors in which a source, a drain electrode, a semiconductor layer, a gate insulating film, and a gate electrode are stacked, and the gate insulating film of the memory transistor is The gate insulating film of the selection transistor is formed of an insulating film having a memory function and has no charge storage function.

[Problem to be solved by the invention]

However, the conventional thin film transistor memory
A memory transistor and a selection transistor are formed adjacent to each other on a substrate, and the memory transistor and selection transistor are connected in series by connection wiring, so a transistor memory composed of a memory transistor and a selection transistor is The problem is that the area is large, and therefore it is difficult to increase the degree of integration of a memory matrix formed by arranging transistor memories vertically and horizontally.

The present invention has been made in view of the above circumstances, and its purpose is to provide a thin film transistor that can increase the degree of integration by reducing the area of a transistor memory composed of a memory transistor and a selection transistor. An object of the present invention is to provide a memory and also a manufacturing method thereof.

[Means to solve the problem]

The thin film transistor memory of the present invention includes source and drain electrodes formed on an insulating substrate, a semiconductor layer formed on the substrate with both sides overlapping the source and drain electrodes, and a portion of this semiconductor layer. a gate insulating film for a memory transistor having a charge storage function at least at an interface with the semiconductor layer formed on the gate insulating film; and a lower gate electrode formed in the same shape as the gate insulating film for a memory transistor on the gate insulating film for a memory transistor. , a gate insulating film for a selection transistor without a charge storage function that covers the lower gate electrode and the semiconductor layer, and a gate insulating film for a selection transistor that covers at least the entire region between the source and drain electrodes of the semiconductor layer and faces the gate insulating film for the selection transistor. a memory transistor is configured by the source and drain electrodes, the semiconductor layer, the memory transistor gate insulating film, and the lower gate electrode, and the source and drain electrodes and the semiconductor layer A selection transistor is configured by the selection transistor gate insulating film and the upper gate electrode.

Further, the method for manufacturing a thin film transistor memory of the present invention includes the following steps: forming source and drain electrodes on an insulating substrate; and forming a semiconductor layer on the substrate so that both sides overlap with the source and drain electrodes. , a gate insulating film for a memory transistor having a charge storage function and a metal film for a lower gate electrode are sequentially deposited on the substrate at least at an interface with the semiconductor layer; patterning into a shape corresponding to a part of the semiconductor layer; depositing a gate insulating film for a selection transistor without a charge storage function on the lower gate electrode and the semiconductor layer; The method is characterized by comprising the steps of: forming an upper gate electrode on the film so as to face at least the entire region between the source and drain electrodes of the semiconductor layer.

[Effect]

That is, in the thin film transistor memory of the present invention, one thin film transistor has an upper gate electrode facing at least the entire region between the source and drain electrodes of the semiconductor layer;
A lower gate electrode provided between the upper gate electrode and the semiconductor layer and facing a part of the semiconductor layer.
The lower gate electrode is formed on a gate insulating film for a memory transistor having a charge storage function, which is provided on a portion of the semiconductor layer at least at the interface with the semiconductor layer. The upper gate electrode is formed on a gate insulating film for a selection transistor having no charge storage function, which is laminated on a semiconductor layer and covering the lower gate electrode. A memory transistor and a selection transistor, which share a semiconductor layer and source and drain electrodes, are connected in series in the semiconductor layer.

In this thin film transistor memory, the portion of the semiconductor layer where the lower gate electrodes are opposed becomes the channel region of the memory transistor, and the portion where the lower gate electrodes are not opposed and only the upper gate electrodes are opposed is the channel region of the memory transistor. Since this becomes the channel region of the selection transistor, the selection transistor operates by applying a gate voltage to the upper gate electrode, and the memory transistor operates by applying a gate voltage to the lower gate electrode. Further, the channel region of the memory transistor and the channel region of the selection transistor are formed to be connected to each other at a portion corresponding to a side edge of the lower gate electrode.

Moreover, in this thin film transistor memory, the lower gate electrode that is the gate electrode of the memory transistor also acts as an electrode that shields the gate voltage applied to the semiconductor layer from the upper gate electrode that is the gate electrode of the selection transistor. The memory transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
After forming source and drain electrodes and a semiconductor layer on an insulating substrate, a gate insulating film for a memory transistor having a charge storage function and a metal film for a lower gate electrode are sequentially deposited thereon. The gate insulating film for the memory transistor and the lower gate electrode constituting the memory transistor are simultaneously formed by patterning the gate insulating film for the memory transistor into a shape corresponding to a part of the semiconductor layer, and then the lower gate electrode and the semiconductor layer are patterned. The thin film transistor of the present invention is manufactured by depositing a gate insulating film for a selection transistor without a charge storage function thereon and forming an upper gate electrode thereon.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 show a first embodiment of the present invention, and FIG. 1 is a sectional view of a thin film transistor memory.

To explain the structure of this thin film transistor memory, numeral 1 in the figure is an insulating substrate made of glass or the like.

On this substrate 1, source and drain electrodes S and D and their line parts (not shown) are formed, and on these source and drain electrodes S and D, n-type amorphous
An ohmic contact layer 2 made of silicon (n''-a-8i) is laminated.

Note that the ohmic contact layer 2 is a source.

It is also laminated on the line portions of the drain electrodes S and D. Reference numeral 3 denotes a semiconductor layer made of i-type amorphous silicon (ia-St), which is formed on the substrate 1 by laminating both side portions on the source and drain electrodes S and D. This semiconductor layer 3 is a source.

Over the entire area between the drain electrodes S and D, both side edges are formed in an area that almost corresponds to the outer edges of the source electrode S and the drain electrode, and both side parts of the semiconductor layer 3 are connected to each other through the ohmic contact layer 2. It is electrically connected to source and drain electrodes S and D. Note that the thickness of this semiconductor layer 3 is 500 layers. A memory transistor gate insulating film 4 is provided on the central portion of this semiconductor layer 3. This gate insulating film 4 for memory transistor
A memory insulating film 4 having a charge storage function is provided, and this memory insulating film 4 includes a memory film 4a with a thickness of 100 mm formed on the semiconductor layer 3, and a memory film 4a laminated thereon. The memory film 4a and the voltage-resistant film 4b are formed in the same shape.

The memory film 4a and the voltage-resistant film 4b are both silicon nitride (StN) films, and the voltage-resistant film 4b has a composition ratio of silicon atoms St and nitrogen atoms N (St/N) set to a stoichiometric ratio. The memory film 4 is formed of silicon nitride which has a charge storage function and has a silicon atomic weight larger than the stoichiometric ratio. Note that this memory film 4a and the voltage-resistant film 4
The width of the lower gate electrode 4 in the left-right direction in the figure is approximately 1/3 of the distance between the source and drain electrodes S and D, and
In the figure, the width in the front and back directions of the paper is approximately equal to the width of the semiconductor layer 3. Further, a lower gate electrode G1 having the same shape as the lower gate electrode G1 is formed on the memory transistor gate insulating film 4, and its line portion (not shown) is as follows.
Wired on the board 1. Note that the memory transistor gate insulating film 4 is also formed over the entire length under the line portion of the lower gate electrode G1.

5 is a gate insulating film for a selection transistor formed on the substrate 1 to cover the lower gate electrode G, its line portion, and the semiconductor layer 3; this gate insulating film 5 for a selection transistor has no charge storage function; Made of silicon nitride. The film thickness of this selection transistor gate insulator M5 is 2000 mm. Then, on this gate insulating film 5 for the selection transistor, an upper gate electrode G2 and its line portion (not shown) are arranged so as to face at least the entire region between the source and drain electrodes S and D of the semiconductor layer 3. It is formed. In this embodiment, the upper gate electrode G2 is formed to be slightly smaller than the semiconductor layer 3, and to have both side edges facing the central portions of the source electrode S and the drain electrode. Further, the line portion of the upper gate electrode G2 is formed at a position that does not vertically overlap with the lower gate electrode G1.

The central portion of the thin film transistor memory of this embodiment is a memory transistor T1, and both sides thereof are selection transistors T2, and the memory transistor T1 has source and drain electrodes S and D, a semiconductor layer 3, The memory transistor gate insulating film 5 is composed of a memory transistor gate insulating film 5 whose interface with the semiconductor layer 3 is a memory film 4a having a charge storage function, and a lower gate electrode G1. Further, both sides of this memory transistor T are respectively used as selection transistors G2, and this selection transistor G
2 is composed of the source and drain electrodes S and D, the semiconductor layer 3, a gate insulating film 5 for a selection transistor, and an upper gate electrode G2. This memory transistor T1 and the two selection transistors T2- on both sides thereof are connected in series via a semiconductor layer 3 which is also used for both. That is, the entire region of the region between the source electrode S and the drain electrode of the semiconductor layer 3, where the lower gate electrode G1 faces, becomes the channel region C1 of the memory transistor T1, and the lower gate electrode G1 is The entire area of the part where only the upper gate electrode G2 faces without facing each other is the channel region C2 of the selection transistor T2, and the channel region C1 of the memory transistor T1 and the channel region G2 of the selection transistor T2 are as follows. Since the memory transistor T1 and the two selection transistors T2 on both sides thereof are formed in a state where they are connected to each other at the portion corresponding to the side edge of the lower gate electrode G1, the memory transistor T1 and the two selection transistors T2 on both sides thereof are connected to each other in the channel region G of the semiconductor layer 3.
, , G2 are connected in series with good conductivity. Furthermore, the two selection transistors T2 on both sides of the memory transistor T are turned on at the same time because their gate electrodes (upper gate electrodes) G2 are common electrodes.

It is supposed to work off.

FIG. 2 shows a method for manufacturing the thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, as shown in FIG. 2(a), source and drain electrodes S, D and their line portions, and an ohmic contact layer 2 thereon are formed on a substrate 1. This sauce,
The drain electrodes S and D, their line parts, and the ohmic contact layer 2 are formed by sequentially depositing metal such as chromium and n-type amorphous silicon on the substrate 1 to a thickness of 250 nm each. The layer and this metal film are formed by patterning in the shape of the source and drain electrodes S, D and their line portions.

Next, as shown in FIG. 2(b), a semiconductor layer 3 is placed on the substrate 1, with both sides overlapping the source and drain electrodes S and D.
form. This semiconductor layer 3 is formed by depositing i-type amorphous silicon to a thickness of 1000 nm on the substrate 1 and patterning this i-type amorphous φ silicon layer.

Next, as shown in FIG. 2(c), a memory film (a silicon nitride film with a charge storage function) 4a, which will become the gate insulating film 4 for the memory transistor, and a breakdown voltage film (a silicon nitride film without a charge storage function) are placed on the substrate 1. silicon nitride film) 4b and 100 people, 900
The metal film M for the lower gate electrode, such as chromium, is deposited on top of this to a thickness of 500 mm.

Next, as shown in FIG. 2(d), the metal film M, the memory transistor gate insulating film 4 made of the memory film 4a and the breakdown voltage film 4b are shaped to correspond to the central part of the semiconductor layer 3. The lower gate electrode G1 made of the metal film M and its line portion, and the gate insulating film 4 for a memory transistor having the same shape as the lower gate electrode G1 are completed.

Next, as shown in FIG. 2(e), a selection transistor gate insulating film (silicon nitride film without charge storage function) 5 is formed over the entire surface of the substrate 1 on the lower gate electrode G1 and the semiconductor layer 3. deposited to a thickness of 2,000 people,
Next, on this selection transistor gate insulating film 5,
The above-mentioned thin film transistor memory is completed by depositing a metal such as chromium to a thickness of 1000 nm and patterning this metal film to form the upper gate electrode G2 and its line portion.

That is, the thin film transistor memory of this embodiment has 1
In one thin film transistor, an upper gate electrode G2 facing at least the entire region between the source and drain electrodes S and D of the semiconductor layer 3, and the upper gate electrode G2 and the semiconductor layer 3 are provided.
and a lower gate electrode G1 provided between and facing the central part of the semiconductor layer 3, and the lower gate electrode G1 is provided above the central part of the semiconductor layer 3, The upper gate electrode G2 is formed in the same shape as the memory transistor gate insulating film 4 having a charge storage function at the interface with the semiconductor layer 3, and the upper gate electrode G2 covers the semiconductor layer 3. A gate insulating film 5 for a selection transistor without a charge storage function laminated on top of the gate insulating film 5
By forming the memory transistor T1 and the selection transistor T2, which share the semiconductor layer 3 and the source and drain electrodes S and D, in one thin film transistor, the memory transistor T1 and the selection transistor T2 are connected in series in the semiconductor layer 3. It was formed.

According to this thin film transistor memory, a memory transistor T1 and two selection transistors T2 located on both sides of the memory transistor T are formed in one thin film transistor. It is possible to increase the degree of integration by reducing the area of the transistor memory configured with .

In this thin film transistor memory, the lower gate electrode G of the semiconductor layer 3.

The part where these are opposed becomes the channel region C1 of the memory transistor T1, and the part where the lower gate electrode Gl is not opposed and only the upper gate electrode G2 is opposed is the channel region C2 of the selection transistor T2. The selection transistor T2 can be operated by applying a gate voltage to the electrode G2, and the memory transistor T1 can be operated by applying a gate voltage to the lower gate electrode G1. Further, the upper gate electrode G2, which is the gate electrode of the selection transistor T2, is connected to the memory transistor T1.
The channel region C1 of the memory transistor T1 and the channel region C2 of the selection transistor T2 correspond to the side edges of the lower gate electrode G1. Because the parts are connected to each other,
The conductivity between the memory transistor T1 and the selection transistor T2 is also good.

Moreover, in this thin film transistor memory, the lower gate electrode G1, which is the gate electrode of the memory transistor T, also serves as an electrode that shields the gate voltage applied to the semiconductor layer 3 from the lower gate electrode G2, which is the gate electrode of the selection transistor T2. In order to function, the upper gate electrode G
Since the memory transistor T1 does not malfunction due to the influence of the gate voltage applied to the gate voltage applied to the gate voltage applied to the gate voltage, the memory transistor T1 does not malfunction even though the memory transistor T1 and the selection transistor T2 are formed in one thin film transistor. Operation for stable writing, erasing,
Reading can be performed.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

That is, FIG. 3 is an equivalent circuit diagram of the thin film transistor memory, in which (a) is when writing, (b) is when erasing, (
c) shows the voltage application state during reading.

First, to explain about writing, when writing, Figure 3 (
As shown in a), the source electrode S and the drain electrode are grounded (GND), and the selection transistor T2
On-voltage V is applied to the gate electrode (upper gate electrode) G2. N
is applied, and a write voltage +vP is applied to the gate electrode (lower gate electrode) G1 of the memory transistor T. When such a voltage is applied, the two selection transistors T2
are turned on at the same time, and the write voltage +vP applied between the gate electrode G of the memory transistor T1 and the semiconductor layer 3 causes the memory transistor gate insulating film 4 to be removed from the semiconductor layer 3.
A charge is injected into the memory transistor gate insulating film 4 at the interface with the semiconductor layer 3 (memory film 4m).
), and the memory transistor T becomes a write state (off state!).

Furthermore, at the time of erasing, as shown in FIG. 3(b), the source electrode S and the drain electrode are grounded (GND), and the on-voltage V is applied to the gate electrode G2 of the selection transistor T2.
ON is applied, and the gate electrode G of the memory transistor T1 is
1, write voltage +■.

An erase voltage -vP having an opposite potential is applied. When such a voltage is applied, the two selection transistors T2 are turned on simultaneously, and the charges trapped in the memory insulating film 4 are removed by the erase voltage -vP applied between the gate electrode G1 of the memory transistor T1 and the semiconductor layer 3. is emitted into the semiconductor layer 3, and the memory transistor T becomes in an erased state (on state).

On the other hand, during reading, as shown in FIG. 3(c), the gate electrode G1 and source electrode S of the memory transistor T1 are grounded (GND), and the on-voltage VON is applied to the gate electrode G2 of the selection transistor T2. , a read voltage VD is applied to the drain electrode. When such a voltage is applied, if the memory transistor T1 is in the erase state (on state), current flows from the drain electrode to the source electrode S due to the two selection transistors T2 being turned on, and the memory transistor T1 is in the write state! ! (If it is in the OFF state, the current will not flow even if the selection transistor T2 is turned on, so read data is output depending on the presence or absence of current flowing from the source electrode S to the line portion.

Note that the thin film transistor memory of the above embodiment includes one memory transistor T1 and two selection transistors T2.
However, the present invention can also be applied to a thin film transistor memory that includes one memory transistor T1 and one selection transistor T2.

4 and 5 show a second embodiment of the present invention, in which FIG. 4 is a sectional view of a thin film transistor memory, and FIG. 5 is an equivalent circuit diagram thereof.

The thin film transistor memory of this embodiment has a memory film 4a.
A gate insulating film 4 for a memory transistor consisting of a withstand voltage film 4b is formed so as to have an area approximately half that of the semiconductor layer 3, and this gate insulating film 4 for a memory transistor is formed so as to face a half area from the center of the semiconductor layer 3. In addition, a lower gate electrode G, which is the gate electrode of the memory transistor T,
1 is formed on the gate insulating film 4 for the memory transistor in the same shape as this. That is, in the thin film transistor memory of this embodiment, the negative half is the memory transistor T1, and the other half is the selection transistor T2.
That is. Note that the thin film transistor memory of this embodiment has only one selection transistor T2, and the basic configuration is the same as that of the first embodiment.
A detailed description of the structure will be omitted by attaching the same reference numerals to the figures. Further, the thin film transistor memory of this embodiment can be manufactured by a method similar to the manufacturing method described above, and the writing and
Erasing and reading can also be performed in the same manner as in the thin film transistor memory of the first embodiment.

Note that in this embodiment, the upper gate electrode G2 is
However, since the effective part of this upper gate electrode G2 is a part that does not overlap with the lower gate electrode G1, the upper gate electrode G2 overlaps with the lower gate electrode G. The part is the lower gate electrode G
The area may be smaller than 1, and even in that case, if the side edge of the upper gate electrode G2 on the lower gate electrode G1 side overlaps the lower gate electrode G1 even slightly, the channel region C1 of the memory transistor T and the selection transistor T
Since the two channel regions C2 are connected to each other, conductivity between the memory transistor T1 and the selection transistor T2 can be ensured.

Further, in the above embodiment, the gate insulating film 4 for the memory transistor is a two-layer film consisting of the memory film 4a and the breakdown voltage film 4b. The memory transistor gate insulating film 4 may be a single-layer film made entirely of silicon nitride or the like having a charge storage function, since it is sufficient that the interface portion has a charge storage function and sufficient voltage resistance.

Further, in the above embodiment, the semiconductor layer 3 and the ohmic contact layer 2 are made of amorphous silicon, but the semiconductor layer 3 and the ohmic contact layer 2 may be made of polysilicon (poly-3i). By forming the semiconductor layer 3 and the ohmic contact layer 2 from polysilicon in this way, the operating speed of the memory transistor T1 and the selection transistor T2 can be increased.

〔Effect of the invention〕

According to the thin film transistor memory of the present invention, since the memory transistor and the selection transistor are formed in one thin film transistor, the area of the transistor memory composed of the memory transistor and the selection transistor is reduced and the degree of integration is increased. be able to. Further, in this thin film transistor memory, the portion of the semiconductor layer where the lower gate electrodes are opposed becomes the channel region of the memory transistor, and the portion where the lower gate electrodes are not opposed and only the upper gate electrodes are opposed is the channel region of the memory transistor. becomes the channel region of the selection transistor, the selection transistor can be operated by applying a gate voltage to the upper gate electrode, and the memory transistor can be operated by applying a gate voltage to the lower gate electrode. Since the channel region of the transistor and the channel region of the selection transistor are connected to each other at the portion corresponding to the side edge of the upper gate electrode, the conductivity between the memory transistor and the selection transistor is also good. . Moreover, in this thin film transistor memory, the lower gate electrode, which is the gate electrode of the memory transistor, also acts as an electrode that shields the gate voltage applied to the semiconductor layer from the upper gate electrode, which is the gate electrode of the selection transistor. Since the memory transistor does not malfunction due to the influence of the gate voltage applied to the electrode, even though the memory transistor and the selection transistor are formed in one thin film transistor, the memory transistor can operate normally and be stable. Writing, erasing, and reading can be performed.

Further, the method for manufacturing a thin film transistor memory of the present invention includes:
After forming source and drain electrodes and a semiconductor layer on an insulating substrate, a gate insulating film for a memory transistor having a charge storage function and a metal film for a lower gate electrode are sequentially deposited thereon. The gate insulating film for the memory transistor and the lower gate electrode constituting the memory transistor are simultaneously formed by patterning the gate insulating film for the memory transistor into a shape corresponding to a part of the semiconductor layer, and then the lower gate electrode and the semiconductor layer are patterned. Since a gate insulating film for a selection transistor having no charge storage function is deposited on top of the gate insulating film and an upper gate electrode is formed thereon, the thin film transistor memory of the present invention can be easily manufactured.

[Brief explanation of drawings]

1 to 3 show a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a thin film transistor memory, FIG. 2 is a manufacturing process diagram of a thin film transistor memory, and FIG. 3 is a diagram of a thin film transistor memory. It is an equivalent circuit diagram. 4 and 5 are a sectional view and an equivalent circuit diagram of a thin film transistor memory showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, S... Source electrode, D... Drain electrode, 2... Ohmic contact layer, 3... Semiconductor layer, 4... Gate insulating film for memory transistor, 4
a... Memory film, 4b... Voltage proof film, G1... Lower gate electrode, 5... Gate insulating film for selection transistor, G2... Upper gate electrode, T... Memory transistor, C1 . . . channel region, T2 . . . selection transistor, C2 . . . channel region.

Claims (2)

[Claims] (1) Source and drain electrodes formed on an insulating substrate, a semiconductor layer formed on the substrate with both sides overlapping the source and drain electrodes, and a semiconductor layer formed on a portion of this semiconductor layer. a gate insulating film for a memory transistor having a charge storage function at least at the interface with the semiconductor layer; a lower gate electrode formed on the gate insulating film for the memory transistor in the same shape as the gate insulating film; a gate insulating film for a selection transistor without a charge storage function that covers an electrode and the semiconductor layer; and a gate insulating film for a selection transistor having no charge storage function, which is formed on the gate insulating film for a selection transistor so as to face at least the entire region between the source and drain electrodes of the semiconductor layer. an upper gate electrode, a memory transistor is configured by the source and drain electrodes, the semiconductor layer, the memory transistor gate insulating film, and a lower gate electrode, the source and drain electrodes, the semiconductor layer, and the selection transistor A thin film transistor memory characterized in that a selection transistor is formed by a gate insulating film and the upper gate electrode. (2) forming source and drain electrodes on an insulating substrate; forming a semiconductor layer on the substrate with both sides overlapping the source and drain electrodes; and forming at least the semiconductor layer on the substrate. A gate insulating film for a memory transistor having a charge storage function and a metal film for a lower gate electrode are sequentially deposited at an interface with the layer, and the metal film and the gate insulating film for a memory transistor correspond to a portion of the semiconductor layer. a step of patterning into a shape; a step of depositing a gate insulating film for a selection transistor without a charge storage function on the lower gate electrode and the semiconductor layer; and a step of depositing at least one of the semiconductor layers on the gate insulating film for the selection transistor. A method for manufacturing a thin film transistor memory, comprising the steps of: forming an upper gate electrode facing the entire region between the source and drain electrodes.