KR960026900A - Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof - Google Patents

Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof Download PDF

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Publication number
KR960026900A
KR960026900A KR1019950049643A KR19950049643A KR960026900A KR 960026900 A KR960026900 A KR 960026900A KR 1019950049643 A KR1019950049643 A KR 1019950049643A KR 19950049643 A KR19950049643 A KR 19950049643A KR 960026900 A KR960026900 A KR 960026900A
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South Korea
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gate electrode
insulating film
isolation insulating
memory cell
film
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KR1019950049643A
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Korean (ko)
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겐이찌 오야마
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가네꼬 히사시
닛본덴기 가부시끼가이샤
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Publication of KR960026900A publication Critical patent/KR960026900A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

기술된 비휘발성 반도체 기억 장치는 메모리 셀부 및 주변 회로부를 가지고 있다. 메모리 셀부는 매립형 확산층(3), 부동 게이트 전극(6), 제어 게이트 전극(8) 및 제1소자 분리 절연막(4)를 가지고 있다. 주변 회로부는 각각 제2소자 분리 절연막(2)를 갖는 다수의 MOS 트랜지스터를 가지고 있다. 부동 게이트 전극은 소스/드레인 영역을 포함하는 매립형 확산층을 부분적으로 중첩한다. 제어 게이트 전극은 부동 게이트 전극을 덮으며 매립형 확산층에 직교한다. 메모리 셀부에서의 제어 게이트 전극과 평행하게 배치된 제1소자 분리 절연막은 증착된 절연막에 의해 형성되는 반면, 주변 회로부에서의 제2소자 분리 절연막은 국부 산화 공정으로부터 발생된 열 산화막에 의해 형성된다. 그 방법은 셀 어레이부에서 미세한 고밀도 산화막을 실현하며, 두께의 비균일성을 완화시키며, 매립형 확산층의 저항을 감소시킬 수 있다.The nonvolatile semiconductor memory device described has a memory cell portion and a peripheral circuit portion. The memory cell portion has a buried diffusion layer 3, a floating gate electrode 6, a control gate electrode 8, and a first device isolation insulating film 4. The peripheral circuit portion has a plurality of MOS transistors each having a second element isolation insulating film 2. The floating gate electrode partially overlaps the buried diffusion layer that includes the source / drain regions. The control gate electrode covers the floating gate electrode and is orthogonal to the buried diffusion layer. The first device isolation insulating film disposed in parallel with the control gate electrode in the memory cell portion is formed by the deposited insulating film, while the second device isolation insulating film in the peripheral circuit portion is formed by the thermal oxide film generated from the local oxidation process. The method can realize a fine high density oxide film in the cell array portion, alleviate nonuniformity of thickness, and reduce the resistance of the buried diffusion layer.

Description

가상 접지 EPROM 셀 구조를 갖는 비휘발성 반도체 기억 장치 및 그 제조 방법Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 제1실시예의 구조로 된 메모리 셀 어레이부의 도면.2 is a diagram of a memory cell array unit having the structure of the first embodiment according to the present invention.

Claims (5)

메모리 셀부 및 주변회로부를 구비한 비휘발성 반도체 기억 장치에 있어서, 상기 메모리 셀부는 소스/드레인 영역을 구성하는 매립형 확산층(3); 상기 매립형 확산층과 부분적으로 중첩되도록 형성된 부동 게이트전극(6); 상기 부동 게이트 전극을 덮고 있고, 상기 매립형 확산층과 직교하여 형성된 제어 게이트 전극(8); 및 증착된 절연막으로 구성되고 상기 제어 게이트 전극과 평행하게 배치된 제1소자 분리 절연막(4)를 포함하며, 상기 주변 회로부는 다수의 MOS 트랜지스터; 및 국부 산화 공정으로 생성된 열 산화막을 구성된 제2소자 분리 절연막(2)를 포함하는 것을 특징으로 하는 비휘발성 반도체 기억장치.A nonvolatile semiconductor memory device having a memory cell portion and a peripheral circuit portion, the memory cell portion comprising: a buried diffusion layer (3) constituting a source / drain region; A floating gate electrode 6 formed to partially overlap with the buried diffusion layer; A control gate electrode 8 covering the floating gate electrode and formed orthogonal to the buried diffusion layer; And a first device isolation insulating film 4 comprising a deposited insulating film and disposed in parallel with the control gate electrode, wherein the peripheral circuit portion comprises: a plurality of MOS transistors; And a second element isolation insulating film (2) comprising a thermal oxide film produced by a local oxidation process. 제1항에 있어서, 메모리 셀부에서의 상기 제1소자 분리 절연막은 상기 주변 회로부에서의 상기 제2소자 분리 절연막 두께의 3/4 미만의 두께를 갖는 것을 특징으로 하는 비휘발성 반도체 기억 장치.The nonvolatile semiconductor memory device according to claim 1, wherein the first device isolation insulating film in the memory cell portion has a thickness less than 3/4 of the thickness of the second device isolation insulating film in the peripheral circuit portion. 제1항에 있어서, 상기 메모리 셀부에서의 상기 제1소자 분리 절연막 상에 제공된 소거 게이트 전극(11)을 포함하며, 상기 소거 게이트 전극이 모든 제1소자 분리 절연막마다 제공되는 벼열과 상기 소거 게이트 전극이 다른 모든 제1소자 분리 절연막마다 제공되는 배열들 중 한 배열로 상기 소거 게이트 전극이 형성되는 것을 특징으로 하는 비휘발성 반도체 기억장치.The method of claim 1, further comprising an erase gate electrode (11) provided on the first device isolation insulating film in the memory cell portion, wherein the erase gate electrode is provided for every first device isolation insulating film and the erase gate electrode And the erase gate electrode is formed in one of the arrays provided for every other first element isolation insulating film. 비휘발성 반도체 기억 장치를 제조하는 방법에 있어서, 1) 국부 산화 공정에 의해 주변 회로부에 다수의 제1소자 분리 절연막(2)을 형성하는 단계; 2) 메모리 셀부에 불순물을 선택적으로 도입함으로써, 소스/드레인 영역을 구성하며 서로 평행인 다수의 매립형 확산층을 형성하는 단계; 3) 상기 메모리 셀부에 실리콘 산화막을 증착함으로써, 상기 매립형 확산층(3)과 직교하여 배치된 다수의 제2소자 분리 절연막(4)를 형성하는 단계; 4) 게이트 절연막(5)가 삽입되어 있는 반도체 기판 상에 폴리실리콘을 증착함으로써 부동 게이트 폴리실리콘막(6a)을 형성하는 단계; 및 5) 상기 게이트 절연막(5)이 삽입되어 있고 게이트 절연막(7)이 삽입된 반도체 기판상에서 형성되어 있는 상기 부동 게이트 폴리실리콘막(6a) 상에 도전막(8a)을 증착함으로써 상기 매립형 확산층에 직교 방향으로 연장하는 다수의 제어 게이트 전극(8)을 형성하고, 또한 상기 부동 게이트 폴리실리콘막(6a)을 패터닝함으로써 부동 게이트 전극(6)을 형성하는 단계를 포함하는 것을 특징으로 하는 비휘발성 반도체 기억 장치의 제조 방법.A method of manufacturing a nonvolatile semiconductor memory device, comprising: 1) forming a plurality of first element isolation insulating films (2) in a peripheral circuit portion by a local oxidation process; 2) forming a plurality of buried diffusion layers constituting a source / drain region and parallel to each other by selectively introducing impurities into the memory cell portion; 3) forming a plurality of second device isolation insulating films 4 orthogonal to the buried diffusion layer 3 by depositing a silicon oxide film on the memory cell portion; 4) forming a floating gate polysilicon film 6a by depositing polysilicon on the semiconductor substrate into which the gate insulating film 5 is inserted; And 5) depositing a conductive film 8a on the floating gate polysilicon film 6a formed on the semiconductor substrate having the gate insulating film 5 inserted therein and the gate insulating film 7 inserted therein. Forming a floating gate electrode 6 by forming a plurality of control gate electrodes 8 extending in an orthogonal direction and patterning the floating gate polysilicon film 6a. Method of manufacturing memory device. 제4항에 있어서, 단계 5) 후, 소거 게이트 전극(11)이 상기 메모리 셀부에서 상기 소자 분리 전연막(4)상의 상기 부동 게이트 전극들(6) 사이 및 상기 제어 게이트 전극들(8) 사이에 형성되게, 폴리실리콘막을 증착 및 패터닝하고, 상기 주변 회로부에서 게이트 전극(11´)을 형성하는 단계를 포함하는 것을 특징으로 하는 비휘발성 반도체 기억 장치의 제조 방법.5. The method according to claim 4, wherein after step 5) an erase gate electrode 11 is provided between said floating gate electrodes 6 and said control gate electrodes 8 on said device isolation lead film 4 in said memory cell portion. And depositing and patterning a polysilicon film to form a gate electrode (11 ') in said peripheral circuit portion. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950049643A 1994-12-15 1995-12-14 Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof KR960026900A (en)

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JP94-332815 1994-12-15
JP6332815A JP2689930B2 (en) 1994-12-15 1994-12-15 Nonvolatile semiconductor memory device and method of manufacturing the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100239701B1 (en) * 1996-10-17 2000-01-15 김영환 Method of fabricating a non-volatile memory cell

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251461A (en) 1998-02-27 1999-09-17 Nec Corp Nonvolatile semiconductor storage device and its manufacture

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* Cited by examiner, † Cited by third party
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JPH01274457A (en) * 1988-04-26 1989-11-02 Seiko Instr Inc Manufacture of semiconductor device
US5070032A (en) * 1989-03-15 1991-12-03 Sundisk Corporation Method of making dense flash eeprom semiconductor memory structures
JP2689004B2 (en) * 1989-12-15 1997-12-10 三菱電機株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100239701B1 (en) * 1996-10-17 2000-01-15 김영환 Method of fabricating a non-volatile memory cell

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JPH08167706A (en) 1996-06-25
JP2689930B2 (en) 1997-12-10

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