KR960026900A - Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof - Google Patents
Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof Download PDFInfo
- Publication number
- KR960026900A KR960026900A KR1019950049643A KR19950049643A KR960026900A KR 960026900 A KR960026900 A KR 960026900A KR 1019950049643 A KR1019950049643 A KR 1019950049643A KR 19950049643 A KR19950049643 A KR 19950049643A KR 960026900 A KR960026900 A KR 960026900A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- insulating film
- isolation insulating
- memory cell
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 7
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 238000002955 isolation Methods 0.000 claims abstract 14
- 238000009792 diffusion process Methods 0.000 claims abstract 9
- 230000002093 peripheral effect Effects 0.000 claims abstract 8
- 238000000034 method Methods 0.000 claims abstract 6
- 230000003647 oxidation Effects 0.000 claims abstract 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 5
- 229920005591 polysilicon Polymers 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 4
- 238000000059 patterning Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 238000003491 array Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
기술된 비휘발성 반도체 기억 장치는 메모리 셀부 및 주변 회로부를 가지고 있다. 메모리 셀부는 매립형 확산층(3), 부동 게이트 전극(6), 제어 게이트 전극(8) 및 제1소자 분리 절연막(4)를 가지고 있다. 주변 회로부는 각각 제2소자 분리 절연막(2)를 갖는 다수의 MOS 트랜지스터를 가지고 있다. 부동 게이트 전극은 소스/드레인 영역을 포함하는 매립형 확산층을 부분적으로 중첩한다. 제어 게이트 전극은 부동 게이트 전극을 덮으며 매립형 확산층에 직교한다. 메모리 셀부에서의 제어 게이트 전극과 평행하게 배치된 제1소자 분리 절연막은 증착된 절연막에 의해 형성되는 반면, 주변 회로부에서의 제2소자 분리 절연막은 국부 산화 공정으로부터 발생된 열 산화막에 의해 형성된다. 그 방법은 셀 어레이부에서 미세한 고밀도 산화막을 실현하며, 두께의 비균일성을 완화시키며, 매립형 확산층의 저항을 감소시킬 수 있다.The nonvolatile semiconductor memory device described has a memory cell portion and a peripheral circuit portion. The memory cell portion has a buried diffusion layer 3, a floating gate electrode 6, a control gate electrode 8, and a first device isolation insulating film 4. The peripheral circuit portion has a plurality of MOS transistors each having a second element isolation insulating film 2. The floating gate electrode partially overlaps the buried diffusion layer that includes the source / drain regions. The control gate electrode covers the floating gate electrode and is orthogonal to the buried diffusion layer. The first device isolation insulating film disposed in parallel with the control gate electrode in the memory cell portion is formed by the deposited insulating film, while the second device isolation insulating film in the peripheral circuit portion is formed by the thermal oxide film generated from the local oxidation process. The method can realize a fine high density oxide film in the cell array portion, alleviate nonuniformity of thickness, and reduce the resistance of the buried diffusion layer.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 제1실시예의 구조로 된 메모리 셀 어레이부의 도면.2 is a diagram of a memory cell array unit having the structure of the first embodiment according to the present invention.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP94-332815 | 1994-12-15 | ||
JP6332815A JP2689930B2 (en) | 1994-12-15 | 1994-12-15 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960026900A true KR960026900A (en) | 1996-07-22 |
Family
ID=18259117
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950049643A KR960026900A (en) | 1994-12-15 | 1995-12-14 | Nonvolatile semiconductor memory device having virtual ground EPROM cell structure and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2689930B2 (en) |
KR (1) | KR960026900A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100239701B1 (en) * | 1996-10-17 | 2000-01-15 | 김영환 | Method of fabricating a non-volatile memory cell |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11251461A (en) | 1998-02-27 | 1999-09-17 | Nec Corp | Nonvolatile semiconductor storage device and its manufacture |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01274457A (en) * | 1988-04-26 | 1989-11-02 | Seiko Instr Inc | Manufacture of semiconductor device |
US5070032A (en) * | 1989-03-15 | 1991-12-03 | Sundisk Corporation | Method of making dense flash eeprom semiconductor memory structures |
JP2689004B2 (en) * | 1989-12-15 | 1997-12-10 | 三菱電機株式会社 | Semiconductor device |
-
1994
- 1994-12-15 JP JP6332815A patent/JP2689930B2/en not_active Expired - Lifetime
-
1995
- 1995-12-14 KR KR1019950049643A patent/KR960026900A/en active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100239701B1 (en) * | 1996-10-17 | 2000-01-15 | 김영환 | Method of fabricating a non-volatile memory cell |
Also Published As
Publication number | Publication date |
---|---|
JP2689930B2 (en) | 1997-12-10 |
JPH08167706A (en) | 1996-06-25 |
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A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
NORF | Unpaid initial registration fee |