JP2887506B2 - Thin film transistor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor memory.

[Conventional technology]

Recently, E ² PROM that can be electrically written, erased, and read
For example, a thin film transistor memory in which a memory transistor and a selection transistor for selecting the memory transistor are used as a thin film transistor is considered.

Conventionally, as this thin film transistor memory, a thin film transistor for memory (hereinafter, referred to as a memory transistor) and a thin film transistor for selection (hereinafter, referred to as a selection transistor) are formed adjacently on an insulating substrate made of glass or the like. It is known that a transistor and a selection transistor are connected in series via a connection line connecting one source electrode and the other drain electrode to form a transistor memory. Note that the memory transistor and the selection transistor are, for example, coplanar thin film transistors in which a semiconductor layer, source and drain electrodes, a gate insulating film, and a gate electrode are stacked. It is formed of a memory insulating film having a storage function, and the gate insulating film of the select transistor is formed of an insulating film having no charge storage function.

[Problems to be solved by the invention]

However, in the conventional thin film transistor memory, a memory transistor and a select transistor are formed adjacent to each other on a substrate, and the memory transistor and the select transistor are connected in series by a connection wiring. There is a problem that the area of a transistor memory including transistors is large, and it is difficult to increase the degree of integration of a memory matrix formed by arranging the transistor memories vertically and horizontally.

The present invention has been made in view of such circumstances, and an object of the present invention is to reduce the area of a transistor memory including a memory transistor and a selection transistor, thereby increasing the degree of integration. To provide memory.

[Means for solving the problem]

The thin film transistor memory according to the present invention includes a memory gate insulating film formed substantially at the center of a semiconductor layer, a memory gate electrode formed on the memory gate insulating film, and a portion facing the memory gate electrode. Source and drain electrodes formed in regions on both sides separated from each other, the memory gate electrode, and a gate insulating film formed to cover the semiconductor layer between the memory gate electrode and the source and drain electrodes; A gate electrode for a memory; and a gate electrode for a select transistor formed on the gate insulating film corresponding to between the memory gate electrode and the source and drain electrodes.

As described above, when the memory gate electrode and the select transistor gate electrode corresponding to the area between the memory gate electrode and the source and drain electrodes are formed on the gate insulating film, the memory gate electrode and the select transistor gate electrode are the same. In the case where the gate electrodes are formed side by side, a portion for separating both gate electrodes becomes unnecessary, and the area can be reduced accordingly.

In such a structure, since the memory gate electrode shields the electric field applied to the semiconductor layer from the selection transistor gate electrode, no problem of malfunction occurs.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 to 3 show a first embodiment of the present invention. FIG. 1 is a sectional view of a thin film transistor memory.

The structure of this thin film transistor memory will be described. In the figure, reference numeral 1 denotes an insulating substrate made of glass or the like.
On top, a semiconductor layer 2 made of i-type amorphous silicon (ia-Si) is formed in a predetermined shape. The thickness of the semiconductor layer 2 is 1000 °. Source and drain electrodes S and D are formed on both sides of the semiconductor layer 2 via an ohmic contact layer 3 made of n-type amorphous silicon (n ⁺ -a-Si). The line portions (not shown) of the source and drain electrodes S and D are formed on the substrate 1, and the ohmic contact layer 3 is formed under the line portions over the entire length. . The semiconductor layer 2
A gate insulating film 4 for a memory transistor is provided on the central portion of. The memory transistor gate insulating film 4 is provided with a memory insulating film 4 having a charge storage function. The memory insulating film 4 is formed on the semiconductor layer 2 and has a thickness of 100 Å. And a pressure-resistant film 4b with a thickness of 900 mm laminated thereon. The memory film 4a and the pressure-resistant film 4b are formed in the same shape. Each of the memory film 4a and the withstand voltage film 4b is a silicon nitride (SiN) film. The withstand voltage film 4b has a stoichiometric ratio of the composition ratio (Si / N) of silicon atoms Si and nitrogen atoms N. The memory film 4 is formed of silicon nitride having a charge storage function with a silicon atomic weight greater than the stoichiometric ratio and having a charge storage function. The width of the lower gate electrode 4 composed of the memory film 4a and the withstand voltage film 4b is approximately one-third the width between the source and drain electrodes S and D in FIG. Are formed in an area substantially equal to the width of the semiconductor layer 2. Further, on the memory transistor gate insulating film 4 is lower gate electrode G ₁ of the same shape and which are formed, (not shown) the line portions are wired on the substrate 1. Incidentally, the memory transistor gate insulating film 4 is also formed over its entire length below the line portion of the lower gate electrode G _1. 5 is a selection transistor gate insulating film formed on the substrate 1 to cover the lower gate electrode G ₁ and the line portion and the semiconductor layer 2, the select transistor gate insulating film 5, no charge accumulation function It is formed of silicon nitride. The thickness of the gate insulating film 5 for the select transistor is 2000 °. Then, on the selection transistor gate insulating film 5, at least the source of the semiconductor layer 2, the drain electrode S, (not shown) to face the entire region and the line section the upper gate electrode G ₂ between D Are formed. In this embodiment, the upper gate electrode G _2, the semiconductor layer 2 slightly smaller than, and is both side edges are formed in the area facing the central portion of the source electrode S and the drain electrode D. The line portion of the upper gate electrode G ₂ is, is formed in a position that does not overlap vertically and the lower gate electrode G _1.

The central portion of the thin film transistor memory in this embodiment is a memory transistors T _1, both sides thereof are respectively selected transistor T _2, the memory transistors T ₁ includes a semiconductor layer 2, a source, a drain electrode S, D and
A memory transistor gate insulating film 5 having a memory film 4a having a charge storage function at an interface with the semiconductor layer 2;
It is composed of a lower gate electrode G _1. Further, each on both sides of the memory transistors T ₁ is selected transistor G ₂
Are as, the selection transistor G ₂ is, the semiconductor layer 2 and the source, drain electrodes S, and D, and the selection transistor gate insulating film 5, and an upper gate electrode G _2. The memory transistors T ₁ and two select transistors T ₂ of the both sides are connected in series through the semiconductor layer 2 which is also used in both. That is,
Wherein in the region between the source electrode S and the drain electrode D of the semiconductor layer 2, the portion where the lower gate electrode G ₁ is facing the next channel area C ₁ of the entire memory transistor T _1, the lower gate electrode G ₁ is a portion only the upper gate electrode G ₂ without opposing faces its entire selection transistor T ₂
Has become a channel region C _2, a channel region C ₁ of the memory transistor T _1, the channel region G ₂ of the select transistor T _2, were connected to each other at the portion corresponding to the side edge of the lower gate electrode G ₁ because it is formed in a state, the memory transistors T ₁ and two select transistors T ₂ of the both sides, the channel region G ₁ of the semiconductor layer 2,
Through G _2, it is connected in series with good conductivity. The memory transistor two select transistors T ₂ of the two sides of T _1, since the gate electrode (upper gate electrode) G ₂ is a common electrode, on the same time, so as to off operation.

FIG. 2 shows a method of manufacturing the thin film transistor memory. The thin film transistor memory is manufactured by the following steps.

First, as shown in FIG. 2A, a semiconductor layer 2 is formed on a substrate 1 in a predetermined shape. The semiconductor layer 2 is formed by depositing i-type amorphous silicon to a thickness of 1000 ° on the substrate 1 and patterning the i-type amorphous silicon layer.

Next, as shown in FIG. 2 (b), an ohmic contact layer 3 and source and drain electrodes S and D are formed on both sides of the semiconductor layer 2 and, at the same time, a source is formed on the substrate 1. , And the line portions of the drain electrodes S and D are formed. The source and drain electrodes S and D, their line portions, and the ohmic contact layer 3 are formed by sequentially depositing n-type amorphous silicon and a metal such as chromium on the substrate 1 to a thickness of 250 or 500 mm. And an n-type amorphous silicon layer are formed by patterning the source and drain electrodes S and D and their line portions.

Next, as shown in FIG. 2 (c), a memory film (a silicon nitride film having a charge storage function) 4a to be a gate insulating film 4 for a memory transistor and a breakdown voltage film (without a charge storage function) are formed on the substrate 1. A silicon nitride film) 4b is deposited to a thickness of 100 ° and 900 °, and a lower gate electrode metal film M such as chromium is deposited thereon to a thickness of 500 °.

Next, as shown in FIG. 2D, the metal film M
And a memory transistor gate insulating film 4 comprising a memory film 4a and the breakdown voltage layer 4b, is patterned in a shape corresponding to the central portion of the semiconductor layer 2, the lower gate electrode G ₁ consisting of the metal film M and the line section Then, the memory transistor gate insulating film 4 having the same shape as the above is completed.

Next, as shown in FIG. 2 (e), said on the lower gate electrode G ₁ and the semiconductor layer 2, over the entire surface of the substrate 1, select transistor gate insulating film (not silicon nitride film charge storage function) 5 was deposited to a thickness of 2000Å and then on the selection transistor gate insulating film 5, a metal such as chromium, it is deposited to a thickness of 1000Å and the upper gate electrode G ₂ in a manner of patterning the metal film By forming the line portion, the above-described thin film transistor memory is completed.

That is, the thin film transistor memory of this embodiment is:
The one thin film transistor, at least the source of the semiconductor layer 2, the drain electrode S, an upper gate electrode G ₂ facing the entire region between D, the semiconductor provided between the upper gate electrode G ₂ and the semiconductor layer 2 provided with two gate electrodes and lower gate electrodes G ₁ facing the central portion of the layer 2,
The lower gate electrode G ₁ is provided on the central portion of the semiconductor layer 2, formed in the same shape and which exists on the memory transistor gate insulating film 4 having a charge accumulation function in the interface portion between the semiconductor layer 2 and, an upper gate electrode G ₂ is, by forming on the lower gate electrode G ₁ of the semiconductor layer without the selection transistor of the charge storage function laminated on the second gate insulating film 5 covering, of one thin film transistor during the semiconductor layer 2 and the source, drain electrodes S, the memory transistors T ₁ and the selection transistor T ₂ and the semiconductor layer 2 that share the D
Are formed in a state of being connected in series.

According to the thin film transistor memory, select in one of the thin film transistor, and the memory transistors T _1, because they form two selection transistors T ₂ located on both sides of the memory transistors T _1, and the memory transistors T ₁ it can be increased the degree of integration by reducing the area of the transistor memory composed of a transistor T _2.

Then, in the thin film transistor memory, wherein the semiconductor layer 2, part becomes the channel region C ₁ of the memory transistors T ₁ to the lower gate electrode G ₁ is facing, the lower gate electrode G ₁ is upper gate not facing Electrode G ₂
Since the portion only is opposed a channel region C ₂ of the select transistor T _2, to operate the selection transistor T ₂ by application of a gate voltage to the upper gate electrode G _2, the gate voltage of the lower gate electrode G ₁ by the application it is possible to operate the memory transistor T _1. Further, since the formed by wrapping the upper gate electrode G ₂ is a gate electrode of the select transistor T ₂ to the lower gate electrode G ₁ is the gate electrode of the memory transistor T _1, the memory transistor
A channel region C ₁ of T ₁ and the channel region C ₂ of the select transistor T ₂ are, from being formed in a state of mutually connected at the portion corresponding to the side edge of the lower gate electrode G _1,
Continuity between the memory transistors T ₁ and the selection transistor T ₂ is also good.

Moreover, in the thin film transistor memory, a lower gate electrode G ₁ is the gate electrode of the memory transistor T _1,
Lower gate electrode is the gate electrode of the select transistor T ₂
To act as an electrode for shielding the gate voltage applied from the G ₂ to the semiconductor layer 2, since the memory transistor T ₁ is never malfunction under the influence of the gate voltage applied to the upper gate electrode G _2, 1 one while is obtained by forming the memory transistors T ₁ and selection transistor T ₂ in the thin film transistor, the memory transistors T ₁ is operated normally stable write, erase, can be read.

Writing, erasing, and reading of this thin film transistor memory are performed as follows.

That is, FIG. 3 is an equivalent circuit diagram of the thin film transistor memory, in which (a) is for writing, (b) is for erasing,
(C) shows a voltage application state at the time of reading.

First, the writing will be described, upon writing, as shown in FIG. 3 (a), as well as ground (GND) and the source electrode S and the drain electrode D, a gate electrode (upper gate electrode) of the select transistor T ₂ G ₂ to apply the oN voltage V _oN, and applies the write voltage + V _P to the gate electrode (the lower gate electrode) G ₁ of the memory transistor T _1. The application of such a voltage, the two select transistors T ₂ is turned on at the same time, the gate electrode G ₁ of the memory transistors T ₁ and the semiconductor layer 2
Such write voltage + V _P charges from the semiconductor layer 2 to the memory transistor gate insulating film 4 by is injected, the interface (memory film 4a of the charge and the semiconductor layer 2 of the memory transistor gate insulating film 4 between the ) Trapped in
Memory transistor T ₁ is in writing state (OFF state).

The erasing, as shown in FIG. 3 (b), while grounding the source electrode S and the drain electrode D (GND), the ON voltage V _ON to the gate electrode G ₂ of the select transistor T ₂
It was applied to the gate electrode G ₁ of the memory transistor T _1, and the write voltage + V _P applies an erase voltage -V _P opposite potential. When such a voltage is applied, two selection transistors T ₂
Are simultaneously turned on, and the gate electrode G ₁ of the memory transistor T ₁ is turned on.
And the charge trapped in the memory insulating film 4 by an erase voltage -V _P applied between the semiconductor layer 2 is discharged to the semiconductor layer 2, the memory transistors T ₁ is erased state (ON state).

On the other hand, during reading, as shown in FIG. 3 (c), with grounding the gate electrode G ₁ and the source electrode S of the memory transistor T ₁ (GND), the gate electrode G ₂ to the ON voltage of the select transistor T ₂ V _ON is applied, and a read voltage V _D is applied to the drain electrode D. The application of such a voltage, if the memory transistor T ₁ is in the erased state (ON state), 2
The drain electrode D is turned on by turning on the _two selection transistors T2.
Current flows to the source electrode S of and, if the memory transistor T ₁ is in the write state (off state), since the selecting transistor T ₂ the current is also turned on does not flow, flows through the line section from the source electrode S Read data according to the presence or absence of the current is output.

Incidentally, the thin film transistor memory of the embodiment, which was provided with a single memory transistors T ₁ and two select transistors T _2, the present invention comprises one memory transistors T ₁ and one selection transistor T ₂ It can also be applied to thin film transistor memories.

4 and 5 show a second embodiment of the present invention. FIG. 4 is a sectional view of a thin film transistor memory, and FIG.
The figure is an equivalent circuit diagram.

The thin film transistor memory according to this embodiment includes a memory film 4a
The gate insulating film 4 for a memory transistor, which is made up of a gate insulating film 4 and a breakdown voltage film 4b, is formed to have a half area of the semiconductor layer 2, and the gate insulating film 4 for a memory transistor is opposed to a half area from the center of the semiconductor layer 2. together, and forming a lower gate electrode G ₁ is the gate electrode of the memory transistors T ₁ into the same shape as this on the memory transistor gate insulating film 4. That is, a thin film transistor memory of this embodiment, and an half the memory transistors T _1, is obtained by a selection transistor T ₂ the other half. Incidentally, the thin film transistor memory of this embodiment, only by one of the selection transistors T _2, since the basic configuration unchanged from the first embodiment, detailed description of the structure are denoted by the same reference numerals in FIG. Omitted. Further, the thin film transistor memory of this embodiment can be manufactured by the same method as the above-described manufacturing method, and writing, erasing, and reading can be performed in the same manner as the thin film transistor memory of the first embodiment.

In this embodiment, the upper gate electrode G ₂ first
Although formed in the same area as of Example, since the effective portion of the upper gate electrode G ₂ is a portion that is not wrapped and the lower gate electrode G _1, the lower gate electrode G ₁ of the upper gate electrode G ₂ the wrapping portion may be G ₁ is smaller than the area under the gate electrode, even in which case the lower gate electrode G ₁ of the side edge of the lower gate electrode G ₁ side even slightly the upper gate electrode G ₂
Between if so wrapped, because the channel area C ₁ of the memory transistors T ₁ and the channel region C ₂ of the select transistor T ₂ is formed in a state of mutually connected, and the memory transistors T ₁ and the selection transistor T ₂ Can be secured.

Further, in the above-described embodiment, the memory transistor gate insulating film 4 is a two-layer film of the memory film 4a and the breakdown voltage film 4b, but the memory transistor gate insulating film 4 has at least an interface portion with the semiconductor layer 2. The gate insulating film 4 for a memory transistor may be a single-layer film made of silicon nitride or the like having a charge storage function as a whole, as long as it has a charge storage function and a sufficient withstand voltage.

Further, in the above embodiment, the semiconductor layer 2 and the ohmic contact layer 3 are formed of amorphous silicon. However, the semiconductor layer 2 and the ohmic contact layer 3 may be formed of poly silicon (poly-Si). thus the semiconductor layer 2 and the ohmic contact layer 3 be formed of polysilicon, it is possible to increase the operating speed of the memory transistors T ₁ and selection transistor T _2.

〔The invention's effect〕

According to the thin film transistor memory of the present invention, the memory gate electrode and the select transistor gate electrode corresponding to the memory gate electrode and the source / drain electrode are formed on the gate insulating film. When the transistor gate electrodes are formed side by side on the same plane, a portion for separating the two gate electrodes becomes unnecessary, and the area can be reduced accordingly.

[Brief description of the drawings]

1 to 3 show a first embodiment of the present invention. FIG. 1 is a sectional view of a thin film transistor memory, FIG. 2 is a manufacturing process diagram of the thin film transistor memory, and FIG. It is an equivalent circuit diagram. FIGS. 4 and 5 are a sectional view and an equivalent circuit diagram of a thin film transistor memory showing a second embodiment of the present invention. 1 ... substrate, 2 ... semiconductor layer, 3 ... ohmic contact layer, S ... source electrode, D ... drain electrode, 4 ... memory transistor gate insulating film, 4a ... memory film, 4b ... withstand voltage layer, G ₁ ... lower gate electrode 5, a gate insulating film for a select transistor, G _{2, an} upper gate electrode, T _{1, a} memory transistor, C _{1, a} channel region, T _{2, a} select transistor, C _2,
Channel area.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27 / 115,29 / 786

Claims (1)

(57) [Claims] A memory gate insulating film formed substantially at a central portion of the semiconductor layer; a memory gate electrode formed on the memory gate insulating film; and a memory gate electrode separated from an opposing portion of the memory gate electrode. A source and drain electrode formed in both side regions, the memory gate electrode, and a gate insulating film formed to cover the semiconductor layer between the memory gate electrode and the source and drain electrodes; A thin film transistor memory comprising: a gate electrode; and a gate electrode for memory, and a gate electrode for a selection transistor formed on the gate insulating film between the source and drain electrodes.