JPH0468778B2 - - Google Patents

Info

Publication number
JPH0468778B2
JPH0468778B2 JP62179084A JP17908487A JPH0468778B2 JP H0468778 B2 JPH0468778 B2 JP H0468778B2 JP 62179084 A JP62179084 A JP 62179084A JP 17908487 A JP17908487 A JP 17908487A JP H0468778 B2 JPH0468778 B2 JP H0468778B2
Authority
JP
Japan
Prior art keywords
chip
fpc
base plate
solder
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62179084A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6423543A (en
Inventor
Katsumichi Ueyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62179084A priority Critical patent/JPS6423543A/ja
Publication of JPS6423543A publication Critical patent/JPS6423543A/ja
Publication of JPH0468778B2 publication Critical patent/JPH0468778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP62179084A 1987-07-20 1987-07-20 Soldering by use of laser Granted JPS6423543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179084A JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179084A JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Publications (2)

Publication Number Publication Date
JPS6423543A JPS6423543A (en) 1989-01-26
JPH0468778B2 true JPH0468778B2 (de) 1992-11-04

Family

ID=16059801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179084A Granted JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Country Status (1)

Country Link
JP (1) JPS6423543A (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02247076A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd レーザはんだ付け装置
JP2601102B2 (ja) * 1992-05-08 1997-04-16 松下電器産業株式会社 Ic部品のリード接合方法
DE102004038401B4 (de) * 2003-10-14 2017-07-06 Conti Temic Microelectronic Gmbh Verfahren zum Verbinden eines flexiblen Flachleiters mit einer Leiterplatte
JP2007243005A (ja) * 2006-03-10 2007-09-20 Ricoh Microelectronics Co Ltd 電極接合方法及びその装置
JP6124758B2 (ja) * 2013-10-07 2017-05-10 株式会社ミマキエンジニアリング 圧力緩衝器の製造方法
JP7406911B2 (ja) * 2019-12-25 2023-12-28 株式会社ディスコ レーザーリフロー装置、及び、レーザーリフロー方法

Also Published As

Publication number Publication date
JPS6423543A (en) 1989-01-26

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term