JPH0463647U - - Google Patents
Info
- Publication number
- JPH0463647U JPH0463647U JP1990106802U JP10680290U JPH0463647U JP H0463647 U JPH0463647 U JP H0463647U JP 1990106802 U JP1990106802 U JP 1990106802U JP 10680290 U JP10680290 U JP 10680290U JP H0463647 U JPH0463647 U JP H0463647U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- attached
- back surface
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000017525 heat dissipation Effects 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
第１図はこの考案の一実施例である高周波混成
集積回路の半導体チツプを取付けた部分の斜視図
、第２図は第１図の−線における断面図、第
３図は従来の高周波混成集積回路の半導体チツプ
を銅ブロツクに取付けた部分の斜視図、第４図は
第３図の−線における断面図である。 図において、１は基板、３は半導体チツプ、４
は回路パターン、６は放熱フイン、６ａは断面コ
の字部、７はワイヤを示す。なお、図中、同一符
号は同一、又は相当部分を示す。
集積回路の半導体チツプを取付けた部分の斜視図
、第２図は第１図の−線における断面図、第
３図は従来の高周波混成集積回路の半導体チツプ
を銅ブロツクに取付けた部分の斜視図、第４図は
第３図の−線における断面図である。 図において、１は基板、３は半導体チツプ、４
は回路パターン、６は放熱フイン、６ａは断面コ
の字部、７はワイヤを示す。なお、図中、同一符
号は同一、又は相当部分を示す。
Claims (1)
- 基板表面に回路パターンを、基板裏面に接地パ
ターンを備え、前記基板裏面に放熱フインが取付
けられ、前記基板表面に裏面を共通端子又は、絶
縁された半導体が取付けられる高周波混成集積回
路において、前記放熱フインの一部を断面コの字
形に形成しこの断面コの字形の部分を基板表面に
出し、この断面コの字形の部分に半導体を取付け
たことを特徴とする高周波混成集積回路。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990106802U JPH0463647U (ja) | 1990-10-09 | 1990-10-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990106802U JPH0463647U (ja) | 1990-10-09 | 1990-10-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463647U true JPH0463647U (ja) | 1992-05-29 |
Family
ID=31853040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990106802U Pending JPH0463647U (ja) | 1990-10-09 | 1990-10-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463647U (ja) |
-
1990
- 1990-10-09 JP JP1990106802U patent/JPH0463647U/ja active Pending