JPH0474443U - - Google Patents
Info
- Publication number
- JPH0474443U JPH0474443U JP1990117916U JP11791690U JPH0474443U JP H0474443 U JPH0474443 U JP H0474443U JP 1990117916 U JP1990117916 U JP 1990117916U JP 11791690 U JP11791690 U JP 11791690U JP H0474443 U JPH0474443 U JP H0474443U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- ceramic
- semiconductor element
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
第１図はこの考案の一実施例である高周波高出
力用混成集積回路装置の実装後の斜視図、第２図
は第１図の展開斜視図、第３図は従来の高周波高
出力用混成集積回路装置の実装後の斜視図である
。 図において、１は厚膜回路基板、４は半導体素
子、５は金属細線、６はセラミツクＡ、７はセラ
ミツクＢ、８，９は厚膜回路基板１上のメタライ
ズ部を示す。なお、図中、同一符号は同一、また
は相当部分を示す。
力用混成集積回路装置の実装後の斜視図、第２図
は第１図の展開斜視図、第３図は従来の高周波高
出力用混成集積回路装置の実装後の斜視図である
。 図において、１は厚膜回路基板、４は半導体素
子、５は金属細線、６はセラミツクＡ、７はセラ
ミツクＢ、８，９は厚膜回路基板１上のメタライ
ズ部を示す。なお、図中、同一符号は同一、また
は相当部分を示す。
Claims (1)
- 混成集積回路基板上に搭載された半導体素子放
熱用のセラミツクと、半導体素子のアース電極を
電気的に接続するためのセラミツクとを一体化し
て接合したことを特徴とする混成集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990117916U JPH0474443U (ja) | 1990-11-07 | 1990-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990117916U JPH0474443U (ja) | 1990-11-07 | 1990-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474443U true JPH0474443U (ja) | 1992-06-30 |
Family
ID=31865813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990117916U Pending JPH0474443U (ja) | 1990-11-07 | 1990-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474443U (ja) |
-
1990
- 1990-11-07 JP JP1990117916U patent/JPH0474443U/ja active Pending