JPH0463282U - - Google Patents
Info
- Publication number
- JPH0463282U JPH0463282U JP10473990U JP10473990U JPH0463282U JP H0463282 U JPH0463282 U JP H0463282U JP 10473990 U JP10473990 U JP 10473990U JP 10473990 U JP10473990 U JP 10473990U JP H0463282 U JPH0463282 U JP H0463282U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- conductive pattern
- pad
- main body
- device main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Description
第1図は、本考案の一実施例を示すICカード
の要部断面図、第2図は、従来技術を説明するた
めのICカードの要部断面図、第3図は、各ボン
デイングを行うのに必要な高さを説明するための
模式的な側面図である。 1……カード本体、2……表面シート、3……
裏面シート、4……半導体チツプ、5……開口部
、6……絶縁性フイルム基板、7……銅箔の導体
パターン、10……透孔、11……ボール。
の要部断面図、第2図は、従来技術を説明するた
めのICカードの要部断面図、第3図は、各ボン
デイングを行うのに必要な高さを説明するための
模式的な側面図である。 1……カード本体、2……表面シート、3……
裏面シート、4……半導体チツプ、5……開口部
、6……絶縁性フイルム基板、7……銅箔の導体
パターン、10……透孔、11……ボール。
Claims (1)
- 【実用新案登録請求の範囲】 半導体チツプを上記半導体チツプが設けられる
装置本体上に取り付ける構造において、 上記装置本体上に形成された収納用凹部と、 上記収納用凹部に配された半導体チツプの上面
を被うようにして上記装置本体上に被着された絶
縁性フイルムと、 上記半導体チツプ上に形成されている複数のパ
ツドの真上にそれぞれ位置するようにして所定の
配列で上記絶縁性フイルム上に形成された導体パ
ターンと、 上記パツドの真上において上記絶縁性フイルム
基板および上記導体パターンを貫通するようにし
て形成された透孔と、 上記透孔を介して上記パツドと上記導体パター
ンとを接続するボールボンデイングにより設けら
れたボールとを具備することを特徴とする半導体
チツプの取付け構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10473990U JPH0463282U (ja) | 1990-10-04 | 1990-10-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10473990U JPH0463282U (ja) | 1990-10-04 | 1990-10-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0463282U true JPH0463282U (ja) | 1992-05-29 |
Family
ID=31850139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10473990U Pending JPH0463282U (ja) | 1990-10-04 | 1990-10-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0463282U (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58209133A (ja) * | 1982-05-14 | 1983-12-06 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | 電気接続方法及びそれを利用する個人カ−ド |
JPS633422A (ja) * | 1986-06-23 | 1988-01-08 | Ricoh Co Ltd | Icチツプの実装方法 |
-
1990
- 1990-10-04 JP JP10473990U patent/JPH0463282U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58209133A (ja) * | 1982-05-14 | 1983-12-06 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | 電気接続方法及びそれを利用する個人カ−ド |
JPS633422A (ja) * | 1986-06-23 | 1988-01-08 | Ricoh Co Ltd | Icチツプの実装方法 |