JPH046105B2 - - Google Patents
Info
- Publication number
- JPH046105B2 JPH046105B2 JP57049121A JP4912182A JPH046105B2 JP H046105 B2 JPH046105 B2 JP H046105B2 JP 57049121 A JP57049121 A JP 57049121A JP 4912182 A JP4912182 A JP 4912182A JP H046105 B2 JPH046105 B2 JP H046105B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- elements
- output pins
- integrated circuit
- wiring substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000017525 heat dissipation Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 8
- 230000032683 aging Effects 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
Description
【発明の詳細な説明】
発明の対象
本発明は複数個の集積回路素子を搭載した回路
アセンブリに関し、特に異種類の素子を高密度に
搭載するに好適な回路アセンブリに関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a circuit assembly equipped with a plurality of integrated circuit elements, and particularly to a circuit assembly suitable for mounting different types of elements at high density.
従来技術
複数個の集積回路素子を一枚の配線基板に搭載
し高い実装密度を有する回路アセンブリを実現す
ることは、装置の実装密度を向上するのに有効な
手段である。また、回路アセンブリとして独立し
た実装階層を有することで、生産あるいは保守の
面から見ても有益な手段である。Prior Art Mounting a plurality of integrated circuit elements on a single wiring board to realize a circuit assembly with high packaging density is an effective means for improving the packaging density of a device. Furthermore, having an independent mounting hierarchy as a circuit assembly is an advantageous means from the viewpoint of production or maintenance.
上述の如き回路アセンブリを実現する方法とし
ては、セラミツク配線基板に複数個の集積回路素
子をチツプ状態で銀ペーストあるいはAuSi共晶
等を用いたダイボンド手段により装着し、ワイヤ
ボンドにより電気的接続を得る方法、あるいはセ
ラミツク配線基板にチツプキヤリア等の回路パツ
ケージにあらかじめ格納された個別の集積回路素
子を複数個搭載する方法等が知られている。 A method for realizing the above-mentioned circuit assembly is to attach a plurality of integrated circuit elements in chip form to a ceramic wiring board by die-bonding means using silver paste or AuSi eutectic, etc., and to obtain electrical connections by wire bonding. A known method is to mount a plurality of individual integrated circuit elements preliminarily stored in a circuit package such as a chip carrier onto a ceramic wiring board.
しかし、従来の方法では生産性や実装密度の面
で問題があつた。すなわち、多数の素子をダイボ
ンドにより配線基板に直接装着する方法において
は、チツプ状態では素子の電気特性を十分に検査
できないことや一旦装着されたチツプを除去し再
装着することが難しいために、回路アセンブリと
しての歩留りが著しく悪くなる欠点がある。ま
た、チツプキヤリア等を搭載する方法では、個々
の素子の電気特性の検査やエージングが基板に搭
載する前にあらかじめできる利点があるが、チツ
プに比べ外形が大きいために配置の自由度が低い
ことや論理素子等の入出力ピンが多い素子ではパ
ツケージ外形が著しく大きくなるために、実装密
度が十分に向上しない欠点がある。 However, conventional methods have had problems in terms of productivity and packaging density. In other words, in the method of directly attaching a large number of elements to a wiring board using die bonding, the electrical characteristics of the elements cannot be sufficiently inspected in the chip state, and it is difficult to remove and reattach the chip once it has been attached. There is a drawback that the yield as an assembly is significantly reduced. In addition, the method of mounting chip carriers has the advantage that the electrical characteristics and aging of individual elements can be inspected and aged before mounting them on the board, but since the external dimensions are larger than chips, there is less freedom in placement. Elements with a large number of input/output pins, such as logic elements, have a drawback that the packaging density is not sufficiently improved because the package size becomes significantly large.
また、従来では、記憶素子と論理素子は分離し
て実装するのが一般的であつた。これは、素子の
集積度が低く一定の機能を実現するのに相当数の
素子が必要であり、また素子の動作速度が遅く素
子間の伝播時間が２次的な問題であつたためであ
る。しかるに、近年における半導体素子の高集積
化と高速化に伴い、素子間の伝播時間が装置全体
の速度を決める上で高い割合を占めるようになつ
てきた。このため記憶素子と論理素子を単一モジ
ユール上に混在して高密度に実装する必要が生じ
てきた。 Furthermore, conventionally, it has been common to separately mount storage elements and logic elements. This is because the degree of integration of the elements is low and a considerable number of elements are required to realize a certain function, and the operation speed of the elements is slow and the propagation time between elements is a secondary problem. However, as semiconductor devices have become more highly integrated and faster in recent years, the propagation time between devices has come to occupy a high proportion in determining the speed of the entire device. For this reason, it has become necessary to mix memory elements and logic elements on a single module and package them at high density.
多数の素子をダイボンドにより配線基板に直接
装着する方法では著しく歩留りが悪い。また、論
理素子は一般に入出力ピンが多くチツプキヤリア
化した場合に外形が著しく大きくなり実装密度の
低下を招く欠点がある。 The method of directly attaching a large number of elements to a wiring board by die bonding has a significantly poor yield. In addition, logic elements generally have a drawback that when they are made into chip carriers with many input/output pins, their external dimensions become significantly large, resulting in a reduction in packaging density.
第１図Ａ，Ｂは回路アセンブリを示し、Ａは平
面図、ＢはＡのＡ−A′線断面図である。図にお
いて、１はセラミツク多層配線基板、２はその端
子ピン、３は予めチツプキヤリア化された記憶素
子、４は論理素子チツプである。 1A and 1B show a circuit assembly, with A being a plan view and B being a sectional view taken along line A-A' of A. In the figure, 1 is a ceramic multilayer wiring board, 2 is a terminal pin thereof, 3 is a memory element which has been made into a chip carrier in advance, and 4 is a logic element chip.
本回路アセンブリは以下の手順により作成され
る。すなわち、まず、セラミツク多層配線基板１
の中央に、論理素子チツプ４がAuSi共晶を用い
たダイボンド技術により装着される。次いで、前
記基板１とチツプ４との間に電気的な接続を得る
ためにワイヤボンドが施こされ、更に、保護のた
めにキヤツプ５により気密封止される。しかる
後、予めチツプキヤリア化された記憶素子３が周
囲に搭載される。 This circuit assembly is created by the following steps. That is, first, the ceramic multilayer wiring board 1
A logic element chip 4 is attached to the center of the structure by die bonding technology using AuSi eutectic. Next, wire bonding is performed to obtain an electrical connection between the substrate 1 and the chip 4, and the cap 5 is hermetically sealed for protection. Thereafter, the memory element 3, which has been made into a chip carrier in advance, is mounted around it.
回路アセンブリによれば、多数の入出力ピンを
有する論理素子が占める面積をキヤツプの大きさ
で定まる範囲に抑えることができる。また、封止
後に従来のパツケージと同様に電気的な検査やエ
ージングが可能であり十分な選別ができる。従つ
て、上記選別後に別途選別されたチツプキヤリア
化記憶素子を搭載すればよく、高い歩留りが確保
できる。 According to the circuit assembly, the area occupied by a logic element having a large number of input/output pins can be suppressed within a range determined by the size of the cap. Furthermore, after sealing, electrical inspection and aging are possible in the same way as conventional packages, allowing for sufficient sorting. Therefore, after the above-mentioned selection, it is sufficient to mount separately selected chip carrier storage elements, and a high yield can be ensured.
第２図は他の回路パツケージの例を示す図で、
前記基板１の端子ピン２を取付けた面に前記論理
チツプ４のダイボンドを施こし、反対面にチツプ
キヤリアを搭載するようにしたことにより、より
一層の高密度実装を行つている。この場合、図に
示す如く、基板１のダイボンド部分にキヤビテイ
を設けることにより、端子ピン２の長さの増加を
最小限に抑えることが可能となる。 Figure 2 is a diagram showing an example of another circuit package.
The logic chip 4 is die-bonded to the surface of the substrate 1 on which the terminal pins 2 are attached, and the chip carrier is mounted on the opposite surface, thereby achieving even higher density packaging. In this case, as shown in the figure, by providing a cavity in the die-bonding portion of the substrate 1, it is possible to minimize the increase in the length of the terminal pins 2.
発明の目的
本発明は、冷却性能を低下させることなく、高
密度実装を実現した回路アセンブリを提供するこ
とにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a circuit assembly that achieves high-density packaging without reducing cooling performance.
発明の総括的な説明
本発明の要点は、裏面に多数の入出力ピンを有
するセラミツク配線基板に複数個の集積回路素子
を搭載する回路アセンブリにおいて、複数個の集
積回路素子の一部をチツプ状態で前記セラミツク
配線基板の裏面に直接搭載し、前記チツプ状態の
集積回路素子が搭載されたセラミツク基板裏面部
分に対向する表面部分に放熱用フインを設け、そ
の他のセラミツク配線基板の表面に他の集積回路
素子をそれぞれ独立した回路パツケージに格納し
た状態で搭載した点にある。General Description of the Invention The main point of the present invention is that in a circuit assembly in which a plurality of integrated circuit elements are mounted on a ceramic wiring board having a large number of input/output pins on the back side, some of the plurality of integrated circuit elements are mounted in a chip state. The ceramic wiring board is mounted directly on the back surface of the ceramic wiring board, heat dissipation fins are provided on the surface opposite to the back surface of the ceramic board on which the chip-state integrated circuit element is mounted, and other integrated circuits are mounted on the other surface of the ceramic wiring board. The main feature is that the circuit elements are housed in independent circuit packages.
より具体的には、チツプを裏面に直接搭載（セ
ラミツク基板に直付け）することで、いわゆるフ
エース・ダウン（Face down）形式となり、表
面に放熱フインを取り付けることでセラミツク基
板を通して効率よく熱放熱が可能とし、表面のそ
の余の領域にはパツケージを搭載するものであ
る。セラミツク基板のサイズがチツプサイズでは
なく、ピン数に依存する多ピンチツプは基板に直
接搭載し、他の入出力の少ない素子はチツプキヤ
リア化して、多ピンチツプのピン配置領域の裏面
を使つて、パツケージを搭載することにより、冷
却性能を低下させることなく、高密度実装を実現
するものである。 More specifically, by mounting the chip directly on the back side (directly attaching it to the ceramic substrate), it becomes a so-called face down format, and by attaching heat dissipation fins to the front side, heat can be efficiently dissipated through the ceramic substrate. The package can be mounted on the remaining area of the surface. The size of the ceramic substrate depends on the number of pins rather than the chip size.Multi-pin chips are mounted directly on the board, and other elements with few inputs and outputs are made into chip carriers, and the back side of the pin arrangement area of the multi-pin chip is used to mount the package. By doing so, high-density packaging can be achieved without reducing cooling performance.
発明の実施例
以下、本発明の実施例を第３図に基づき詳細に
説明する。第３図は本発明による回路アセンブリ
の断面図である。本実施例においては、第２図に
示した実施例においてダイボンドにより装着した
素子の消費電力が大きく、発熱量が大きい場合
に、チツプキヤリア面に放熱用のフイン６が取付
けられることを示している。Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to FIG. FIG. 3 is a cross-sectional view of a circuit assembly according to the present invention. This embodiment shows that when the element mounted by die bonding in the embodiment shown in FIG. 2 consumes a large amount of power and generates a large amount of heat, a heat dissipation fin 6 is attached to the chip carrier surface.
なお、上記実施例に示した、基板に直接搭載す
る素子とチツプキヤリア化素子との配列は一例で
あり、他の任意の配列が可能であることは言うま
でもない。 It should be noted that the arrangement of the elements directly mounted on the substrate and the chip carrier elements shown in the above embodiment is merely an example, and it goes without saying that any other arrangement is possible.
発明の効果
本発明は、このような構成を採用したことによ
り、チツプを裏面に直接搭載（セラミツク基板に
直付け）することで、いわゆるフエース・ダウン
（Face down）形式となり、表面に放熱フインを
取り付けることでセラミツク基板を通して効率よ
く熱放熱が可能となる。また、放熱フインの大き
さ（基板との接触面積）は、チツプサイズ＋基板
厚）程度でよいから、セラミツク基板裏面におけ
るチツプの端子ピンに必要な領域の上部まで広げ
る必要がなく、この領域にはパツケージを搭載す
ることが可能となる。セラミツク基板のサイズが
チツプサイズではなく、ピン数に依存する多ピン
チツプでは、このような領域を使つて、パツケー
ジを搭載することにより、冷却性能を低下させる
ことなく、高密度実装を実現することができる。Effects of the Invention By adopting such a configuration, the present invention allows the chip to be directly mounted on the back side (directly attached to the ceramic substrate), resulting in a so-called face down type, and heat dissipation fins are placed on the front side. By attaching it, it becomes possible to efficiently dissipate heat through the ceramic substrate. In addition, since the size of the heat dissipation fins (contact area with the board) can be as small as chip size + board thickness, there is no need to extend the heat dissipation fins to the top of the area required for the chip's terminal pins on the back surface of the ceramic board. It becomes possible to mount a package. For multi-pin chips where the size of the ceramic substrate depends on the number of pins rather than the chip size, by using this area to mount the package, high-density mounting can be achieved without reducing cooling performance. .
第１図Ａは回路アセンブリの一例を示す平面
図、第１図Ｂは第１図ＡのＡ−A′断面図、第２
図は回路アセンブリの他の例を示す断面図、第３
図は本発明による回路アセンブリを示す断面図で
ある。
１：配線基板、２：端子ピン、３：チツプキヤ
リア化された記憶素子、４：論理素子チツプ、
５：キヤツプ、６：フイン。
FIG. 1A is a plan view showing an example of a circuit assembly, FIG. 1B is a sectional view taken along line A-A' in FIG.
The figure is a sectional view showing another example of the circuit assembly.
The figure is a cross-sectional view of a circuit assembly according to the invention. 1: Wiring board, 2: Terminal pin, 3: Chip carrier memory element, 4: Logic element chip,
5: Cap, 6: Finn.
Claims (1)
配線基板に複数個の集積回路素子を搭載する回路
アセンブリにおいて、複数個の集積回路素子の一
部をチツプ状態で前記セラミツク配線基板の裏面
に直接搭載し、前記チツプ状態の集積回路素子が
搭載されたセラミツク基板裏面部分に対向する表
面部分に放熱用フインを設け、その他のセラミツ
ク配線基板の表面に他の集積回路素子をそれぞれ
独立した回路パツケージに格納した状態で搭載す
ることを特徴とする回路アセンブリ。 ２ 特許請求の範囲第１項の記載において、前記
セラミツク基板の裏面に設けられた凹部の中に、
前記チツプ状態の集積回路素子を搭載することを
特徴とする回路アセンブリ。[Claims] 1. In a circuit assembly in which a plurality of integrated circuit elements are mounted on a ceramic wiring board having a large number of input/output pins on the back surface, a part of the plurality of integrated circuit elements is mounted on the ceramic wiring board in a chip state. A heat dissipation fin is provided on the surface opposite to the back side of the ceramic substrate on which the integrated circuit element in chip form is mounted, and other integrated circuit elements are mounted independently on the surface of the other ceramic wiring board. A circuit assembly characterized in that it is mounted while being housed in a circuit package. 2. In the statement of claim 1, in the recess provided on the back surface of the ceramic substrate,
A circuit assembly comprising the integrated circuit element in a chip state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57049121A JPS58166755A (en) | 1982-03-29 | 1982-03-29 | Circuit assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57049121A JPS58166755A (en) | 1982-03-29 | 1982-03-29 | Circuit assembly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58166755A JPS58166755A (en) | 1983-10-01 |
| JPH046105B2 true JPH046105B2 (en) | 1992-02-04 |
Family
ID=12822227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57049121A Granted JPS58166755A (en) | 1982-03-29 | 1982-03-29 | Circuit assembly |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58166755A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2526515B2 (en) * | 1993-11-26 | 1996-08-21 | 日本電気株式会社 | Semiconductor device |
| US5642262A (en) | 1995-02-23 | 1997-06-24 | Altera Corporation | High-density programmable logic device in a multi-chip module package with improved interconnect scheme |
| JP4707446B2 (en) * | 2005-04-26 | 2011-06-22 | 富士通セミコンダクター株式会社 | Semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5619411Y2 (en) * | 1976-04-01 | 1981-05-08 | ||
| JPH027472Y2 (en) * | 1980-10-20 | 1990-02-22 | ||
| JPS5780836U (en) * | 1980-10-31 | 1982-05-19 | ||
| JPS5780837U (en) * | 1980-10-31 | 1982-05-19 | ||
| JPS5787544U (en) * | 1980-11-17 | 1982-05-29 | ||
| JPS5797961U (en) * | 1980-12-08 | 1982-06-16 |
-
1982
- 1982-03-29 JP JP57049121A patent/JPS58166755A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58166755A (en) | 1983-10-01 |
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