JPH0459959U - - Google Patents

Info

Publication number
JPH0459959U
JPH0459959U JP1990103964U JP10396490U JPH0459959U JP H0459959 U JPH0459959 U JP H0459959U JP 1990103964 U JP1990103964 U JP 1990103964U JP 10396490 U JP10396490 U JP 10396490U JP H0459959 U JPH0459959 U JP H0459959U
Authority
JP
Japan
Prior art keywords
power supply
buffer circuit
circuit
grounding
internal logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990103964U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990103964U priority Critical patent/JPH0459959U/ja
Publication of JPH0459959U publication Critical patent/JPH0459959U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す平面図、第２
図は従来の半導体集積回路の一例を示す平面図で
ある。 １，１Ａ……半導体基板、２……内部論理回路
、３……入力バツフア回路、４……出力バツフア
回路、５……入力用パツド、６……出力用パツド
、７，７Ａ，７Ｂ……電源用パツド、８，８Ａ，
８Ｂ……接地用パツド、９，９Ａ，９Ｂ……電源
配線、１０，１０Ａ，１０Ｂ……接地配線、１１
Ａ，１１Ｂ……容量素子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板上に設けられた、所定の論理処理を
    行う内部論理回路と、外部からの入力信号を前記
    内部論理回路へ伝達する入力バツフア回路と、前
    記内部論理回路の出力信号を外部回路へ供給する
    ための出力バツフア回路と、それぞれ所定の位置
    に互いに分離されて形成された第１及び第２の電
    源用パツドと、一端を前記第１の電源用パツドと
    接続し前記内部論理回路及び入力バツフア回路へ
    電源を供給する第１の電源配線と、一端を前記第
    ２の電源用パツドと接続し前記出力バツフア回路
    へ電源を供給する第２の電源配線と、前記第１及
    び第２の電源用パツドとそれぞれ対応する位置に
    互いに分離されて形成された第１及び第２の接地
    用パツドと、この第１の接地用パツドと前記内部
    論理回路及び入力バツフア回路の各接地端との間
    に形成された第１の接地配線と、前記第２の接地
    用パツドと前記出力バツフア回路の接地端との間
    に形成された第２の接地配線と、前記第１の電源
    配線、接地配線間及び前記第２の電源配線、接地
    配線間にそれぞれ形成された第１及び第２の容量
    素子とを有することを特徴とする半導体集積回路
    。
JP1990103964U 1990-10-01 1990-10-01 Pending JPH0459959U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990103964U JPH0459959U (ja) 1990-10-01 1990-10-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990103964U JPH0459959U (ja) 1990-10-01 1990-10-01

Publications (1)

Publication Number Publication Date
JPH0459959U true JPH0459959U (ja) 1992-05-22

Family

ID=31849052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990103964U Pending JPH0459959U (ja) 1990-10-01 1990-10-01

Country Status (1)

Country Link
JP (1) JPH0459959U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216592A (ja) * 2010-03-31 2011-10-27 Oki Semiconductor Co Ltd 半導体集積回路装置
JP2012109411A (ja) * 2010-11-17 2012-06-07 Canon Inc 半導体装置及び半導体装置を搭載したプリント基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552237A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor device
JPS617660A (ja) * 1984-06-21 1986-01-14 Toshiba Corp 半導体装置
JPS61264747A (ja) * 1985-05-20 1986-11-22 Matsushita Electronics Corp 半導体装置
JPH02121362A (ja) * 1988-10-31 1990-05-09 Seiko Epson Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552237A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor device
JPS617660A (ja) * 1984-06-21 1986-01-14 Toshiba Corp 半導体装置
JPS61264747A (ja) * 1985-05-20 1986-11-22 Matsushita Electronics Corp 半導体装置
JPH02121362A (ja) * 1988-10-31 1990-05-09 Seiko Epson Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216592A (ja) * 2010-03-31 2011-10-27 Oki Semiconductor Co Ltd 半導体集積回路装置
JP2012109411A (ja) * 2010-11-17 2012-06-07 Canon Inc 半導体装置及び半導体装置を搭載したプリント基板

Similar Documents

Publication Publication Date Title
JP2855975B2 (ja) 半導体集積回路
JPH0459959U (ja)
JPS62201949U (ja)
JPS6375876U (ja)
JPH0338639U (ja)
JPH0184460U (ja)
JPS60153032U (ja) 集積回路装置
JPH0180937U (ja)
JPH0284345U (ja)
JPH0183339U (ja)
JPH0341937U (ja)
JPS62134254U (ja)
JPS639137U (ja)
JPH0323934U (ja)
JPH0479447U (ja)
JPH0472651U (ja)
JPS6117745U (ja) Ｌｓｉパツケ−ジ
JPS6448035U (ja)
JPH0456340U (ja)
JPH03102747U (ja)
JPH01121946U (ja)
JPH06132497A (ja) 半導体メモリ
JPS58142941U (ja) Ｉｃパツケ−ジ
JPH05102310A (ja) 半導体集積回路における入出力バツフアーセル
JPS62116563U (ja)