JPH0338639U - - Google Patents

Info

Publication number
JPH0338639U
JPH0338639U JP1989099238U JP9923889U JPH0338639U JP H0338639 U JPH0338639 U JP H0338639U JP 1989099238 U JP1989099238 U JP 1989099238U JP 9923889 U JP9923889 U JP 9923889U JP H0338639 U JPH0338639 U JP H0338639U
Authority
JP
Japan
Prior art keywords
terminal pad
wiring
semiconductor integrated
internal logic
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989099238U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989099238U priority Critical patent/JPH0338639U/ja
Publication of JPH0338639U publication Critical patent/JPH0338639U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の第一の実施例を説明するため
のマイクロコンピユータのブロツク図、第２図は
本考案の第二の実施例を示すブロツク図、第３図
は従来のマイクロコンピユータのブロツク図であ
る。 １…ＩＣチツプ（マイクロコンピユータ）、２
…内部論理回路、３，４…入力バツフア、５，６
…出力バツフア、７，１１，１７…ＶＤＤ端子パ
ツド、９，１３，１９…ＧＮＤ端子パツド、８，
８′，１２，１２′，１８…ＶＤＤ配線、１０，
１０′，１４，１４′，２０…ＧＮＤ配線、１５
…入力信号端子パツド、１６…出力信号端子パツ
ド。

Claims (1)

    【実用新案登録請求の範囲】
  1. 入力バツフアと出力バツフアと内部論理回路を
    備える半導体集積回路において、出力バツフアに
    電源を供給するための電源端子パツドおよび配線
    が、入力バツフア、内部論理回路へ電源を供給す
    るための電源端子パツドおよび配線とは別に備え
    られていることを特徴とする半導体集積回路。
JP1989099238U 1989-08-24 1989-08-24 Pending JPH0338639U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989099238U JPH0338639U (ja) 1989-08-24 1989-08-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989099238U JPH0338639U (ja) 1989-08-24 1989-08-24

Publications (1)

Publication Number Publication Date
JPH0338639U true JPH0338639U (ja) 1991-04-15

Family

ID=31648295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989099238U Pending JPH0338639U (ja) 1989-08-24 1989-08-24

Country Status (1)

Country Link
JP (1) JPH0338639U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004068577A1 (ja) * 2003-01-27 2004-08-12 Matsushita Electric Industrial Co., Ltd. 半導体装置
KR20180136762A (ko) * 2017-06-15 2018-12-26 (주)착한음식 음식물 조리용 발열 용기

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004068577A1 (ja) * 2003-01-27 2004-08-12 Matsushita Electric Industrial Co., Ltd. 半導体装置
KR20180136762A (ko) * 2017-06-15 2018-12-26 (주)착한음식 음식물 조리용 발열 용기

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