JPH0456262A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH0456262A
JPH0456262A JP2167207A JP16720790A JPH0456262A JP H0456262 A JPH0456262 A JP H0456262A JP 2167207 A JP2167207 A JP 2167207A JP 16720790 A JP16720790 A JP 16720790A JP H0456262 A JPH0456262 A JP H0456262A
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
substrate
semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2167207A
Other languages
English (en)
Inventor
Susumu Sanai
佐内　進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2167207A priority Critical patent/JPH0456262A/ja
Publication of JPH0456262A publication Critical patent/JPH0456262A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路設置、特にその３次元の構造に
関するものである。
従来の技術 半導体集積回路は通常、基板上に１個又は数個、半導体
チップを配置する２次元構造である。
発明が解決しようとする課題 従来の２次元構造の集積回路装置では、半導体を多数用
いると、機器が太き（なる問題がある。
また半導体と半導体を結ぶ配線の長さによる負荷等で、
機器のスピードが遅くなる問題があった。
本発明は、半導体集積回路装置を用いた装置の小型化と
装置の電気的特性の向上を目的とする。
課題を解決するための手段 半導体のチップを基板上に２つ以上積み重ねた構造にし
、基板と１番目のチップとボンディングし、さらに２番
目、３番目、ｎ番目のチップと基板をボンディングする
ことにより構成される３次元の半導体集積回路装置であ
る。
作用 多層構造の集積回路装置にすることにより、面積あたり
の集積度が向上し、またチップ間の配線長が従来より短
くなるため、電気特性を向上させることができる。
実施例 以下本発明の実施例について添付図面に基づき説明する
。第１図は本発明の半導体集積回路装置の断面図である
。この装置は、半導体チップ１゜２．３を、それぞれ、
基板４のＡｕ薄膜１０上に積み重ねて接着し、ボンディ
ングワイヤ５でチップと基板４上の配線６を接続する。
このチップ上を樹脂７でハードコートする。ただし、基
板上のボンディング部分を除く。次にチップ２を接着剤
８を用いて接着し、ボンディングでチップ２と基板４上
の配線６とを接続する。同様な工程を繰り返すことによ
ってチップ３も基板４上の配線６と接続される。最後に
全体を樹脂９でおおうことによって製品が得られる。な
お、図中の符号１０は金（Ａｕ）の膜を示し、これは、
Ａｕのほか、他の金属導電薄膜であってもよい。
第２図は半導体集積回路の基板を電源電圧又はアースに
接続した実施例である。半導体チップ１は前記の方法と
同様にして、基板４上の配線６に接続される。樹脂７で
ハードコートした後に、Ａｕ又は他の金属による導電薄
膜１１を設け、半導体チップ２をこの膜上に接着した後
に、配線６と導電薄膜１１とをボンディングする。他の
工程は前記の実施例と同様である。導電薄膜１１を設け
ることにより、チップ１と同様にチップの基板を電源ま
たはアースに接続することができる。
この方法を用いることにより、チップを２個以上積層す
ることができる。
またチップ間の結線長が本発明では数關であるのに対し
、通常のパッケージされた集積回路では数ｃｍ以上と長
い。このため、従来と比較して回路の特性が向上した。
以上の実施例より、本発明の半導体集積回路装置は、半
導体チップを積層することができ、高密度化を図ること
ができる。
発明の効果 本発明によると、半導体集積回路装置の面積あたりの集
積度が向上するため、機器の小型化が図れる。またチッ
プを積層しているため、チップ間の配線距離が短くなる
ため、機器の電気的スピードのアップを図ることができ
る。見かけ上、大チップ（３０ｍ＋＋口以上）を用いた
集積回路装置とほぼ同じ効果がある。
【図面の簡単な説明】
第１図、第２図はそれぞれ本発明の各実施例半導体集積
回路装置の断面図である。 （２．３・・・・・・半導体チップ、４・・・・・・基
板、５・・・・・・ボンディングワイヤ、６・・・・・
・基板上の配線、７・・・・・・樹脂、８・・・・・・
接着剤、９・・・・・・樹脂、１０・・・・・・Ａｕの
膜、１１・・・・・・導電薄膜。 代理人の氏名　弁理士　粟野重孝　ほか１名第１図 第　２　図

Claims (4)

    【特許請求の範囲】
  1. （１）半導体のチップを２つ以上積み重ねた多層構造を
    特徴とする半導体集積回路装置。
  2. （２）基板上に、半導体のチップ、樹脂の順に積層した
    ことを特徴とする請求項（１）記載の半導体集積回路装
    置。
  3. （３）基板上に、半導体のチップを接着し、前記チップ
    と基板をボンディングした後に、表面にハードコート処
    理を基板上のボンディング部分を除いて施し、この処理
    の後に、半導体チップを前記チップ上に接着し、ボンデ
    ィングを２番目のチップと基板間で行い、さらに表面を
    ハードコート処理し、チップを接着するという方法で半
    導体チップを２つ以上積層した構造を特徴とする請求項
    （２）記載の半導体集積回路装置。
  4. （４）半導体チップ上にハードコート処理をした後、こ
    の表面上に金属の薄膜を設けた構造である請求項（３）
    記載の半導体集積回路装置。
JP2167207A 1990-06-25 1990-06-25 半導体集積回路装置 Pending JPH0456262A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2167207A JPH0456262A (ja) 1990-06-25 1990-06-25 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2167207A JPH0456262A (ja) 1990-06-25 1990-06-25 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH0456262A true JPH0456262A (ja) 1992-02-24

Family

ID=15845410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2167207A Pending JPH0456262A (ja) 1990-06-25 1990-06-25 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH0456262A (ja)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
WO1997011492A1 (fr) * 1995-09-20 1997-03-27 Hitachi, Ltd. Dispositif a semi-conducteurs et son procede de fabrication
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
WO1999018611A1 (en) * 1997-10-08 1999-04-15 Cardiac Pacemakers, Inc. Stacked integrated circuits using tape automated bonding within an implantable medical device
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
USRE36613E (en) * 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
EP1045443A2 (en) * 1999-04-14 2000-10-18 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6189402B1 (en) 1997-12-09 2001-02-20 Isuzu Motors Limited Gear transmission
US6339255B1 (en) * 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7023079B2 (en) * 2001-03-01 2006-04-04 Advanced Semiconductor Engineering, Inc. Stacked semiconductor chip package
JP2006093554A (ja) * 2004-09-27 2006-04-06 Sanyo Electric Co Ltd 半導体集積回路装置
WO2006106569A1 (ja) * 2005-03-31 2006-10-12 Spansion Llc 積層型半導体装置及びその製造方法
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
JP2007158244A (ja) * 2005-12-08 2007-06-21 Fujitsu Ltd 半導体装置に配設される中継部材、半導体装置、及び半導体装置の製造方法
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
USRE40112E1 (en) * 1999-05-20 2008-02-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US7615856B2 (en) 2004-09-01 2009-11-10 Sanyo Electric Co., Ltd. Integrated antenna type circuit apparatus
US7829379B2 (en) 2007-10-17 2010-11-09 Analog Devices, Inc. Wafer level stacked die packaging
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
USRE36613E (en) * 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
WO1997011492A1 (fr) * 1995-09-20 1997-03-27 Hitachi, Ltd. Dispositif a semi-conducteurs et son procede de fabrication
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
WO1999018611A1 (en) * 1997-10-08 1999-04-15 Cardiac Pacemakers, Inc. Stacked integrated circuits using tape automated bonding within an implantable medical device
US6189402B1 (en) 1997-12-09 2001-02-20 Isuzu Motors Limited Gear transmission
US6339255B1 (en) * 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6500698B2 (en) 1998-10-24 2002-12-31 Hynix Semiconductor, Inc. Method for fabricating a stacked semiconductor chip package
EP1045443A2 (en) * 1999-04-14 2000-10-18 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
USRE40112E1 (en) * 1999-05-20 2008-02-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6650019B2 (en) 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US7023079B2 (en) * 2001-03-01 2006-04-04 Advanced Semiconductor Engineering, Inc. Stacked semiconductor chip package
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7615856B2 (en) 2004-09-01 2009-11-10 Sanyo Electric Co., Ltd. Integrated antenna type circuit apparatus
JP2006093554A (ja) * 2004-09-27 2006-04-06 Sanyo Electric Co Ltd 半導体集積回路装置
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