JPH0444970B2 - - Google Patents

Info

Publication number
JPH0444970B2
JPH0444970B2 JP60178485A JP17848585A JPH0444970B2 JP H0444970 B2 JPH0444970 B2 JP H0444970B2 JP 60178485 A JP60178485 A JP 60178485A JP 17848585 A JP17848585 A JP 17848585A JP H0444970 B2 JPH0444970 B2 JP H0444970B2
Authority
JP
Japan
Prior art keywords
address
register
data
data memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60178485A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6160133A (ja
Inventor
Eru Satsukusu Chaaruzu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of JPS6160133A publication Critical patent/JPS6160133A/ja
Publication of JPH0444970B2 publication Critical patent/JPH0444970B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Advance Control (AREA)
JP60178485A 1984-08-15 1985-08-13 アドレス算出装置 Granted JPS6160133A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US641098 1984-08-15
US06/641,098 US4704680A (en) 1984-08-15 1984-08-15 Address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle

Publications (2)

Publication Number Publication Date
JPS6160133A JPS6160133A (ja) 1986-03-27
JPH0444970B2 true JPH0444970B2 (US06272168-20010807-M00014.png) 1992-07-23

Family

ID=24570924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60178485A Granted JPS6160133A (ja) 1984-08-15 1985-08-13 アドレス算出装置

Country Status (7)

Country Link
US (1) US4704680A (US06272168-20010807-M00014.png)
JP (1) JPS6160133A (US06272168-20010807-M00014.png)
CA (1) CA1223664A (US06272168-20010807-M00014.png)
DE (1) DE3507584A1 (US06272168-20010807-M00014.png)
FR (1) FR2569288B1 (US06272168-20010807-M00014.png)
GB (1) GB2163280B (US06272168-20010807-M00014.png)
NL (1) NL8500683A (US06272168-20010807-M00014.png)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3619036A1 (de) * 1986-06-06 1987-12-10 Wajda Eligiusz Dipl Ing Verfahren zur steuerung von datenverarbeitenden einrichtungen
US5159686A (en) * 1988-02-29 1992-10-27 Convex Computer Corporation Multi-processor computer system having process-independent communication register addressing
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
JP2617974B2 (ja) * 1988-03-08 1997-06-11 富士通株式会社 データ処理装置
US5163149A (en) * 1988-11-02 1992-11-10 International Business Machines Corporation Combining switch for reducing accesses to memory and for synchronizing parallel processes
DE69125874T2 (de) * 1990-02-21 1997-11-20 Matsushita Electric Ind Co Ltd Generator für mehrdimensionale Adressen und Anordnung zum Steuern desselben
US5265225A (en) * 1990-02-21 1993-11-23 Harris Corporation Digital signal processing address sequencer
US5832533A (en) * 1995-01-04 1998-11-03 International Business Machines Corporation Method and system for addressing registers in a data processing unit in an indexed addressing mode
US6047364A (en) * 1997-08-27 2000-04-04 Lucent Technologies Inc. True modulo addressing generator
US5983333A (en) * 1997-08-27 1999-11-09 Lucent Technologies Inc. High speed module address generator
US6049858A (en) * 1997-08-27 2000-04-11 Lucent Technologies Inc. Modulo address generator with precomputed comparison and correction terms
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6892237B1 (en) 2000-03-28 2005-05-10 Cisco Technology, Inc. Method and apparatus for high-speed parsing of network messages
US6505269B1 (en) 2000-05-16 2003-01-07 Cisco Technology, Inc. Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
WO2001090888A1 (en) * 2000-05-23 2001-11-29 Theis Jean Paul A data processing system having an address generation unit with hardwired multidimensional memory indexing support

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965377A (ja) * 1982-10-05 1984-04-13 Nippon Telegr & Teleph Corp <Ntt> アドレス制御方法およびその装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852265B2 (ja) * 1977-01-12 1983-11-21 株式会社日立製作所 デ−タ処理装置
US4130868A (en) * 1977-04-12 1978-12-19 International Business Machines Corporation Independently controllable multiple address registers for a data processor
JPS54127653A (en) * 1978-03-28 1979-10-03 Toshiba Corp Data processor
US4365292A (en) * 1979-11-26 1982-12-21 Burroughs Corporation Array processor architecture connection network
US4370732A (en) * 1980-09-15 1983-01-25 Ibm Corporation Skewed matrix address generator
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
DE3483489D1 (de) * 1983-04-13 1990-12-06 Nec Corp Speicherzugriffseinrichtung in einem datenverarbeitungssystem.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965377A (ja) * 1982-10-05 1984-04-13 Nippon Telegr & Teleph Corp <Ntt> アドレス制御方法およびその装置

Also Published As

Publication number Publication date
DE3507584C2 (US06272168-20010807-M00014.png) 1988-10-20
GB8504822D0 (en) 1985-03-27
NL8500683A (nl) 1986-03-03
US4704680A (en) 1987-11-03
GB2163280B (en) 1988-06-08
FR2569288B1 (fr) 1990-12-14
DE3507584A1 (de) 1986-02-27
JPS6160133A (ja) 1986-03-27
FR2569288A1 (fr) 1986-02-21
GB2163280A (en) 1986-02-19
CA1223664A (en) 1987-06-30

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