JPH0442696B2 - - Google Patents

Info

Publication number
JPH0442696B2
JPH0442696B2 JP60036171A JP3617185A JPH0442696B2 JP H0442696 B2 JPH0442696 B2 JP H0442696B2 JP 60036171 A JP60036171 A JP 60036171A JP 3617185 A JP3617185 A JP 3617185A JP H0442696 B2 JPH0442696 B2 JP H0442696B2
Authority
JP
Japan
Prior art keywords
transfer
address
data
logical address
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60036171A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61195447A (ja
Inventor
Isamu Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60036171A priority Critical patent/JPS61195447A/ja
Publication of JPS61195447A publication Critical patent/JPS61195447A/ja
Publication of JPH0442696B2 publication Critical patent/JPH0442696B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
JP60036171A 1985-02-25 1985-02-25 デ−タ転送制御方式 Granted JPS61195447A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60036171A JPS61195447A (ja) 1985-02-25 1985-02-25 デ−タ転送制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60036171A JPS61195447A (ja) 1985-02-25 1985-02-25 デ−タ転送制御方式

Publications (2)

Publication Number Publication Date
JPS61195447A JPS61195447A (ja) 1986-08-29
JPH0442696B2 true JPH0442696B2 (enrdf_load_stackoverflow) 1992-07-14

Family

ID=12462302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60036171A Granted JPS61195447A (ja) 1985-02-25 1985-02-25 デ−タ転送制御方式

Country Status (1)

Country Link
JP (1) JPS61195447A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS61195447A (ja) 1986-08-29

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term